Abstract: Disclosed is a limiting amplifier for amplifying an input signal including at least first portions having a first amplitude and second portions having a second amplitude being lower than said first amplitude. The amplifier includes a first peak detector for detecting the current maximum value in the input signal. The amplifier also includes a second peak detector for detecting the current minimum value in the input signal. The amplifier also includes determining means for providing a first decision that a variation in the input signal is due to a variation in a first amplitude and/or a second amplitude, or a second decision that a variation in the input signal is due to a transition from a first portion to a second portion, a third decision that a variation in the input signal is due to a transition from a second portion to a first portion, and controlling meats for either activating or inactivating one of the decreasing means and the increasing means based on the decision.

Abstract: In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.

Abstract: An electronic system with semiconductor components allows electronic circuits with conventional semiconductor components to be used, having minimal supply voltages to guarantee stable operation, lowering said minimum supply voltages. The range of supply voltages of such a circuit for which operation is stable can be extended towards low values by the effect of mutual compensation of the respective behaviors of said semiconductor components in their respective transition regions.

Abstract: A frequency margin testing blade is adapted for use in a bladed server. The testing blade is further adapted to provide one or more output clock signals for use as clock inputs to one or more server blades internal to the bladed server in which the testing blade is installed and/or one or more server blades external to the bladed server in which the testing blade is installed.

Abstract: A configurable feedback path is included in an amplitude control system having a signal source and an amplitude controller, and provides accurate tracking between a signal provided at a test port and a reference signal, whether or not the configurable feedback path is in an internally-leveled configuration or an externally-leveled configuration. The configurable feedback path includes a series of access ports, a detector that has an input coupled to the first access port, a filtered output coupled to the amplitude controller, and an unfiltered output providing the reference signal. The configurable feedback path also includes a signal separator that has an input terminal coupled to the signal source, a thru-terminal coupled to the third access port, and a coupled terminal that is coupled to the second access port. The fourth access port is coupled to the test port.

Abstract: In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.

Abstract: An extended range variable gain amplifier is described. The variable gain capability is achieved by replacing differential pair amplifiers having an input signal with less attenuation with one having an input signal that is more attenuated. This replacement continues until only ten differential pair amplifiers are remaining. At this point, if less gain is desired, differential pair amplifiers are turned off, but are not replaced. A minimum number of amplifiers will remain on.

Abstract: A circuit configuration for potential-free signal transmission has a transformer with a primary winding and a secondary winding. A drive circuit is connected upstream of the primary winding and a selection circuit is connected up to the secondary winding and is driven by pulses. A latching circuit is connected downstream of the selection circuit and prevents a forwarding of second pulses under specific conditions. Finally, a storage element generates an output signal.

Abstract: An apparatus and method for a DC-DC charge pump voltage converter-regulator circuit includes a control circuit, a multiplier circuit, and a feedback circuit. The feedback circuit includes a load circuit, a comparator circuit, and a voltage reference circuit. The multiplier circuit produces an output signal by multiplying a supply signal according to a multiplication factor. The output signal is communicated to the load circuit. The output signal is measured producing a sense signal. The voltage reference circuit produces a reference voltage. The control circuit regulates the output signal according the result of a comparison between the sense signal and the reference voltage. In one embodiment, the multiplication factor is adjusted to compensate for a change in the supply signal. The multiplication factor may be increased to compensate for a decrease in the supply signal.

Abstract: Programmable voltage pump for producing an output voltage includes a trim input configured to set the output voltage, an output configured to emit the output voltage therefrom, and an activation/deactivation input configured to at least one of activate and deactivate the voltage pump. The activation/deactivation input includes a switch connected to the output, the switch configured to selectively connect a network to ground, the network being connected to the output.

Abstract: An ultrashort pulse amplifier produces high-power ultrafast laser pulses. Pulses first have net negative (i.e. blue to red) chirp applied, and are then amplified in a laser amplifier. After amplification, the pulses are compressed using propagation through a block of material or other convenient optical system with a positive sign of chromatic dispersion. High-order dispersion correction may also be included.

Abstract: a limiting amplifier with a power detection circuit (100) comprises an amplification section having a plurality of amplification inverters (INV1−INVn+1), a detection inverter (INV0) taking in and inverting an output potential of any of the amplification inverters, a diode (170) having an anode connected to an output of the detection inverter, and a detection resister (180) and a capacitor (190) connected in parallel between a cathode of the diode and a ground line. The output voltage of the inverter (INV0) is not reduced by a schottky current and, therefore, an output potential of the inverters INVn−1 is sufficiently amplified and the precise power detection is performed even if an amplitude of an input signal is high.

Abstract: An SCSI circuit which allows for the independent control of driver slew rate and amplitude with a linear shaped driver output voltage. The circuit comprises 1) a symmetrical H-Driver having at least four predrive controls; and 2) a predrive control circuit coupled to one of the predrive controls for independently varying the amplitude and rise time. The SCSI circuit is designed to utilize minimal space on the IO circuit pad, thereby conserving the amount of space allotted by the silicon area on the integrated circuit chip.

Abstract: A signal amplitude limiting circuit includes a differential circuit, a feed back circuit and a voltage supply circuit. The differential circuit has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal. The feedback circuit is connected to the first differential circuit. The feedback circuit compares voltages at the positive and negative output terminals with a reference voltage and outputs a comparison signal in response to the comparison. The voltage supply circuit is connected to the differential circuit and the feedback circuit. The first voltage supply circuit provides a current to the differential circuit in response to the comparison signal.

Abstract: Programmable voltage pump for producing an output voltage includes a trim input configured to set the output voltage, an output configured to emit the output voltage therefrom, and an activation/deactivation input configured to at least one of activate and deactivate the voltage pump. The activation/deactivation input includes a switch connected to the output, the switch configured to selectively connect a network to ground, the network being connected to the output.

Abstract: An in-line distortion generator for coupling in-line with a non-linear device (NLD) produces an output signal of useful amplitude, but with low composite second order, composite triple beat and cross modulation distortions. The distortion generator comprises an instant controlled non-linear attenuator which utilizes the non-linear current flowing through a pair of diodes, in parallel with a resistor and an inductor, to provide the proper amount of signal attenuation over the entire frequency bandwidth. The distortion generator circuitry is always matched to the NLD, thereby ensuring a frequency response that is predictable and predefined. The distortion generator may also include a temperature compensation circuit to ensure consistent operation throughout a wide temperature range.

Abstract: The invention relates to an evaluation device (4) connected to the output of an A/D converter (3) for comparing the direct component of a digitally converted input signal having a threshold value and at least one power source (13, 14, 17, 18) that may be connected to the differential input (1) by the evaluation device (4) in such a way that the differential input (1) can be loaded or unloaded with a current to increase or reduce the direct component in the direction of the threshold value.

Abstract: Method and apparatus are provided for processing a wide dynamic range analog signal which comprises a compressive nonlinear transfer function responsive to the average amplitude of the signal without feedback along the signal path. The invention employs frequency selective filtering and expansion of the compressed signal. The invention is applicable to any analog signal system having a plurality of channels carrying related signal information.

Abstract: A device which uses a detection circuit to determine whether an output current thereof is source-induced or load-induced, and the method therefor. The device which performs some type of operation based upon the determination as to whether the output current thereof is source-induced or load-induced, and method therefor. The detection circuit determines whether polarities of the output current and an output voltage are the same, and determines the output current to be source-induced if the polarities are the same and load-induced if the polarities are opposite each other. Such a device may have many applications, including use in systems where distinctions between source and load-induced currents are employed in feedback systems to control the system voltage source, systems where the system voltage source is not controlled, but other sources are controlled to influence a summation of voltages and currents at sensing locations, and systems for measurement instrumentation.

Abstract: A high-voltage capacitive voltage divider circuit includes a high-voltage Silicon-On-Insulator (SOI) capacitor connected between a high-voltage terminal and a low-voltage terminal, and a low-voltage SOI capacitor connected between the low-voltage terminal and a common terminal. The voltage divider circuit also includes control circuitry for processing a signal generated at the low-voltage terminal in order to provide voltage-related control of a larger circuit employing the voltage divider circuit. The high-voltage SOI capacitor can include an oxide layer on a substrate, with a thinned drift region on the oxide layer, a thick oxide layer over the thinned drift region, and an electrode layer over the thick oxide layer, with the electrode layer and the thinned drift region forming capacitor plates insulated from each other by the thick oxide layer.

Abstract: A circuit arrangement for generating specific waveforms includes a controllable voltage transformer circuit for generating an output signal (VOUT) with a specific waveform, which increases the voltage of its output signal depending on a first control signal (VH) or reduces it depending on a second control signal (VL). The arrangement also includes a control unit that generates the first and second control signal (VH, VL) for the voltage transformer circuit depending on a reference signal (VREF) in the form of an open-loop control or in the form of a closed-loop control.

Abstract: Disclosed is a programmable impedance driver that includes two sets of impedance devices, two primary counters and two test counters. The primary counters selectively activate individual ones of the impedance devices to vary an overall impedance of the driver and the test counters verify the counting operation of the primary counters during manufacturing testing of the driver. Therefore, the built-in self-test (BIST) aspect of the invention easily detects if one of the counters will become stuck during normal usage.

Abstract: A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection circuit. The SOI ESD protection circuit has a first and a second diode, a first and a second NMOS transistor and a first and a second PMOS transistor. The input terminal of the first diode is coupled to the bonding pad while the output terminal is coupled to a voltage source. The input terminal of the second diode is coupled to an earth voltage while the output terminal is coupled to the bonding pad. Both the source terminal and the gate terminal of the first NMOS transistor are coupled to the earth voltage. The drain terminal of the first NMOS transistor is coupled to the voltage source. Both the source and the gate terminal of the second NMOS transistor are coupled to the earth voltage. Both the source and the gate terminal of the first PMOS transistor are coupled to the voltage source. The drain terminal of the first PMOS transistor is coupled to the substrate of the first NMOS transistor.

Abstract: A step attenuator for use in attenuating an electromagnetic signal. The step attenuator includes a first path having a plurality of attenuator structures provided therein, each attenuator structure being selectively actuated to permit the signal to pass therethrough. A second path is disposed in parallel with the first path, the second path permitting the signal to selectively bypass the first path. A third path is disposed in series with the first and second paths and includes at least one attenuator structure that is selectively actuated to permit the signal to pass therethrough.

Abstract: A network protector includes a coil drive circuit for the trip actuator which operates as a current limiter to protect a trip coil with limited impedance at the upper limit of network voltage while assuring operation at network voltages of less than 10% rated voltage. A comparator provides gate drive current to a FET connected in series with the trip coil as long as coil current is below a reference voltage proportional to a specified maximum value of coil current. When the specified value of coil current is reached, the FET is latched off until the network protector is tripped open again.

Abstract: A bus coupling includes an amplitude-controlled transmission circuit for generating a substantially rectangular active pulse for a transmission pulse including an active pulse and an equalizer pulse for a bus system which guides alternating voltage data and direct voltage in order to prepare a vehicle wiring system voltage for user terminals, in particular for the bus of the European Installation Bus Association. The transmission circuit operates with a transmission circuit operates with a transmission stage which includes as a transmission transistor, a transmission valve functioning as a transistor in the transmission circuit. Depending on the function, the selection line of this transmission circuit is reduced in terms of the control signal by a transistor of the inverse type to the transistor in the collector circuit as reducing transistor.

Abstract: A programming method (250) for digitally programming the adjustment of an electronic trim capacitor (212, 314, 414). In an initial step (252), programming is initiated by setting an enable terminal (224). In subsequent steps (254, 256) a pulse signal (226) then applied to a program terminal (222) and the number of pulses (228) provided to the programming terminal (222) while the enable terminal (224) is set determines the total number of capacitance increments for which the electronic trim capacitor (212, 314, 414) is programmed. The electronic trim capacitor (212, 314, 414) may be incorporated into an integrated circuit (12, 312) or a module (412) and the electronic trim capacitor (212, 314, 414) may be programmed and used “in situ” in a more general circuit (1) such as an oscillator (301) or an amplifier (401).

Abstract: A method is disclosed for conditioning a periodic analog signal (SIN, COS) to predetermined, positive and negative desired peak values by adjusting the signal (SIN, COS) using multiplicative correcting steps, which increase or decrease the signal amplitude, and additive correcting steps, adding to the signal a constant which adjusts the signal level in a positive or negative direction, wherein the presence of a current actual peak value is detected said method providing that the difference between the actual peak value and the predetermined desired peak value is stepwise reduced by repeated adjustment of the signal (SIN, COS) using modifying steps within a part of a period of the signal (SIN, COS), each modifying step including exactly one multiplicative and exactly one additive correcting step.

Abstract: A termination impedance in a semiconductor circuit is trimmed to fall within a desired range by a trimming circuit such that the amount of variation in the termination impedance is less than the variation in the sheet rho (resistivity) of the semiconductor. An external reference resistor causes a reference current to flow in multiple branches of a current mirror circuit. One branch of the current mirror circuit has a resistance less than the reference resistor, another has a resistance approximately equal to the reference resistor, and another has resistance greater than the reference resistor. Variation in the sheet rho results voltage drops across the resistor in variation in the resistor values. A logic circuit detects the variations, and encodes a control signal. The control signal is received by a variable termination circuit that switches parallel resistance branches in or out of the termination impedance circuit such that an effective termination impedance is selected based upon the control signal.

Abstract: The small swing output buffer of the present invention comprises, for example, four transistors or FETs; P1, P2, N1, and N2. The source of P2 is connected to Vcc and the drain of P2 is connected to the source of P1. The drain of PI is connected to the source of N1. The drain of N1 is connected to the source of N2. The drain of N2 is connected to ground. The input signal to the output buffer is fed into input IN which is connected to the gates of P1 and N1. The output of the output buffer is output OUT which is connected to the drain of P1 and the source of N1. For the small swing output buffer, when the input signal is at a high potential, P1 and P2 are turned off and N1 and N2 are turned on which pulls down the potential of OUT towards ground potential. Since FETs have a threshold voltage, the potential of the output OUT cannot be completely pulled to ground potential. Therefore, the potential of the output OUT when the input signal applied to IN is a high potential, is the threshold voltage (Vt) of N2.

Abstract: A phase stable clock circuit includes a phase gate having track-and-hold (T/H) circuits with each T/H circuit receiving a phase shifted continuous sinusoidal signal of predetermined phase and a control input signal to capture and hold phase samples of the sinusoidal signals. In alternative embodiments, a phase correction circuit provides phase correction values that are added to the held phase values to generate corrected phase values and time-error phase lookup table is used to generate time position correction values. The corrected phase values are applied to the phase gate remove deterministic phase errors to generate an output signal with a predetermined startup phase relative to the control input signal transition. The phase error-to-time lookup table adjusts the time placement of waveform record samples after the acquisition of the samples.

Abstract: A predistortion circuit (102) includes a signal splitter (114), a diode network (118) and a signal combiner (116). The signal splitter (114) is splits an input signal into two portions. One of the signal portions is passed through the diode network (118) and combined with the other portion of the input signal in the signal combiner (116). The diode network (118) includes a plurality of diode circuits (204,206), each including two diode branches (208-214) coupled to an electrical ground (220). The resulting predistorted signal at the output (106) of the signal combiner is amplified, amplitude adjusted and injected into the nonlinear device (112). The input signal is predistorted such that distortion due to nonlinear characteristics of the nonlinear device (112) is reduced.

Abstract: A maximum voltage bias control circuit (22) is provided which accepts two supply voltages (Vbatt and Vout) and determines the maximum voltage. The maximum voltage is then applied to terminal (Vmax) with current drivers (46,50) used to provide additional current drive to terminal (Vmax). PMOS transistors (40,42) are used to provide proper N-Well bias control of PMOS transistors (40, 42, 46 and 50).

Abstract: A filter circuit extracts a desired signal in the presence of interference by using a variable gain circuit whose input is the frequency converted received signal and whose output is fed through an active filter to produce the desired signal. The signal levels before and after the active filter are detected and the higher level is used to control the gain of the variable gain circuit.

Abstract: A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second output signal.

Abstract: An embodiment of the invention is directed to a buffer circuit having a closed loop negative feedback amplifier that is coupled to continuously drive a node to a predetermined set voltage. A precharge circuit is coupled to selectively drive the node at a higher rate than the amplifier. The buffer circuit is particularly useful for reducing the recovery and settling time of the node voltage when the node is suddenly subjected to a large, capacitive load.

Abstract: A DC-coupled data slicer operates on a baseband signal based on a variable threshold and an AC-coupled data slicer operates on the baseband signal based on a fixed threshold. The variable threshold is initially set to a stored threshold value corresponding to a previously used value of the variable threshold. Differences between DC-coupled sliced data and the AC-coupled sliced data are determined and used to adjust the variable threshold. In one embodiment, the AC-coupled data slicer is characterized by a settling time constant. The variable threshold is not adjusted until expiration of a predetermined delay preferably set to be a multiple of the settling time constant. After expiry of the predetermined delay, adjustments to the variable threshold are made to correct any detected variances in the expected duty cycle of the DC-coupled data slicer output. In this manner, the present invention overcomes the problems resulting from settling times inherent in prior art techniques.

Abstract: A first circuit which is constituted by a thin film resistor is connected between the collector of a transistor and a power supply terminal, and a second circuit which is constituted by a semiconductor resistor is connected between the emitter of the transistor and a grounding terminal. The film thickness of a thin film resistor is set to not more than its skin depth at a frequency to be compensated for.

Abstract: Disclosed herein is a level conversion circuit which operates at high speeds even at a low power-supply voltage. The level conversion circuit is largely constituted by an emitter follower section 101, an amplitude amplification section 102, and a level conversion section 103.

Abstract: An input signal is phase-inverted to supply the inverted signal to a gate of an FET. When the gate-source voltage Vgs decreases, the differential resistance Rds of the FET increases. Moreover, the differential resistance Rds also increases when the drain-source voltage Vds increases. That is, if the magnitude of the input signal from the signal source (2) increases, the gate-source voltage Vgs decreases and the drain-source voltage Vds increases, so that the differential resistance Rds varies largely. This compensates the non-linearity of the following saturation amplifier. Phase compensation is also effected with a capacitor (stray capacitor) or an inductor connected in parallel to the FET in corporation of the phase inverter. The phase inverter may be structured using the stray capacitances of the FET.

Abstract: An integrated device having a pad receiving, in a standard operative condition, an input signal having a first value and, in a test operative condition, a test voltage having a second value higher than the first value; an input stage connected to the pad and including an electronic component having a first terminal connected to the pad; a third-level detecting stage connected to the pad and supplying a logic third-level signal having a first level in presence of the input signal and a second level in presence of the test voltage; and a selector connected to a second terminal of the electronic component and structured to connect the second terminal to a reference potential in the presence of the first logic level of the third-level signal and to a biasing voltage higher than the reference potential and lower than the second value in the presence of the second logic level of the third-level signal.

Abstract: A circuit to reduce the temperature-dependence of a predistorter diode in a predistorter for an external optical modulator characterized in that a predistorter diode (D1, D2) is connected in series with an ohmic resistance (Rv) and the series circuit is fed from a power supply in operation, whereby the voltage V1 of the power supply and the ohmic resistance are selected such that when the temperature of the predistorter changes the curvature of the temperature-dependent current-voltage curve for the predistorter diode hardly varies at the respective operating point. One advantage of the invention is the very simply type of compensation that it allows.

Abstract: A DC drift canceller circuit is disclosed. The circuit includes a decision device including an input and an output and a first adder configured to received the input and the output of the decision device. The first adder produces an error signal indicative of the difference between the input and output of the decision device. A noise filter of the circuit is configured to receive the error signal. A second adder of the circuit includes a first input coupled to the input of the canceller circuit and a second input coupled to the output of the noise filter such that the output of the second adder is substantially free of any DC drift component of the input signal. The output of the second adder is coupled to the input of the decision device. In one embodiment, the decision device comprises a slicer. In one embodiment, the noise filter comprises a low pass filter.

Abstract: The invention presents a circuit by which control of the output amplitude of digital analog converters can be carried out at high speed and with high precision. A first digital signal that is the same as the input signal and a second digital signal of a value slightly smaller than an input signal provided from a high-speed processor are selectively applied to plural D-A converters and the output therefrom is added. By changing the ratio with which the first digital signal and the second digital signal are selected, it is possible to control the analog output amplitude.

Abstract: A magnetic-field-to-voltage transducer includes a Hall element and a digitally gain-controlled Hall-voltage amplifier that produces an analog voltage Vsig having excursions of one polarity corresponding to the passing of magnetic articles. Vsig is applied to the input of a peak-referenced-threshold signal detector that generates a binary proximity-detector output voltage, Vout, having transitions of one direction upon approaches of gear teeth down to zero speed. A digitally gain-controlled amplifier is connected to the Hall element. A comparator circuit generates a binary signal Vbig (or Vtoobig) that changes from one to another binary level each time that Vsig exceeds a DC target voltage, VTG. The AGC circuit incrementally changes the transducer gain in the direction to bring the peaks in Vsig to just below the target value TTG. Reference voltages VP2 and VN2 are generated that are equal respectively to the most recent peak positive and negative going excursion in Vsig.

Abstract: A 90° phase shift circuit receives an input signal to generate a Q-signal and an I-signal having a phase difference of 90° therebetween. The 90° phase shift circuit has a CR-type high-pass filter having a variable capacitor and fixed resistor, a CR-type low-pass filter having a variable capacitor and a fixed resistor, and a level comparator for comparing the amplitudes of both the outputs from the filters to feed-back a control signal for controlling the cut-off frequencies of both the filters.

Abstract: A voltage boosting circuit which derives an output voltage than is substantially twice the magnitude of a supply voltage applied thereto. The voltage boosting circuit consists of complementary acting boost circuits each having a pair of switches (42A, 52A; 42B, 52B) connected between an input of the voltage boosting circuit, at which is applied the supply voltage, and an output at which the output voltage is produced. Boost capacitors (48A, 48B) are connected between the respective switches of the complementary boost circuits and the switches of the these circuits are opened and closed out of phase with respect to each other in response to clocking signals being applied thereto such that a boosted output voltage is produced during each half cycle of the clocking signals.

Abstract: In a control voltage producing apparatus, either a pulse-duration modulation signal or a pulse-width modulation signal, which are generated in response to a digital control signal, is from a first buffer circuit to an averaging circuit so as to be averaged. A power supply voltage is supplied from a first voltage source to this first buffer circuit. Then, the averaged signal is supplied to a control voltage producing circuit for producing a target control voltage. When a control voltage is produced, the same output voltage as that of the first buffer circuit is generated by a second buffer circuit, and then is supplied to the control voltage generating circuit and an operation control circuit. In response to the output voltage derived from the second buffer circuit, the operation control circuit applies the power supply voltage to the control voltage producing circuit so as to cause this control voltage producing circuit to be operable.

Abstract: An electronic vernier realizes programmable gain steps with first and second impedance ladders, a plurality of activatable coupling networks and a switch network. The ladders receive and progressively process the differential input signal into a plurality of progressive differential signals. In an embodiment, the coupling networks each generate a respective one of a plurality of progressive differential output signals in response to a respective one of the progressive differential signals and the switch network activates any selected one of the coupling networks. Thus, any selected vernier step is obtained by activating the respective coupling network. The verniers can be integrated into various systems, e.g., programmable amplifiers.

Abstract: A microprocessor (9) has output driver circuitry (20 FIG. 1; 30, 32 FIG. 2) which is selectable by signals on electrical lines (22 FIG. 1; 36 FIG. 2) to obtain different drive levels. In this manner mass produced microprocessors may be employed with output voltage selected to better match load and thereby reduce electrical noise from overshoot and ringing. Typically, each microprocessor when installed in a printer (1) or other apparatus will be selected to only one such status during the life of the apparatus.