Abstract: Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal.

Abstract: The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, a pull-up circuit, and a pull down circuit. The negative elevating circuit senses a transition of a logic input signal to generate a control signal. The first pull-up circuit is operatively coupled to this control signal for switching the driver output from a negative voltage to a ground voltage. There is an additional delay module which is configured to provide a delay in the logic input signal. This delayed logic input signal is operatively coupled to the second pull-up stage which takes the output of the driver from GND to VDD. The pull-down circuit is operatively coupled to the negative elevator for controlling a voltage at the driver output to the negative level.

Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

Abstract: A calibration circuit calibrates an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance. The calibration circuit outputs a calibration signal carrying information for calibrating the capacitor and includes a calibration loop.

Abstract: Systems and methods for determining a slicing level which is used as a threshold to determine whether timeslots of an incoming data signal contain ones or zeros. The method of one embodiment comprises receiving a data signal, identifying a maximum level of the data signal, identifying a minimum level of the data signal, determining an average of the minimum and maximum levels, and then using the average of the minimum and maximum levels as a slicing level to identify bits of a data packet embodied in the data signal.

Abstract: The present invention relates to a method for transmitting a two-valued signal via a channel, a pulse train being output after the change of a signal level of the two-valued signal, and subsequently to the pulse train, a backswing is output. The present invention also relates to a circuit configuration for transmitting a two-valued signal having a magnetically coupled coil pair which includes an input coil and an output coil, at least two driver stages which are each connected to a terminal of the input coil, and an evaluation circuit which is connected to the terminals of the output coil, a capacitance being provided between a driver stage and a terminal of the input stage, and the input coil and the output coil each include two coil sections having windings in the opposite direction, the coil sections having the same winding direction of the input coil and the output coil being magnetically coupled.

Abstract: Embodiments of the present invention provide an apparatus and control method for an analog front end (AFE) amplifier for controlling DC restore operations. According to the exemplary method, a first input stage of the AFE is controlled to operate as a continuous time amplifier that has high input impedance and draws substantially no input leakage current for a first predetermined area of an imaging sensor image array. The first input stage is controlled to operate as a sample and hold amplifier with DC restore functionality for a second predetermined area of the imaging sensor image array. According to an embodiment, the AFE input stage operates as a continuous time amplifier when reading pixels from the sensor's active image array but operates as a sample and hold amplifier with DC restore when reading pixels from the image array that correspond to so-called ‘black-level’ pixels or pixels that otherwise fall outside the sensor's active image field.

Abstract: A waveform controller includes a monitor configured to monitor a waveform of an output pulse obtained by the response of a responsive element to a driving signal supplied thereto and a driving waveform shaper configured to shape a waveform of the driving signal based on a monitoring result obtained by the monitor.

Abstract: A system for providing at least two output signals to produce a substantially uniform potential profile includes a signal generator adapted to emit a frequency at least about 30 megahertz, a splitter in communication with the signal generator, and a signal manipulator in communication with the splitter. The splitter is adapted to split the signal of the signal generator into the two output signals, and the signal manipulator is adapted to manipulate a phase, a gain, or an impedance of the two output signals. The signal manipulator manipulates the two output signals so that the two output signals produce the substantially uniform potential profile.

Abstract: An integrated circuit includes a pull-up compensation path unit configured to adjust a pull-up driving power of an input signal; a pull-down compensation path unit configured to adjust a pull-down driving power of the input signal; and a path control unit configured to route the input signal to one of the pull-up compensation unit and the pull-down compensation unit in response to a conditional signal.

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract: In various embodiments, applicants' teachings are related to an active guarding circuit and method for reducing parasitic impedance signal loading on a signal-transmission channel that is shunted by a parasitic impedance. The presence of an electrical signal on the signal-transmission channel causes a leakage current to flow through the parasitic impedance. In various embodiments, the circuit comprises an amplifier and an impedance, one terminal of the impedance is coupled to the signal-transmission channel. The input of the amplifier is coupled to the signal-transmission channel and the output is coupled to the other terminal of the impedance so as to cause a compensation current to flow through the impedance. The gain of the amplifier and the value of the impedance are selected so that the compensation current has a magnitude substantially equal to the leakage current magnitude.

Abstract: A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.

Abstract: A method and apparatus to regulate voltage used to power an ASIC comprising an ASIC having a signal source and a modulator. The modulator establishes a characteristic of a signal created by the signal source to indicate a voltage level to be used to power the ASIC. The signal is communicated to a voltage regulator to apply an optimal voltage to the ASIC.

Abstract: A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.

Abstract: A receiving stage for a multi-stage signal modulated upon a supply voltage, including: a supply potential terminal and a ground potential terminal, a voltage divider and a low-pass filter, whose input is connected to the supply potential terminal and the ground potential terminal, and which has an output which is arranged to output the low-pass filter output signal.

Abstract: Methods (1500) and corresponding systems (400, 500) for determining and correcting a DC offset in a receiver operate to sample (1503) a signal to provide complex samples; estimate (1505) a Direct Current (DC) offset corresponding to each of the complex samples, the estimating the DC offset further including solving a plurality of equations relating to the plurality of complex samples, e.g., N simultaneous equations in N samples with a power of the signal invariant across the N samples, to deterministically derive offset values; and then remove (1517) the DC offset from the signal.

Abstract: One high-frequency switch Qm supplied with transmit and receive signals to ON, and another high-frequency switch Qn supplied with a signal of another system to OFF are controlled. In the other high-frequency switch Qn, to set V-I characteristics of near-I/O gate resistances Rg1n-Rg3n of a near-I/O FET Qn1 near to a common input/output terminal I/O connected with an antenna are set to be higher in linearity than V-I characteristics of middle-portion gate resistances Rg3n and Rg4n of middle-portion FETs Qn3 and Qn4. Thus, even in case that an uneven RF leak signal is supplied to near-I/O gate resistances Rg1n-Rg3n, and middle-portion gate resistances Rg3n and Rg4n, the distortion of current flowing through the near-I/O gate resistances Rg1n-Rg3n near to the input/output terminal I/O can be reduced.

Abstract: A high voltage generation circuit includes a clock logic unit configured to generate a switch clock signal and a pump clock signal, that has a varying frequency, in response to an input signal, a high voltage unit configured to generate a high voltage in response to the pump clock signal, a high voltage switch configured to output a selection signal in response to the switch clock signal, and a switching element configured to transfer the high voltage, generated by the high voltage unit, to an output node in response to the selection signal.

Abstract: In a method and apparatus for compensating non-linearity of a gain of a residual amplifier (RA), a pipelined analog-to-digital converter (ADC) converts an analog input to a digital output (DO). The ADC includes a plurality of pipelined stages (PPS). Each stage, which includes an instance of the RA, provides a digital code corresponding to an output of the RA included in a preceding stage. A memory stores a piecewise linear representation for modeling the non-linearity of the gain. A calibrated gain of the RA corresponding to each region of a plurality of linear operating regions of the RA is stored in the memory. A gain adjuster adjusts the digital code for each one of the PPS in accordance with a gain factor derived from the calibrated gain for each one of the PPS. A constructor constructs the DO from the adjusted digital code received from each one of the PPS.

Abstract: The present invention discloses a charge pump down circuit which comprises three capacitors operating in three time phases. In the first time phase, the total of the voltages across the three capacitors is equal to an input voltage; in the second time phase, the voltage across the second capacitor is equal to the voltage across the third capacitor; in the third time phase, the difference between the voltages across the first and the second capacitors is equal to the voltage across the third capacitor, wherein the voltage across the third capacitor is the output voltage of the charge pump down circuit.

Abstract: Implementations are presented herein that include a level shifter circuit.

Abstract: There is provided a current amount adjusting section adjusting a current amount flowing through a power supply line supplying power to an internal circuit which includes a circuit operating based on a clock signal and a ratio of consumed charge amounts by the current flowing at a rising edge of the clock signal and by the current flowing at a falling edge of the clock signal so that noise generated in the power supply line may be restrained.

Abstract: An apparatus, system, and method are disclosed for phase shifting and amplitude control. A two-phase local oscillator generates an in-phase sinusoidal signal of a fixed frequency and a quadrature sinusoidal signal of the fixed frequency having a ninety degree phase shift from the in-phase sinusoidal signal. A signal generator receives the in-phase sinusoidal signal and the quadrature sinusoidal signal and generates a controllable sinusoidal signal of the fixed frequency. The controllable sinusoidal signal has a variable amplitude and a shiftable phase. A mixer varies the amplitude and shifts the phase of an input signal by mixing the input signal with the controllable sinusoidal signal to generate an output signal. The input signal and the output signal carry phase and amplitude information required for phased array signal processing. Either a receiver or a transmitter may be implemented using the present invention.

Abstract: The disclosure relates to a method and apparatus for noise suppression in an LVDS receiver by providing improved common mode noise immunity through a bypass circuit. In one embodiment, the disclosure relates to an apparatus for providing Low Voltage Differential signaling (LVDS). The apparatus includes a preamplifier circuit for receiving a DC component of a first signal and providing a first processed DC signal; a first bypass circuit for receiving an AC component of the first signal, the first bypass circuit providing a first AC output signal; a first node for combining the processed DC signal with the first AC output signal to form a first combined output signal; and an amplifier circuit for amplifying the first combined output signal and a second signal to provide a first amplified signal and a second amplified signal, wherein the first bypass circuit is in parallel with the preamplifier circuit.

Abstract: A pre-driver for driving a high-side transistor of a bridge driver is connected to a bridge driver including first and second drive transistors connected in series between a high voltage power supply and ground. A reference circuit generates a reference voltage that varies depending on the output voltage of the bridge driver. In response to the reference voltage, the regulator circuit generates an internal power supply voltage that is substantially higher than the output voltage by a constant value. A buffer circuit generates a drive voltage for driving the first drive transistor based on the internal power supply voltage and the output voltage.

Abstract: A signal adjusting circuit is provided. The signal adjusting circuit includes a first operational unit, a second operational unit, an auto-gain controller (AGC), a first clamp circuit, and a second clamp circuit is provided. The first operational unit performs an operation to a digital signal and a first gain value, to obtain a first adjusting signal. The second operational unit performs an operation to the digital signal and a second gain value, to obtain a second adjusting signal. The AGC generates a third gain value according to the first adjusting signal. The first clamp circuit receives and restricts the third gain value between a first upper limit and a first lower limit for generating the first gain value. The second clamp circuit receives and restricts the third gain value between a second upper limit and a second lower limit for generating the second gain value.

Abstract: A system for detecting a buried conductor comprises a transmitter for generating a test signal in the buried conductor and a detector for detecting an electromagnetic signal resulting from the test signal flowing in the buried conductor. The transmitter comprises a waveform generator for generating a drive waveform signal, a power supply, an amplifier, connected to the power supply and the waveform generator for producing an output drive signal based on the drive waveform signal and an output circuit for acting on the output drive signal to generate an output signal having a current and a voltage. In-phase and quadrature components of the current and voltage of the output signal are fed back for controlling the amplifier.

Abstract: A variable gain amplifying apparatus has an amplifier, one or more first switching elements connected in parallel to the amplifier, and a phase shifter connected in series to the first switching element. The first switching element is enabled if the level of an input signal or an output signal is higher than a predetermined level, and the first switching element is disabled if the level of the input signal or the output signal is equal to or lower than the predetermined level. The amplifier does not operate when the first switching element is enabled, and the amplifier operates when the first switching element is disabled, and the amount of phase shift when the input signal is passed through the amplifier and phase shifter is substantially equal to the amount of phase shift when the input signal is passed through the first switching element.

Abstract: An energy saving driving circuit and method is provided for use with a solid state relay (SSR). The circuit and method reduce the overall energy required to drive a solid state relay by maintaining the SSR in an “on” state with a minimal maintenance or holding current after applying a turn-on current. The driving circuit includes a control circuit configured for outputting a control signal; a turn-on circuit configured for providing an output current at a first current level for a first time period in response to the control signal; and a holding circuit configured for maintaining said output current at a second reduced current level for a second time period. The maintenance or holding current is reduced in respect of that of a conventional driving current, and in some cases may be an order of magnitude or more less in magnitude than a conventional driving current, thereby resulting in less energy consumed by the SSR.

Abstract: Systems and methods relating to programmable circuits are described. Several embodiments relate to systems and methods for controlling the long-term stability and accuracy of circuits that produce waveforms varying in frequency and amplitude. Such embodiments may include a circuit comprising a common vacuum environment that houses a pair of heater-thermocouples. The circuit may compare signals outputted by each heater-thermocouple and then may produce a resultant value based on the comparison. The resultant value may be used by the circuit to control the long-term stability and accuracy of the circuit. Such control of the long-term stability and accuracy of the circuit may include drift compensation associated with certain components of the circuit.

Abstract: A circuit includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined voltage level. A first stage set of capacitors is operatively coupled to the level-crossing detector. A ramp circuit is operatively coupled to the set of series-connected capacitors. A second stage set of capacitors is operatively coupled to the first stage set of capacitors and the ramp circuit. The ramp circuit includes a feedback capacitor and a preset switch to provide a linear ramp output.

Abstract: An input and output circuit apparatus includes a signal generating circuit configured to generate a first signal, an input and output circuit configured to receive the first signal from the signal generating circuit and a second signal to generate an output signal responsive to the first signal and the second signal, an operation test circuit having substantially an identical circuit configuration to the input and output circuit, and configured to receive the first signal from the signal generating circuit and a third signal to generate an output signal responsive to the first signal and the third signal, a check circuit configured to generates a check signal indicative of an operating condition of the operation test circuit in response to the output signal of the operation test circuit, and an adjustment circuit configured to adjust the signal generating circuit in response to the check signal output from the check circuit.

Abstract: A pulse detection device detects a pulse signal having an intermediate potential in a predefined period. Furthermore, the pulse detection device includes a signal fixing section that fixes the intermediate potential of the pulse signal at a low level or a high level. Furthermore, the signal fixing section is preferably a pull-down resistor or a pull-up resistor connected to an input signal line to which the pulse signal is input. Note that a pulse detection method may fix the intermediate potential of the pulse signal at a low level or a high level.

Abstract: In a receiving-side printed circuit board, a reflected-waveform analyzing unit analyzes a reflected wave generated in a transmission line on a backplane along with transmission of a signal from a transmitting-side printed circuit board, and acquires waveform data that indicates a waveform of the reflected wave. An input signal identifying unit calculates a size of the reflected wave that is currently received based on the waveform data and data on previously received signals. The input signal identifying unit corrects a threshold value by the calculated size, and identifies a state of a bit indicated by the signal from the transmitting-side printed circuit board.

Abstract: A system and method for restoring a clipped signal may be used in an optical receiver that detects a clipped modulated optical signal. The clipped modulated optical signal is detected to produce a clipped electrical signal including a series of clipped negative peaks and corresponding positive peaks. The clipped signal may be corrected by detecting at least one trigger peak preceding one or more clipped negative peaks to be restored and generating a replacement tip signal segment for the clipped negative peak(s) to be restored. The replacement tip signal segment may be combined with the clipped electrical signal such that the replacement tip signal segment coincides with a clipped end of the clipped negative peak to be restored to produce a restored negative peak.

Abstract: An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

Abstract: A frequency control circuit including a controlled oscillator and an amplifier circuit is disclosed for providing a clock signal to a switched capacitor circuit which divides an input voltage to provide an output voltage. The controlled oscillator has a frequency control input receiving a frequency control signal and an output for providing the clock signal at a frequency based on the frequency control signal. The amplifier circuit has an input for receiving the output voltage and an output providing the frequency control signal based on droop of the output voltage. In one embodiment, the amplifier circuit adjusts the frequency control signal to optimize efficiency of the switched capacitor circuit over a voltage range of the output voltage, which changes based on load level.

Abstract: In order to transfer data at high speed over a long distance, a current mode logic output circuit (CML) having a large number of taps, high accuracy, and a wide switchable range of the amount of pre-emphasis is needed. However, when the amount of emphasis is set by adding unit source-coupled pair circuits, a problem will arise that the output capacitance of the current mode logic output circuit would increase, thus hampering high-speed transmission. An output circuit of the invention is constructed from unit source-coupled pair circuits 501, which are obtained by dividing a current mode logic output circuit (CML) into m groups, terminal resistors 502, and a data selector 504. The amount of emphasis of each tap is determined by the ratio of the number of unit source-coupled pair circuits, which have been obtained by dividing the CML into m groups, allocated to each tap. Thus, the amount of emphasis can be set to be any arbitrary amount without a change in the output amplitude of 1.

Abstract: A gate and the other end of the current path of first and second transistors are cross-connected. A third transistor is inserted to the other end of the current path of the first transistor, and a gate is supplied with a constant voltage, and further, one end of the current path and well are connected. A fourth transistor is inserted to the other end of the current path of the second transistor, and a gate is supplied with a constant voltage, and further, one end of the current path and well are connected. Fifth and sixth transistors are connected to the other end of the current path of the third and fourth transistors, and a gate is complementarily supplied with an input signal. Seventh and eighth transistors are connected to a back gate (well) of the third and fourth transistors, and a gate is complementarily supplied with an output signal.

Abstract: Disclosed is a signal output circuit comprising: a first transistor of an emitter follower configuration, which receives an input signal; a second transistor of an emitter follower configuration, which receives the input signal, and has an output connected to an external load (106); a comparator circuit which has an input pair connected via resistors to emitters of the first and the second transistors; a first current mirror circuit which has an input connected to an output of a first current source transistor and an output connected to an emitter of the first transistor; and a second current mirror circuit which has an input connected to a connection node of an output of a second current source transistor and an output of the comparator circuit, and has an output connected to an emitter of the second transistor.

Abstract: A power control device for an electronic device for enhancing power stability when the electronic device is powered on including a high-pass filtering unit for performing a filtering process on an input signal for generating an output signal, and a control unit coupled to the high-pass filtering unit and a first voltage generator of the electronic device for outputting the output signal to the first voltage generator according to the voltage level of the output signal.

Abstract: A method of processing an in-phase signal component and a quadrature signal component of a low intermediate frequency (LIF) signal includes estimating and correcting an amplitude imbalance between a digitized in-phase signal component and a digitized quadrature signal component at a first point in time, and estimating and correcting a phase imbalance between the digitized in-phase signal component and the digitized quadrature signal component at a second point in time in response to the correcting process. The digitized in-phase signal component corresponds to the in-phase signal component at the first point in time and the digitized quadrature signal component corresponds to the quadrature signal component at the first point in time. The second point in the time is subsequent to the first point in time.

Abstract: An adjustable voltage supply (310) may have a plurality of levels of adjustment, such as a coarse select circuit (471) and a fine select circuit (473), to generate an adjustable voltage (e.g. Vout 364 of FIGS. 3 and 4) with fine resolution across a wide voltage range. In one embodiment, the adjustable voltage may be used as an adjustable read voltage to measure the threshold voltages of bitcells in a memory array (300). From the distribution of these threshold voltages, it is possible to determine the marginality of the bitcells with regard to the voltage which is required to read the bitcells. In one embodiment, the adjustable voltage supply (310) may also be used to provide an adjustable voltage to one or more integrated circuit pwells and/or nwells in order to apply electrical stress. An adjustable voltage supply (310) may be used in any desired context, not just memories.

Abstract: A controllable-gain circuit (TI, Rt, TS1, . . . , TS4) provides a first and a second pair of complementary gain-controlled signals (Ip1, Ip3; Ip2, Ip4) in response to an input signal (RFI). In each pair, one gain-controlled signal (Ip1, Ip2) is the input signal amplified with a gain G comprised in a range between a minimum gain Gmin and a maximum gain Gmax. The other gain-controlled signal (Ip3, Ip4) is the input signal amplified with complementary gain Gmax-G. A fixed-gain output circuit (Rfg, Nfg) makes a weighed sum (Ip1*Rfg+Ip3*Rfg) of one and the other gain-controlled signal in the first pair of complementary gain-controlled signals. The respective weighing factors for one and the other gain-controlled signal are substantially similar (Rfg). A controllable-gain output circuit (Rlg, Rhg, Nlg, Nhg) makes a weighed sum (Ip2*Rlg+Ip4*(Rlg+Rhg)) of one and the other gaincontrolled signal in the second pair of complementary gain-controlled signals.

Abstract: A reference voltage generating circuit that generates a reference voltage includes: a first pn junction that generates a first voltage; a second pn junction that has a different current density from the first pn junction; a first resistor that generates a first current having a positive temperature coefficient based on a voltage equivalent to a difference between a forward voltage of the first pn junction and a forward voltage of the second pn junction; a second resistor that generates a first voltage having a positive temperature coefficient based on the first current, wherein the first voltage having the positive temperature coefficient and a voltage having a negative temperature coefficient are added to generate the reference voltage; and a third resistor that generates a temperature-dependent voltage based on the first current having the positive temperature coefficient, wherein the reference voltage and the temperature-dependent voltage are outputted in parallel from first and second output nodes, respec

Abstract: A voltage detecting circuit for comparing a voltage to be detected with a reference voltage and outputting an output signal having a level depending on the comparison is disclosed. The voltage detecting circuit includes an inverting amplifier circuit configured to receive an intermediate signal having a level depending on the comparison and output the output signal. The inverting amplifier circuit includes an active element having a control terminal. A threshold voltage of the control terminal is as low as or lower than the reference voltage. The voltage to be detected is applied to the control terminal of the active element.

Abstract: The present invention relates to emphasizing and de-emphasizing of an analog data signal. Using a main analog driver (14) a data signal indicative of bit values of binary data is converted into a first analog data signal. A second data signal is determined by delaying the data signal a predetermined time interval and inverting the delayed data signal. Using a de-emphasis driver (114), the second data signal are converted into a second analog data signal, wherein the second analog data signal is additive to the first analog data signal if the data signal and the second data signal are indicative of a same bit value, and wherein the second analog data signal is subtractive to the first analog data signal if the data signal and the second data signal are indicative of an opposite bit value. The first analog data signal is emphasized or de-emphasized by superposing the first analog data signal and the second analog data signal.

Abstract: An integrated laser device includes a pre-distortion circuit. The pre-distortion circuit receives an electrical modulation signal and generates a pre-distorted modulation signal. A laser is integral with the pre-distortion circuit. The laser includes an electrical modulation input that is connected to the output of the pre-distortion circuit. The laser modulates an optical signal with the pre-distorted modulation signal. The pre-distorted modulation signal causes at least some vector cancellation of distortion signals generated when the laser modulates the optical signal.

Abstract: A level translator has an inverter comprising a first transistor having a first predetermined voltage threshold and a second transistor having a second predetermined voltage threshold. The two transistors have control gates being of complementary conductivity. A first capacitor is connected at one end to the gate of the first transistor and at a second end to an input signal. A second capacitor is connected at one end to the gate of the second transistor, the input signal being applied to a second end of the second capacitor. A comparator is used for detecting the relationship between the input signal and a reference voltage. A first current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the first transistor. A second current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the second transistor. A first clamp circuit is used for limiting a gate voltage of said first transistor.