Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry includes first and second DAC circuits which generate first and second signals according to an input pattern. The input pattern includes at least one of first logic value and at least one of second logic value that have different numbers. The calibration circuitry performs a calibration operation according to first and second comparison results, to generate a control signal for controlling the second DAC circuit. The first comparison results are comparison results of the first and the second signals when the input pattern is a first pattern, the second comparison results are comparison results of the first and the second signals when the input pattern is a second pattern, and the first pattern is inverse to the second pattern.

Abstract: A semiconductor device includes a voltage generator generating a reference voltage, a first reference current generator receiving the reference voltage and generating a reference current, a non-volatile memory storing a calibration code, a first bias current generator mirroring the reference current to generate a first bias current, and a second bias current generator adjusting the reference current according to the calibration code of the non-volatile memory to generate a second bias current.

Abstract: A VCOM generator circuit generates a VCOM signal for an electronic display. The VCOM circuit includes an operational amplifier having reduced supply rails. In an implementation, the VCOM circuit has at least three supply rails, AVDD, ground or GND, and VP or VN, or both. VP is less than AVDD and greater than VN. VN is higher than ground and below VP. The VCOM circuit with reduced voltage supply rails for VP and VN reduces power consumption of the VCOM op amps. By reducing power consumption, this also reduces the surface temperature of the integrated circuit.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output.

Abstract: Apparatuses and methods for data transmission in an image sensor are disclosed herein. An example data transmission circuit may include a plurality of transmission banks coupled in series with a first one of the plurality of transmission banks coupled to function logic, where each of the plurality of transmission banks are coupled to provide image data to a subsequent transmission bank in a direction toward the function logic in response to a clock signal, a plurality of delays coupled in series, wherein each of the plurality of delays is associated with and coupled to a respective transmission bank of the plurality of transmission banks, and wherein the clock signal is received by each of the plurality of transmission banks after being delayed by a respective number of delays of the plurality of delays in relation to the function logic.

Abstract: An imaging device includes: a plurality of pixels arranged to form rows and columns and each configured to output a signal in accordance with an incident light, a plurality of column signal processing units provided in association with the columns and each having an A/D conversion unit that performs A/D conversion on a signal output from the pixels arranged on a corresponding column, a plurality of memory units provided in association with the columns and each having a memory that holds digital data output from the column signal processing unit of a corresponding column, a transfer unit that sequentially outputs the digital data held in each of the plurality of memory units to a common output line, and a bit value inversion unit that inverts a value of a bit of one of first and second digital data sequentially output to the common output line.

Abstract: Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e.

Abstract: There is provided a successive-approximation type AD converter and a pipeline type AD converter without delay due to sample hold. A successive-approximation type AD converter 1 includes: receiving circuits configured to output the analog input signal according to the received analog input signal; subtractors configured to calculate subtraction signals between the analog input signal in each of n successive conversions and comparison signals obtained by DA-converting the control values by DA converters; comparators configured to determine a high-low relationship between the voltages of the subtraction signals and the reference voltage; a control circuit configured to update the control values so that the comparison signals approach the analog input signal based on the comparison results; and an output register configured to output the digital output signal based on the comparison results of the comparators.

Abstract: An image sensor comprising: a generator that generates a plurality of reference signals having different slopes of potential change; a selector that selects one of the reference signals; and an analog/digital converter that converts an analog signal output from a pixel unit by first or second driving using the selected reference signal into a digital signal. In the first driving, a noise signal is converted into a plurality of first digital signals using the reference signals and a photoelectric conversion signal is converted into a second digital signal using one of the reference signals. In the second driving, the noise signal is converted into the first digital signal using a predetermined one of the reference signals and the photoelectric conversion signal is converted into the second digital signal using one of the reference signals. The first driving is performed intermittently.

Abstract: Analog multipliers circuits can provide signal processing asynchronously and clock free and with low power consumptions, which can be advantageous, including in emerging mobile, portable, and at edge or near sensor artificial intelligence (AI) and machine learning (ML) applications. As such, analog multipliers can process signals memory-free in AI and ML applications, which avoids the power consumption and latency delays attributed to memory read-write cycles in conventional AI and ML digital processors. Based on standard digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of multi-quadrant current-mode analog multiplier (iMULT) circuits that can be utilized in current-mode multiply-accumulate (iMAC) circuits and artificial neural network (ANN) end-applications that require high-volumes, low costs, medium precision, low power consumptions, and clock free asynchronous signal processing.

Abstract: An apparatus includes a time-to-digital converter (TDC). The TDC includes a fine TDC (F-TDC) to generate a first output signal in a first range in response to a first signal and a second signal, and a coarse TDC (C-TDC) to generate a second output signal in a second range in response to the first signal and a delayed version of the second signal.

Abstract: A ramp generator includes an integrator including a first stage having first and second inputs and first and second outputs, and a second stage including first and second transistors coupled between a power supply rail and ground. A node between the first and second transistors is coupled to the output of the integrator amplifier. A control terminal of the first transistor is coupled to the first output of the first stage, and a control terminal of the second transistor is coupled to the second output of the first stage. A first current flows from the output to ground during a ramp event in the ramp signal generated from the output. Trimming circuitry is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to trimming inputs. The second current substantially matches the first current.

Abstract: A successive approximation register (SAR) analog to digital converter (ADC) and a method of detecting an offset of a comparator are introduced. The SAR ADC includes a switch circuit, a comparator and a calibration circuit. The switch circuit is configured to perform a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal. The comparator is coupled to the switching circuit and is configured to compare the first intermediate analog signal and the second intermediate analog signal before the swapping operation to generate a least-significant-bit value. The comparator is further configured to compare the first swapped analog signal and the second swapped analog signal after the swapping operation to generate a calibration bit value. The calibration circuit is configured to determine whether the comparator has an offset according to the least-significant-bit value and the calibration bit value.

Abstract: In a sonar system using a large array multielement sonar detector, the raw phase and intensity data is reduced to less than three bits per channel per slice for each of the detectors in the multielement array before the raw data is transmitted to a beamformer for transforming the data to information about the spatial positions of objects reflecting the sonar signals.

Abstract: A pulse generator of an image sensor includes a delay cell including a plurality of transistors arranged in series between a power voltage and a ground, a stabilization capacitor, and a stabilization switch. The power voltage is supplied to a first terminal of a first transistor disposed first among the plurality of transistors, and a gate terminal of the first transistor is connected to a first node. An input voltage is supplied to a gate terminal of an n-th transistor disposed last among the plurality of transistors, and a ground voltage is supplied to a first terminal of the n-th transistor. The stabilization switch is disposed between a reference voltage input terminal providing a reference voltage and the first node. The stabilization switch is turned on by an input bias control signal to supply the reference voltage to the first node.

Abstract: A wireless communication device converts a signal component, which has one of distributed frequency bands in an analog RF signal and passes through one of a plurality of bandpass filters, into digital data with an AD converter that carries out undersampling. A sampling frequency of the AD converter is set so that frequencies which are integral multiples of a Nyquist frequency based on the sampling frequency do not fall within frequency bands of signal components which are of the RF signal and are to pass through the respective plurality of bandpass filters.

Abstract: In one embodiment an analog-to-digital converter circuit has an input for receiving a first analog signal level and a second analog signal level, a ramp generator adapted to provide a ramp signal, a comparison unit coupled to the input and the ramp generator, a control unit coupled to the comparison unit the control unit having a counter, the control unit being prepared to enable the counter as a function of a comparison of the ramp signal with the first analog signal level and the second analog signal level, and an output for providing an output digital value as a function of a relationship between the first analog signal level and the second analog signal level. Therein the ramp signal has at least one linearly rising and at least one linearly falling portion and an adjustable shift at a reversal point between the rising and the falling portion of the ramp signal, the shift depending on the number of rising and falling portions of the ramp signal.

Abstract: A ramp signal generation device may be provided to include a ramp signal generator including a plurality of local ramp signal generators, each local ramp signal generator structured to generate a local ramp signals having a local ramp range based on a control of an external control unit, an AC coupler coupled to the ramp signal generator to receive local ramp signals from the ramp signal generator, the AC couple structured to perform AC coupling on the received local ramp signals and generate AC-coupled ramp signals, and an integrator coupled to the AC coupler to receive the AC-coupled ramp signals and structured to integrate the AC-coupled ramp signals into a ramp signal having a full ramp range.

Abstract: A photoelectric conversion apparatus includes a pulse shaping circuit that shapes an output from a diode of avalanche amplification type into a pulse, and a pulse conversion circuit that converts a pulse signal output from the pulse shaping circuit. The pulse conversion circuit converts a pulse signal having a first amplitude and output from the pulse shaping circuit into a pulse signal having a second amplitude smaller than the first amplitude.

Abstract: Power converter circuits, including DC-DC converter circuits, that conserve IC area by utilizing more area-efficient alternatives for measurement circuitry. Various embodiments include a power converter circuit including a charge pump having a plurality of stack-nodes VCXM and at least one multiplexor for coupling selected stack-nodes VCXM to a corresponding comparator circuit configured to output a signal indicative of a difference between a selected input to the multiplexor and a reference signal. The number of comparator circuits is less than (N?1)×M, where N is the conversion gain of the power converter circuit (i.e., the number of charge pump stages X plus one), and M is the number of parallel charge pump legs. Related methods include measuring voltages at stack-nodes VCXM in a charge pump, wherein the stack-nodes VCXM are selected by means of a multiplexor and an input to a comparator.

Abstract: According to an aspect, a tri-level digital to analog converter (DAC) comprises a first set of switches turned on to cause a first analog value with a first error as an output for a first digital value, a second set of switches turned on to cause a second analog value with a second error as the output for a second digital value, wherein, both the first set of switches and the second set of switches are turned on to cause a third analog value, proportional to the first error and the second error, as the output for a digital value equal to zero, and both the first set of switches and the second set of switches are turned off to cause a fourth analog value equal to zero as the output for a fourth digital value representing a reset state.

Abstract: An analog-to-digital (A/D) conversion system includes a track-and-hold circuit, a digital-to-analog (D/A) conversion circuit, a comparison circuit and a control circuit. The track-and-hold circuit is configured to output a first signal based on an input signal. The D/A conversion circuit is configured to generate a second signal based on an N-bit logical signal. The comparison circuit is configured to generate a comparison result based on the first signal and the second signal. The control circuit is configured to generate the N-bit logical signal according to N comparison results from the comparison circuit.

Abstract: A dual-slope analog-to-digital converter includes a switching circuit, an integrating circuit, a dual comparison circuit, and a control circuit. The integrating circuit is configured to perform a charging operation having a first slope, based on a magnitude of an input voltage selected by the switching circuit, and a discharging operation having a second slope, based on a magnitude of the reference voltage selected by the switching circuit, and output a first voltage. The dual comparison circuit is configured to output a first comparison signal by comparing the first voltage with a first reference voltage and output a second comparison signal by comparing a second reference voltage, higher than the first reference voltage, with the first voltage. The control circuit is configured to output a digital value corresponding to the magnitude of the input voltage, based on a first count value and a second count value.

Abstract: A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.

Abstract: A power loss protection integrated circuit includes a VIN terminal, a VOUT terminal, an STR terminal, a switch circuit (eFuse), a control circuit, and a prebiasing circuit. In a normal mode, current flows from a power source, into VIN, through the eFuse, out of VOUT, and to the output node. A switching converter of which the control circuit is a part is disabled. If a switch over condition then occurs, the eFuse is turned off and the switching converter starts operating. The switching converter receives energy from STR and drives the output node. Switch over is facilitated by prebiasing. Prior to switch over, the prebiasing circuit prebiases a control loop node as a function of eFuse current flow prior to switch over. When the switching converter begins operating, the node is already prebiased for the proper amount of current to be supplied by the switching converter onto the output node.

Abstract: There provided an AD converter that includes an analog processing part configured to select one of the measurement target voltages and a plurality of reference voltages for each channel, to output an analog voltage signal; a first selection part configured to select one of a plurality of analog voltage signals; a first AD conversion part configured to perform AD conversion on the analog voltage signal to generate a first original digital signal; a second selection part configured to select one of the plurality of analog voltage signals; a second AD conversion part configured to perform AD conversion on the analog voltage signal to generate a second original digital signal; a digital processing part configured to receive the first original digital signal and the second original digital signal; and a controller configured to control contents selected in the analog processing part, the first selection part, and the second selection part.

Abstract: In accordance with an embodiment, a method includes performing an analog-to-digital conversion on a signal at an input pin of an integrated circuit using an analog-to-digital converter having a first input range, monitoring the signal at the input pin using a first comparator having a first threshold outside of the first input range, operating the integrated circuit in a first mode when the signal at the input pin is within the first input range, and operating the integrated circuit in a second mode different from the first mode when the signal at the input pin is outside of the first input range and crosses the first threshold.

Abstract: A switched capacitor circuit includes a first capacitor, a second capacitor, and a switching circuit. The first capacitor is configured to receive a first signal. The second capacitor is configured to receive a second signal. The switching circuit is configured to selectively couple the first capacitor and the second capacitor to an input terminal of a quantizer according to at least one clock signal. In a first configuration of the switching circuit, the first capacitor is configured to store the first signal, and the second capacitor is configured to store the second signal. In a second configuration of the switching circuit, the first capacitor and the second capacitor are stacked in series, in order to transmit a combination of the first signal and the second signal to the input terminal of the quantizer.

Abstract: A first communication device includes a first timer and a second communication device includes a second timer. The first communication device receives, from the second communication device, a packet that includes a timestamp that corresponds to a least significant portion of the second timer. The first communication device determines whether a most significant bit of a least significant portion of the first timer is different than a most significant bit of the timestamp. At least when the most significant bit of the least significant portion of the first timer is different than the most significant bit of the timestamp: the first communication device determines a mathematical difference between i) the least significant portion of the first timer and ii) the timestamp, and selectively adjusts a most significant portion of the first timer based on the mathematical difference. The first communication device uses the timestamp to set the least significant portion of the first timer.

Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.

Abstract: A module for a programmable controller includes a plurality of analog input channels, a control and evaluation device, and input terminals, where for each input channel, the module includes two analog to digital converters, at least four coupling elements and a switchover device, where for each input channel, where an input side of one analog to digital converter is directly or indirectly connected with the input terminals and an output side is connected with the evaluation circuit via a coupling element, where a control input of the switchover device is connected with the switching signal generator via a further coupling element, a signal output of the switchover device is connected with an input side of the other analog-to-digital converter, and where an output side of the other analog-to-digital converter is connected with the evaluation circuit via a further coupling element, where the coupling elements cause electrical isolation.

Abstract: A range-finding device including a light-emitting device, an imaging unit, a calculator, and a controller. The image unit receives pulsed light reflected from an object within the space for a plurality of time periods in a time-division manner, electrically converts the pulsed light into an electrical signal, and accumulates electric charge of the electrical signal for each of the plurality of time periods. The calculator calculates a time difference between emission of the pulsed light and reception of the pulsed light reflected from the object based on the electric charge accumulated for each of the plurality of time periods and determine a distance to the object based on the time difference. The controller controls the timing of reception of the pulsed light for each of the plurality of time periods at the imaging unit according to an intensity of the pulsed light reflected from the object.

Abstract: In one embodiment, a time-interleaved analog-to-digital convertor (ADC) system, includes an array of ADCs to sample respective analog voltages at sampling times indicated by respective clock signals and to output corresponding digital values, phase generator circuitry to provide multiple, different phase-shifted clock signals for driving the respective sampling times of the ADCs, and a clock and data recovery circuit including ADC-specific first-order loop filters to derive respective ADC-specific average phase error corrections, and a shared loop filter to derive a shared average phase error correction over the array of ADCs and wherein the phase generator circuitry is coupled to provide corrected respective ones of the phase-shifted clock signals responsively to both respective ones of the ADC-specific average phase error corrections derived by respective ones of the first-order loop filters, and the shared average phase error correction derived by the shared loop filter.

Abstract: A semiconductor device including a resistance section that includes a first terminal and a second terminal disposed in contact with an outer periphery, and a serial resistance section in which plural resistance elements are connected in series, wherein one end of the serial resistance section is connected to the first terminal, and another end of the serial resistance section is connected to the second terminal; and a current adjustment section that includes a current source that supplies current to the serial resistance section, and disposed adjacent to the resistance section such that a distance between the first terminal and the current adjustment section along the outer periphery of the resistance section and a distance between the second terminal and the current adjustment section along the outer periphery of the resistance section are equal.

Abstract: Time-to-digital conversion circuitry converts a time between a start time point and a stop time point, which are state-change time points of digital signals, into digital. The time-to-digital conversion circuitry comprises oscillation circuitry that outputs a plurality of phase signals having different phases, and outputs a digital value of the time based on the plurality of phase signals. The oscillation circuitry performs free-running oscillation and outputs the phase signals that do not synchronize with the start time point and the stop time point.

Abstract: Time-interleaved analog-to-digital converters (ADCs) and related methods are disclosed that are based upon multiplying digital-to-analog converters (MDACs). For one ADC embodiment, a sample-and-hold circuit receives an input signal and outputs a voltage that represents the input signal. An MDAC receives the voltage, outputs an N-bit digital value, and outputs a current that represents the voltage. A phased current generator receives the current and outputs time-interleaved currents that are based upon the current. An array of sub-ADCs receive the time-interleaved currents, and each sub-ADC outputs a digital value. The digital values from the array of sub-ADCs are then combined and to output an M-bit digital value. The N-bit digital value and the M-bit digital value provide a digital conversion output for the ADC.

Abstract: This invention discloses a control circuit and a control method of a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The control circuit includes a memory, an inverter and a data path. The memory is configured to store an output value of the comparator. The inverter has an output coupled to a first end of a capacitor of the switched-capacitor DAC. A second end of the capacitor is coupled to an input of the comparator. The data path, coupled between an output of the comparator and an input of the inverter, temporarily causes a voltage at the first end of the capacitor to be controlled by the output value of the comparator. The data path does not contain any memory.

Abstract: An electronic circuit comprises multiple analog-to-digital converter (ADC) circuits and control logic circuitry. The control logic circuitry advances the multiple ADC circuits through multiple time-interleaved conversions that include time-interleaved acquisition phases, conversion phases, and tracking phases. An acquisition phase of a first ADC circuit samples the analog signal, a conversion phase of the first ADC circuit converts the sampled analog signal to a digital value, and the control logic circuitry is configured to update the first ADC circuit with most recent A/D conversion information by a different ADC circuit during a tracking phase of the first ADC circuit before the acquisition phase of the first ADC circuit.

Abstract: A biopotential monitoring device and use of such device. The device includes a configurable receiver circuit having a plurality of channels for receiving a plurality of biopotential signals from a biological tissue via a plurality of inputs coupled with the electrodes, and each channel substantially removes a DC (direct current) offset from a corresponding one of the biopotential signals and then band-pass amplifies such corresponding biopotential signal at a configurable gain and particular frequency range based on frequency control signals. The device further includes a controller circuit for receiving commands for configuring frequency characteristics of each biopotential signal. The controller automatically generates the frequency control signals based on such commands and outputs such frequency control signals to the configurable receiver circuit. The controller outputs a representation of each biopotential signal to an analyzer device that is configured to analyze such biopotential signal.

Abstract: An image sensor may include an array of pixels, and analog and digital circuitry. The pixels in the array may generate image signals in response to incident light. The image sensor may also include power supply circuitry and corresponding voltage rail structures that provide voltage levels to operate the pixel array, the analog circuitry, and the digital circuitry. The power supply circuitry may provide a low voltage, a high voltage, and an intermediate voltage power rail. The analog circuitry may operate in a voltage level domain defined by voltages between an intermediate voltage level and a high voltage level. The digital circuitry may operate in a voltage level domain defined by voltages between a low voltage level and the intermediate voltage level. In such a configured, analog and digital circuitry may both be provided with low-voltage transistors that are more area and power efficient and that are more scalable.

Abstract: Processing circuitry comprising: a reference node for connection to a reference voltage source so as to establish a local reference voltage signal at the reference node; a signal processing unit connected to the reference node and operable to process an input signal using the local reference voltage signal, wherein the signal processing unit is configured to draw a current from the reference node at least a portion of which is dependent on the input signal; and a current-compensation unit connected to the reference node and operable to apply a compensation current to the reference node, wherein the current-compensation unit is configured, based on an indicator signal indicative of the input signal and/or of the operation of the signal processing unit, to control the compensation current to at least partly compensate for changes in the current drawn from the reference node by the signal processing unit due to the input signal.

Abstract: A memory array structure that includes memory columns having first bit lines and second bit lines is introduced. Each of the memory columns includes a bit line pair, a pre-charge switch pair and a first switch pair. Output voltages from the first bit lines and the second bit lines are used to generated a first average voltage and a second average voltage, respectively. One of the first average voltage and the second average voltage is a lower average voltage and another one of the first average voltage and the second average voltage is a higher average voltage. The pre-charge switch pair and the first switch pair of a selected memory column among the plurality of memory columns are controlled to repeatedly perform an incremental step to increment the lower average voltage by a step voltage until the lower average voltage is greater than the higher average voltage.

Abstract: Embodiments of the present disclosure provide ADCs particularly suitable for PDAF image sensors, which ADCs may have an increased speed and/or reduced design complexity and power consumption compared to conventional implementations. An example ADC for a PDAF image sensor is configured to implement modified SAR techniques which reduce the number of bit trials required for conversion, and enable increased number of samples in a row-conversion time period of the image sensor. The ADC may implement the modified SAR techniques in combination with CMS in pixel readout signal chain, which may reduce noise without a proportionate increase in ADC sample rate.

Abstract: A latched comparator comprises a pre-amplifier stage with a positive input (Vin,p), a negative input (Vin,n); and a differential output (?Vout) comprising a first output (Vout,1) and a second output (Vout,2), the pre-amplifier stage comprising a first cascode pair, comprising a first amplifying transistor (MN2) and a first cascode transistor (MN4) connected at a first cascode node, the first amplifying transistor (MN2) being controlled by the positive input (Vin,p) and the first cascode transistor (MN4) being connected, opposite to the first cascode node, to the first output (Vout,1); a second cascode pair, comprising a second amplifying transistor (MN3) and a second cascode transistor (MN5) connected at a second cascode node, the second amplifying transistor (MN3) being controlled by the negative input (Vin,n) and the second cascode transistor (MN5) being connected, opposite to the second cascode node, to the second output (Vout,2); a first gain-boosting transistor (MN6) connected between the first output (V

Abstract: A comparison device includes an offset generation circuit that includes an input port to receive an offset control signal and is structured to generate an offset based on the received offset control signal; a comparison circuit comprising a first input port coupled to the offset generation circuit to receive a first input signal and a second input port coupled to receive a second input signal that is offset by the offset generated by the offset generation circuit and operable to compare the first input signal with the second input signal to produce a comparison signal; and a control circuit coupled to the comparison circuit to receive the comparison signal and operable to detect a crossing of the first input signal and the second input signal according to the comparison signal circuit and to output the offset control signal to the offset generation circuit.

Abstract: A TI ADC circuit (30) comprises a plurality of L analog inputs (32-1, 32-2, 32-3) and a plurality of L digital outputs (34-1, 34-2, 34-3). The i:th analog input (32-i) is for receiving an i:th analog input signal. The i:th digital output (34-i) is for outputting an i:th digital output signal, which is a digital representation of the i:th analog input signal. TI ADC circuit (30) comprises a set (90) of sub ADCs (100-1—100-K). The TI ADC circuit (30) is configured to generate one sample of each of the L digital output signals per conversion cycle. Each sub ADC (100-1—100-K) is configured to generate a digital output sample in M conversion cycles, wherein M is an integer >1. The number K of sub ADCs in the set (90) of sub ADCs (100-1—100-K) exceeds L·M.

Abstract: A conversion and folding circuit includes a voltage-to-delay converter block, including preamplifiers, for converting a voltage signal into delay signals, and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals. If desired, the logic gates may include odd and even chains for outputting delay signals to first and second analog-to-digital converters. If desired, the conversion and folding circuit may include first and second chains, and a chain selection circuit for selectively outputting a delay signal from a desired one of the first and second chains.

Abstract: In accordance with an embodiment, a method for calibrating at least two analog-to-digital converters includes feeding an analog predefined signal to the at least two analog-to-digital converters; converting the analog predefined signal into at least two converter-associated digital values using the at least two analog-to-digital converters, wherein the converting is based on a received clock signal; and adapting a converter-specific time delay based on the at least two converter-associated digital values.

Abstract: The present invention relates to analogue-to-digital converter (ADC) circuitry. In particular, the present invention relates to ADC circuitry configured to use successive approximation to arrive at a multi-bit digital value representative of an analogue input value.

Abstract: In a comparator of an analog-to-digital converter, an input signal is input to a control terminal of each of a plurality of signal input transistors. A signal input transistor selection section selects any one of the plurality of signal input transistors, and generates a current in response to a difference between the input signal and a reference signal to flow in the differential pair configured with the selected signal input transistor and a reference input transistor. A load section converts, at a time of a change of a current flowing in any one of the plurality of signal input transistors and the reference input transistor in response to the difference, the change of the current into a change of a voltage, and outputs the change of the voltage as a result of comparison between the input signal and the reference signal.