Abstract: Data isolators for providing isolation between two ports that enable dynamic communication are described. The dynamic communication may be achieved by varying a ratio of the data rate relative to a clock frequency of a clock signal. The data isolator may include a first circuit that transmits data across an isolation barrier when the clock signal is in a first state and a second circuit that transmits data across the isolation barrier when the clock signal is in a second state. The clock frequency may be variable and, as a result, change the duration of data transmissions in a given clock cycle. For example, the clock frequency may be reduced to increase the number of bits transmitted per clock cycle and, conversely, increased to reduce the number of bits transmitted per clock cycle. Thus, the number of bits transmitted per clock cycle may be adjusted to suit the situation.

Abstract: A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.

Abstract: A transmission interface module includes a receiving unit, a transmitting unit, a multiplexer, and a processing unit. An output terminal and a control terminal of the receiving unit are electrically connected to the processing unit. The input terminal and the control terminal of the transmitting unit are electrically connected to the processing unit, and the control terminal of the multiplexer is electrically connected to the processing unit. The transmission interface module respectively adjusts a turn-on state or a turn-off state of the analog power terminal, the digital power terminal, the processing unit, the receiving unit, the transmitting unit, and the multiplexer through a plurality of operation modes to transmit the detecting signals.

Abstract: A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a reference loading circuit uses a plurality of sampling switched capacitors connected in a switching configuration to selectively couple a first reference voltage and/or a second reference voltage to the central node by pre-charging the plurality of sampling switched capacitors with the first and second reference voltages during the sampling phase, and by coupling each of the first and second reference voltages to at least one of the plurality of sampling switched capacitors when connected to the central node during the gain phase.

Abstract: A photoelectric conversion device includes a pixel block including a plurality of pixels, a signal generating block, and a signal processing block. Each of the plurality of pixels includes a photoelectric conversion element to photoelectrically convert light striking the photoelectric conversion element into pixel data and output the pixel data; and a reset unit to reset electrical charge of the photoelectrically converted pixel data light and output a reset signal. The signal generating block includes a reference signal generator to generate a reference signal. The signal processing block performs correlated double sampling (CDS) on the reference signal to obtain correction data, and perform CDS on the pixel data and the reset signal to generate an output signal to correct the output signal with the correction data.

Abstract: A successive-approximation-register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal-independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal-independent (can be easily measured and corrected/calibrated).

Abstract: A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit.

Abstract: An integration circuit having multiple wells that allow for the simultaneous storage of charge during an integration interval and techniques for using the same provide benefits in dynamic range that enhance the performance of pixels. The circuit and techniques described herein could also be used in many different infrared focal plane array applications where higher dynamic range is desired and multiple gain state outputs are allowed.

Abstract: The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.

Abstract: An A/D converter includes an A/D conversion circuit for converting an analog output signal into a digital signal, and a control circuit for controlling the A/D conversion circuit. The control circuit acquires a digital signal of a first bit indicating which level regions the voltage level of the analog output signal corresponds to in accordance with a first conversion operation by the A/D conversion circuit, sets a reference voltage corresponding to the level region based on the first bit, amplifies the difference voltage between the analog output signal and the reference voltage to correspond to the A/D conversion input range of the A/D conversion circuit, outputs an amplified analog signal, acquires a digital signal of a second bit indicating the voltage level of the amplified analog signal in accordance with a second conversion operation by the A/D conversion circuit, and synthesizes the first bit and the second bit.

Abstract: An analog to digital converting circuit includes a correlated double sampling circuit (CDS) that compares a pixel signal with a ramp signal, and outputs a comparison signal, a timing amplifier that increases an active time of the comparison signal “N” times, and outputs an extended signal, wherein the “N” is a positive integer, and a counter that outputs a digital signal corresponding to the pixel signal in response to the extended signal and a first clock signal.

Abstract: An A/D converter includes: an integrator circuit executing ?? modulation to an analog signal to be converted; an adder outputting an addition result of at least an output signal of the integrator circuit and a first reference signal as a reference signal of ?? modulation; a quantizer receives an output signal of the integrator circuit, an output signal of the adder, and a second reference signal as a reference signal in cyclic A/D conversion to generate a result of quantization of the output signal of the integrator circuit and the output signal of the adder; and a controller is configured to switch between a ?? modulation mode and a cyclic mode.

Abstract: An apparatus for collecting data is provided. According to an example, the apparatus for collection data may include: n number of detector arrays, n number of DAS circuits and a back-end processor. Each of the DAS circuits may include an analog-to-digital converter and a front-end processor coupled with the analog-to-digital converter. Each of front-end processors is coupled with the back-end processor via an independent transmission line. For each of the detector arrays, the detector array may be configured to output analog signals based on detected scanning rays penetrating through a subject. The analog-to-digital converter may be configured to perform an analog-to-digital conversion on the analog signals to generate raw data. The front-end processor may be configured to logarithmically compress the raw data and transmit the logarithmically-compressed raw data to the back-end processor via the transmission line.

Abstract: A network platform manages the provisioning of a UE with a dominant identity profile and a recessive identity profile. The dominant profile is associated with a user's existing wireless data plan and the recessive profile corresponds to a data plan of a provider of device, or machine-to-machine, services to the UE. The UE uses the two profiles to transmit separate data contexts on separate respective bearers. When managing two separate bearers, the UE always uses the dominant profile first for managing a handoff to a stronger cell. The UE reports that the new cell that now serves the dominant context is the only cell that has enough strength to support the recessive context, even if other cells near the UE have signals strong enough. This necessarily causes the recessive context to always be handed off to the same cell to which the dominant context has already been handed off.

Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

Abstract: A SAR ADC includes a first capacitor array, a first comparator, a second capacitor array, a second comparator, an arbiter and a control circuit. The first capacitor array is arranged for receiving an input signal to generate a first signal. The first comparator is arranged for comparing the first signal with a first reference signal to generate a first comparison result. The second capacitor array is arranged for receiving the input signal to generate a second signal. The second comparator is arranged for comparing the second signal with a second reference signal to generate a second comparison result. The arbiter is arranged for generating an arbitration result according to the first comparison result and the second comparison result. The control circuit is arranged for generating an output signal according to the first comparison result, the second comparison result and the arbitration result.

Abstract: Systems and methods for improving computer technology related to the rendering and encoding of images are disclosed, preferably for use in a video-game environment. In certain embodiments, a codec is used to encode one or more reference images for a partial range of encoder settings and a renderer is used to generate one or more rendering quality-settings profiles, generate one or more reference images, calculate perceived qualities for each of the one or more reference images, re-render the one or more reference images for each of the one or more rendering quality-setting profiles, and calculate perceived qualities for each of the one or more re-rendered reference images. The renderer compares the perceived qualities of the reference images to the perceived qualities of the re-rendered images and matches them. Those matches result in an association of one or more encoder settings with their matching rendering quality-settings profiles into a look-up table.

Abstract: A sampling circuit comprises a switch circuit and a gate bootstrapping circuit. The switch circuit includes a switch input to receive an input voltage, a gate input, and a switch output. The gate bootstrapping circuit provides a boosted clock signal to the gate input of the switch circuit. The boosted voltage of the boosted clock signal tracks the input voltage by a voltage offset. The gate bootstrapping circuit includes a single boost capacitance coupled between a first circuit node and a second circuit node. A high supply voltage is applied to the first circuit node and the input voltage is applied the second circuit node to generate the boosted voltage on the single boost capacitance.

Abstract: Multiplying digital-to-analog converter (MDACs) are implemented in pipelined ADCs to generate an analog output being fed to a subsequent stage. A switched capacitor MDAC can be implemented by integrating a capacitor digital-to-analog converter (DAC) with charge pump gain circuitry. The capacitor DAC can implement the DAC functionality while the charge pump gain circuitry can implement subtraction and amplification. The resulting switched capacitor MDAC can leverage strengths of nanometer process technologies, i.e., very good switches and highly linear capacitors, to achieve practical pipelined ADCs. Moreover, the switched capacitor MDAC has many benefits over other approaches for implementing the MDAC.

Abstract: An SAR ADC and a conversion method, which include an SAR control logic circuit configured to control A/D conversion by: 1) sampling analog input signal for first time; 2) subjecting the sampled signal to conversions; 3) sampling analog input signal for another time; 4) subjecting the sampled signal in step 3) to conversion including: i) determining whether the lowest M bits of previous N-bit digital output signal are 1's or 0's, if so, looping back to step 2), otherwise, proceeding to step ii); ii) performing conversions on lowest M bits of new N-bit digital output signal, directly taking N-th to (M+1)-th bits of previous N-bit digital output signal as N-th to (M+1)-th bits of new N-bit digital output signal, and repeating steps 3) and 4) until the analog input signal is fully sampled and converted. Required cycles can be reduced resulting in higher conversion rate and lower power consumption.

Abstract: An apparatus for collecting data is provided. According to an example, the apparatus for collection data may include: n number of detector arrays, n number of DAS circuits and a back-end processor. Each of the DAS circuits may include an analog-to-digital converter and a front-end processor coupled with the analog-to-digital converter. Each of front-end processors is coupled with the back-end processor via an independent transmission line. For each of the detector arrays, the detector array may be configured to output analog signals based on detected scanning rays penetrating through a subject. The analog-to-digital converter may be configured to perform an analog-to-digital conversion on the analog signals to generate raw data. The front-end processor may be configured to logarithmically compress the raw data and transmit the logarithmically-compressed raw data to the back-end processor via the transmission line.

Abstract: An active receiver having a digital-pixel focal plane array (DFPA) ranges a target when observing return pulses from a pulsed laser beam synced with the receiver. The DFPA establishes a time when the pulsed laser beam contacts a target and the range can then be established because the speed at which the laser beam travels is known. Various basis functions may be implemented with the DFPA data to establish when the laser beam contacts the target. Some exemplary basis functions are binary basis functions, and other exemplary basis functions are Fourier basis functions.

Abstract: An ADC device comprises a comparator having an output, a first input, and a second input. And the ADC includes a SAR configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage. The ADC also includes a DAC configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a first voltage that is greater than the reference voltage such that a ratio N is equal to the reference voltage divided by the first voltage. The DAC also includes one or more first capacitors also coupled to the first voltage, where at least one first capacitor is associated with the MSB.

Abstract: An analog-to-digital converter with noise elimination is disclosed. The analog-to-digital converter converts a single-ended analog input into digital representation, and comprises an input buffer and an analog-to-digital conversion module. The input buffer outputs a positive differential signal and a negative differential signal based on the single-ended analog input. The analog-to-digital conversion module receives the positive differential signal and the negative differential signal to generate the digital representation. The input buffer further transmits a noise compensation signal to the analog-to-digital conversion module. The noise compensation signal contains noise information about noise transmitted from the input buffer to the analog-to-digital conversion module through the positive differential signal and the negative differential signal.

Abstract: An output circuit for use with a comparator includes a first transistor having a control terminal coupled to receive an output signal from a first stage of the comparator. A second transistor is coupled between the first transistor and a reference voltage. The second transistor has a control terminal coupled to receive a first reset signal. The second transistor is coupled to precharge a first output node of the first transistor between the first and second transistors to the reference voltage prior to a comparison operation of the comparator. An output stage has an input node coupled to the first output node. The output stage is coupled to generate an output voltage of the output circuit at an output node of the output stage in response to the first output node.

Abstract: Disclosed herein is a solid-state imaging element including a pixel unit configured to include a plurality of pixels arranged in a matrix and a pixel signal readout unit configured to include an analog-digital conversion unit that carries out analog-digital conversion of a pixel signal read out from the pixel unit. Each one of the pixels in the pixel unit includes a plurality of divided pixels arising from division into regions different from each other in optical sensitivity or a charge accumulation amount. The pixel signal readout unit reads out divided-pixel signals of the divided pixels in the pixel. The analog-digital conversion unit carries out analog-digital conversion of the divided-pixel signals that are read out and adds the divided-pixel signals to each other to obtain a pixel signal of one pixel.

Abstract: An offset compensation circuit comprises an error signal generation block arranged for receiving an input phase and an output phase, and for generating an error signal indicative of an error between the input phase and the output phase. Means are provided for combining the error signal with an offset compensation signal, yielding an offset compensated signal. A loop filter is arranged for receiving the offset compensated signal and for outputting the output phase. An offset compensation block is arranged for receiving the output phase and for determining the offset compensation signal. The offset compensation signal comprises at least a contribution proportional to a periodic function of the output phase.

Abstract: A time-of-flight (TOF) sensor includes a set of optical converters; each optical converter is configured to convert a reflection of the optical pulse from an object in the scene into an analog signal indicative of a time-of-flight of the optical pulse to the object. To that end, the set of optical converters produces a set of analog signals. The TOF sensor also includes at least one modulator to uniquely modulate each analog signal from the set of analog signals to produce a set of modulated signals, a mixer to mix the modulated signals to produce a mixed signal, and an analog to digital converter to sample the mixed signal to produce a set of data samples indicative of the TOF to the scene.

Abstract: A pipelined analog-to-digital converter (ADC) and a residue amplifier used in the ADC. An ADC includes a capacitive digital-to-analog converter (CDAC), a residue amplifier, and a switched capacitor circuit. The residue amplifier is coupled to the CDAC. The residue amplifier includes a first complementary transistor pair and a first tail current circuit. The first complementary transistor pair is coupled to a first output of the CDAC, and includes a high-side transistor and a low-side transistor. The first tail current circuit is coupled to the high side transistor. The switched capacitor circuit is coupled to inputs of the CDAC and to the first tail current circuit. The switched capacitor circuit is configured to generate a voltage to bias the first tail current circuit with compensation for common mode voltage at the inputs of the CDAC.

Abstract: An A/D converter includes an integrator having an operational amplifier, a first feedback capacitor, and a second feedback capacitor, a quantizer outputting a quantization result of an output signal of the operational amplifier, and a D/A converter having a D/A converter capacitor. The D/A converter capacitor has a first terminal connected to an input terminal of the operational amplifier and a second terminal connected to an output terminal of the operational amplifier. The D/A converter performs a subtraction operation by repeating subtraction of charges accumulated in the first and second feedback capacitors based on the quantization result, and performs a cyclic operation by sequentially repeating subtraction and amplification of the charges accumulated in one of the first and second feedback capacitors based on the quantization result.

Abstract: An oscillator-based sensor interface circuit comprises at least two oscillators, at least one of which is arranged for receiving an electrical signal representative of an electrical quantity being a converted physical quantity, phase detection means arranged to compare output signals of the at least two oscillators and for outputting a digital phase detection output signal in accordance with the outcome of the comparing, a feedback element arranged for converting a representation of the digital phase detection output signal into a feedback signal used directly or indirectly to maintain a given relation between oscillator frequencies of the at least two oscillators, detection means for detecting a difference between the at least two oscillators; and at least one tuning element arranged for receiving the detected difference and for tuning at least one characteristic of the oscillator-based sensor interface circuit.

Abstract: An active suspension system that interfaces a sprung mass and an unsprung mass is disclosed. The active suspension system includes a suspension comprising one or more actuators capable of exerting a force on the sprung mass to at least partially isolate motion of the sprung mass from motion of the unsprung mass. A user interface allows a user to indicate a desired degree of motion isolation.

Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460).

Abstract: An analog-to-digital converter (ADC) is disclosed. The ADC includes a successive approximation register and a voltage-to-time conversion element. The successive approximation register is configured to receive an input signal and to generate a first digital signal and a residue voltage. The voltage-to-time conversion element is configured to convert the residue voltage to a time domain representation. The voltage-to-time conversion element includes an amplifier having an input coupled to an output of the successive approximation register and configured to receive the residue voltage, and a zero crossing detector directly coupled to an output of the amplifier. A time-to-digital converter is coupled to an output of the zero crossing detector and is configured to generate a second digital signal.

Abstract: Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.

Abstract: The present application discloses an analog-to-digital conversion (ADC) circuit. The circuit includes an integral circuit including an operational amplifier and an integral capacitor. The circuit further includes a comparator and a timer. The operational amplifier includes a positive input terminal configured to receive a first voltage, a negative input terminal coupled to a signal-collection line configured to collect an analog current signal, and an output terminal configured to output a first output signal. The comparator is configured to compare the first output signal with a second voltage to generate a second output signal to the timer. The timer is configured to start a timing operation when the operational amplifier receives the analog current signal and end the timing operation when the second output signal changes. A binary data resulted from the timing operation characterizes a digital signal corresponding to the analog current signal.

Abstract: A signal processing apparatus includes: a difference signal acquirer configured to obtain a difference signal reflecting a change in an input signal at a preset time interval based on a reference signal; a signal amplifier configured to amplify the difference signal; and a signal restorer configured to generate an output signal by converting the amplified difference signal to a digital signal and summing the digital signal.

Abstract: Continuous-time pipeline analog-to-digital converters can achieve excellent performance, and avoid sampling-related artifacts traditionally associated with discrete-time pipeline ADCs. However, the continuous-time circuitry in the ADCs can pose a challenge for digital signal reconstruction, since the transfer characteristics of the continuous-time circuitry are not as well characterized or as simple as their discrete-time counterparts. To achieve perfect digital signal reconstruction, special techniques are used to implement an effective and efficient digital filter that combines the digital output signals from the stages of the CT ADCs.

Abstract: A peak/bottom detection circuit is disclosed. A comparator compares a voltage of one of three or more capacitors with an input voltage. A calculation amplifier amplifies the voltage of one of the three or more capacitors. Each of three or more switches respectively corresponding to the three or more capacitors connects a corresponding capacitor among the three or more capacitors to one of the comparator, the calculation amplifier, and a source of the input voltage. A controller generates control signals for sequentially switching connection destinations of the three or more capacitors and to supply the control signals to the three or more switches, respectively, in which the connection destinations of three capacitors among the three or more capacitors are different from each other.

Abstract: A device has a digital-to-analog converter to convert waveform data into analog waveforms, a waveform memory to store stored waveform data, an external waveform interface to receive real-time waveform data from an external device, a waveform multiplexer connected to the digital-to-analog converter to select between the first memory and the external waveform interface, a sequencer to receive and execute instructions to identify and access waveform data to drive the digital-to-analog converter, a sequencer instruction memory to provide stored instructions to the sequencer, an external instruction interface to receive real-time instructions for the sequencer, and a sequencer multiplexer to select between the sequencer instruction memory and the external instruction interface connected to the sequencer.

Abstract: A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.

Abstract: A Dynamic Triggering and Sample Engine (DTSE) that detects a first trigger received on a trigger input terminal that triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit. The DTSE then determines a first sequence configuration stored in a sequence configuration table that is associated with the first trigger, causes a first analog-to-digital conversion to be performed using the first sequence configuration; causes a first analog-to-digital conversion result value to be stored in a sequence result table; and outputs an interrupt to a processor indicating that the first analog-to-digital conversion result value is available in the sequence result table. The interrupt is output from the DTSE before all remaining analog-to-digital conversions in the series are completed. In response to receiving the interrupt, the processor reads the analog-to-digital result value from the sequence result table via a bus.

Abstract: A comparator includes a first comparison block suitable for sampling a pixel signal, comparing a sampled pixel signal with a coarse ramping voltage, outputting a first comparison signal, sampling a coarse step voltage and outputting a residue voltage as a difference voltage between the sampled pixel signal and a sampled coarse step voltage; and a second comparison block suitable for comparing a fine ramping voltage with the residue voltage of the first comparison block and outputting a second comparison signal.

Abstract: Encoding of Higher Order Ambisonics (HOA) signals commonly results in high data rates.

Abstract: A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.

Abstract: Disclosed is a method of receiving a compressive sensing signal and an apparatus for the same. According to an embodiment of the present disclosure, the method includes: receiving a signal processed using a predetermined dictionary set and a first sampling rate for each symbol group including one or more symbols; performing analog-to-digital conversion on the received signal at a second sampling rate that is lower than the first sampling rate; checking compressed measurement information from the signal on which analog-to-digital conversion is performed; and reconstructing values of the symbols included in the symbol group, which correspond to the compressed measurement information, on the basis of the predetermined dictionary set.

Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

Abstract: A method for processing a signal includes reading in a signal and filtering the signal using a first number of band-pass filters in order to obtain one band-pass filtered signal per band-pass filter. The first number of band-pass filters is configured to each allow distinct frequency ranges of the signal to pass. The method further includes calculating at least one signal parameter each from the plurality of band-pass filtered signals. The method further includes performing analog-to-digital conversion of the plurality of band-pass filtered signals or signals derived therefrom using a plurality of signal parameters such that a second number of analog-to-digital converters used to perform the analog-to-digital conversion is less than the first number of band-pass filters used to filter the signal.

Abstract: Data isolators for providing isolation between two ports that enable dynamic communication are described. The dynamic communication may be achieved by varying a ratio of the data rate relative to a clock frequency of a clock signal. The data isolator may include a first circuit that transmits data across an isolation barrier when the clock signal is in a first state and a second circuit that transmits data across the isolation barrier when the clock signal is in a second state. The clock frequency may be variable and, as a result, change the duration of data transmissions in a given clock cycle. For example, the clock frequency may be reduced to increase the number of bits transmitted per clock cycle and, conversely, increased to reduce the number of bits transmitted per clock cycle. Thus, the number of bits transmitted per clock cycle may be adjusted to suit the situation.

Abstract: Disclosed is a calibration circuit and method. The circuit includes: a DAC that outputs an analog parameter and includes output parameter adjustment circuitry; a comparator that receives a reference parameter and the analog parameter; and a control circuit (with select logic) connected to the comparator and DAC in a feedback loop. During a calibration mode, the magnitude of the analog parameter is adjusted by ½ DAC step in one direction and the feedback loop is used to perform a binary search calibration process. During an operation mode, the magnitude of the analog parameter is adjusted by ½ DAC step in the opposite direction. The select logic selects the DAC step identified by the calibration process or the next higher DAC step as a final DAC step. The control circuit outputs a final DAC code corresponding to the final DAC step and the DAC generates a calibrated parameter based thereon.