Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.

Abstract: Residue generation systems for use in continuous-time and hybrid ADCs are disclosed. An example residue generation system includes at least one stub filter, configured to generate a modified analog input based on an analog input, and a quantizer, configured to generate a digital input to a feedforward DAC based on the modified analog input generated by the filter. The feedforward DAC is configured to generate a feedforward path analog output based on the digital input generated by the quantizer, and the system may further be configured to generate a residue signal based on the feedforward path analog output. Providing one or more stub filters that filter the analog input before it is quantized by the quantizer advantageously allows blockers to be attenuated before they are sampled and aliased by the quantizer.

Abstract: A method of mass spectrometry is disclosed comprising digitizing a signal output from a detector to provide a first digitized signal. A finite impulse response (“FIR”) filter, a digital filter or an echo cancellation filter is applied to the first digitized signal in order to reduce the effect of baseline perturbations, echoes or ringing effects. Alternatively, an analog signal output from a detector is passed to one or more first power splitters or dividers, wherein one or more first transmission lines are attached to one or more ports of one more said first power splitters or dividers in order to reduce the effect of baseline perturbations, echoes or ringing effects.

Abstract: Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

Abstract: The present technology relates to an image sensor capable of achieving both higher S/N and higher frame rate, an electronic device, a control device, a control method, and a program. An AD converter has a comparator in which differential pairs are provided at an input stage. The differential pairs have a plurality of transistors as first transistors and second transistors paired to configure the differential pairs. The AD converter compares a level-changing reference signal with an electric signal output by a shooting unit for performing photoelectric conversion and outputting the electric signal, thereby performing AD conversion on the electric signal. The comparator is controlled such that a transistor to be operated is selected as active transistor from among the transistors depending on the amount of light incident in the shooting unit and the active transistor operates. The present technology is applicable to an image sensor for shooting an image, and the like, for example.

Abstract: A test and measurement instrument includes a coefficient storage facility coupled to a programmable filter. The coefficient storage facility is configured to store at least two pre-determined filter coefficient sets, and configured to pass a selected one of the at least two pre-determined filter coefficient sets to the filter based on a measurement derived using a compensation oscillator. The measurement may include clock delay and clock skew. In some examples the test and measurement instrument may additionally adjust clock delay and/or clock skew in addition to selecting appropriate filter coefficients.

Abstract: An A/D conversion device includes a phase-difference clock generation unit configured to use a plurality of phase interpolators to generate multi-phase clock signals, of which phases are shifted with respect to an input clock signal, from the input clock signal and a signal obtained by delaying the input clock signal; and an A/D conversion unit configured to perform A/D conversion on an input analog signal using the multi-phase clock signals generated by the phase-difference clock generation unit.

Abstract: An analog-to-digital converter (ADC) device includes analog-to-digital converter circuitries and a data output circuitry. The ADC circuitries correspond to channels respectively, and convert an input signal to generate quantization outputs according to interleaved clock signals, wherein each of the interleaved clock signals has a sampling frequency. The data output circuitry performs a down-sampling operation according to a first control signal and the quantization outputs, in order to generate a digital signal. The first digital signal is for determining a performance of the ADC circuitries, and a frequency of the digital signal is N/M times of the sampling frequency, and N is a positive integer and is a number of the channels.

Abstract: An analog-to-digital converter includes an analog-to-digital conversion unit configured to output first and second digital signals based on a comparison of first and second reference voltages with an input signal, an amplifier including first and second input terminals and an output terminal, a first capacitor having one end or electrode connected to the first input terminal of the amplifier, a second capacitor having one end or electrode connected to the first input terminal of the amplifier, a third capacitor having one end or electrode connected to the first input terminal of the amplifier, a switch unit configured to selectively provide a third or fourth reference voltage to at least one of the second and third capacitors based on the first and second digital signals, and a control switch between another end or electrode of the first capacitor and the output terminal of the amplifier.

Abstract: A bias-voltage-adjustable communications apparatus including a radio frequency RF part, an analog-to-digital converter, a digital baseband communications processor, a voltage controller, and a voltage generator. The RF part is coupled to the analog-to-digital converter and the voltage controller. The voltage generator is coupled to the analog-to-digital converter and the voltage controller. The analog-to-digital converter is coupled to the digital baseband communications processor.

Abstract: Systems and methods for improving computer technology related to the rendering and encoding of images are disclosed, preferably for use in a video-game environment. In certain embodiments, a codec is used to encode one or more reference images for a partial range of encoder settings and a renderer is used to generate one or more rendering quality-settings profiles, generate one or more reference images, calculate perceived qualities for each of the one or more reference images, re-render the one or more reference images for each of the one or more rendering quality-setting profiles, and calculate perceived qualities for each of the one or more re-rendered reference images. The renderer compares the perceived qualities of the reference images to the perceived qualities of the re-rendered images and matches them. Those matches result in an association of one or more encoder settings with their matching rendering quality-settings profiles into a look-up table.

Abstract: If spatial measurement point intervals in imaging mass analysis data of two samples to be compared are different and the degrees of spatial distribution spreading of substances are compared, one of the data is defined as a reference, the measurement point intervals in the other of the data are redefined so as to be equalized to the reference, and a mass spectrum at each virtual measurement point set as a result of the redefinition is obtained through interpolation or extrapolation based on a mass spectrum at an actual measurement points. If the arrays of the m/z values of mass spectra are different for each sample, the m/z value positions of the mass spectrum in one of the data are defined as a reference, and the intensity values corresponding to the reference m/z values are obtained through interpolation or extrapolation for the mass spectrum of the other of the data.

Abstract: Techniques are provided for compensating gain of a combined amplifier and analog-to-digital converter (ADC) circuit, for example, due to additional filtering added to an input of the circuit. In an example, an integrated circuit including an amplifier and ADC can include an amplifier circuit configured to receive an input signal and to amplify the input signal based on an input resistance and a feedback resistance, and to provide an amplified representation of the input signal, and an ADC circuit configured to receive an output of the amplifier, to determine a digital coefficient associated with an additional input resistance coupled to the amplifier, and to provide a compensated digital representation of the amplified representation of the input signal using the digital compensation coefficient.

Abstract: The embodiments described herein provide analog-to-digital converters and methods that can reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals while still providing the ability to perform an accurate analog-to-digital conversion. In general, the embodiments described herein reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals by pre-charging the sampling capacitor used in the conversion. For example, the embodiments can apply the buffered input signal apply to the sampling capacitor for a first sampling cycle to pre-charge the sampling capacitor, and then directly apply the unbuffered input signal to the sampling capacitor for a second sampling cycle to final-charge the sampling capacitor. With the sampling capacitor charged using the two stage charging, a digital output corresponding to the charge of the sampling capacitor is generated.

Abstract: Measurement apparatuses and methods are described. A measurement input is coupled with a first terminal of a capacitance via a first switch, and a reference voltage is coupled with the first terminal of the capacitance via a second switch. A measurement circuit is coupled to a second terminal of said capacitance.

Abstract: A semiconductor device that enables a memory size reduction is provided. The semiconductor device includes a converter circuit, a memory circuit, and a detection circuit. The converter circuit has a function of converting first data that includes a digital voltage value to second data that includes an analog current value. The memory circuit has a function of storing third data that includes an analog current value. The detection circuit has a function of generating data that indicates whether the analog current values of the second and third data match.

Abstract: A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C1-C128; and 4) selecting 64 groups of capacitors from C33 to C96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.

Abstract: An analog-digital converter may include: an analog-digital converter comprising: a ramp signal selection unit suitable for receiving ramp signals having different offsets, and sequentially selecting one of the ramp signals according to a preset order; a comparison unit suitable for comparing the magnitudes of the selected ramp signal with a pixel signal, and outputting a comparison signal according to the comparison result; and a counting unit suitable for counting the number of clocks of a clock signal until the comparison signal transitions, and outputting a count signal based on the count when the comparison signal transitions.

Abstract: An analog front end system can include a filter bypass switch connected in a boot-strapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage. Using bootstrapped switches can allow both the charge injection and capacitive coupling of the bypass switches of a differential anti-alias filter (AAF) to be common mode. A differential input signal of the ADC is not affected by the charge injection and capacitive coupling of the bypass switches in the AAF filter to a first order.

Abstract: The physical parameter measurement method is performed using an electronic circuit (1) with a resistive sensor (2). The resistive sensor includes two resistors (R1, R2) mounted in series, whose connection node connected to a moving mass (M), is connected to a first input of an amplifier-comparator (3). A second input of the amplifier-comparator receives a reference voltage. One output of the amplifier-comparator is connected to a logic unit (4), which provides a digital output signal (OUT). A digital-to-analog converter (5) provides a measurement voltage (Vdac), as a function of a digital signal provided by the logic unit, to the first resistor (R1) in a first phase of a measurement cycle, whereas the second resistor (R2) is polarized by a polarization voltage, and to the second resistor in a second phase, whereas the first resistor is polarized by a polarization voltage via a switching unit.

Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

Abstract: A comparator includes a first comparison block suitable for accumulating a difference value between a voltage of a pixel signal and a coarse step voltage, and outputting a residue voltage, representing a difference between a coarse ramping voltage of a ramp signal and the accumulated difference value; and a second comparison block suitable for comparing a fine ramping voltage to the residue voltage of the first comparison block and outputting a third comparison result signal.

Abstract: The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC.

Abstract: Disclosed is an automobile Bluetooth receiver, which includes a Bluetooth receiver and an automobile charger for plugging the Bluetooth receiver therein. The Bluetooth receiver includes a receiver housing, a Bluetooth receiver module, a rechargeable battery, a switch, a first magnetic element and a plug. The rechargeable battery is electrically connected to the Bluetooth receiver module, and the plug is electrically connected to the Bluetooth receiver module and the rechargeable battery. The automobile charger includes an automobile charger housing, a PCB, and a second magnetic element attachable to the first magnetic component; and the automobile charger housing has a plug hole formed thereon and disposed proximate to a side of the receiver housing for receiving a plug and the plug is plugged into the plug hole and electrically coupled to the PCB. This disclosure improves the reliability of the charging and the convenience of use.

Abstract: Provided is a signal generating apparatus including an inverse characteristic calculation unit that sets an amplitude characteristic of a signal as input data to calculate an inverse characteristic of a transfer function from an inverse characteristic of the amplitude characteristic of the input data, an inverse Fourier transform unit that performs inverse Fourier transform of the inverse characteristic of the transfer function, an impulse response extract unit that extracts points corresponding to a desired number of taps on the basis of a peak of the impulse response obtained by the inverse Fourier transform unit, a power spectrum calculation unit that calculates a power spectrum on the basis of values which are extracted from the impulse response, and a loss value correction unit that corrects a loss value of the power spectrum by using a loss value correction curve.

Abstract: Methods and systems for interference avoidance in a multi-protocol communication system may comprise receiving signals in a first communications protocol in a first frequency range and preventing interference signals from being generated in said first frequency range by configuring channel usage in a second communications protocol in a second frequency range based on said received signals. The configuring channel usage may include avoiding communicating in taboo channels and the received signals in said first communications protocol and signals in said configured channels in said second communications protocol may be communicated over one or more coaxial cables based on the configured channel usage. The taboo channels may be selected based on said received signals such that interference signals from said second frequency range do not occur in said first frequency range. The first frequency range comprises a cable or satellite television frequency range, or data over cable service interface standard (DOCSIS).

Abstract: An analog to digital conversion device according to one or more embodiments may include sequential comparison type analog to digital converters, wherein each of the analog to digital converters converts an analog signal to a digital signal by repeating comparative voltage generation processing to generate a comparative voltage and comparison processing to compare the analog signal with the comparative voltage. Each of the analog to digital converters may include a noise notification part that generates a noise notification signal to give notification of noise production and inputs the noise notification signal to a different one of the analog to digital converters. At start of operation, based on the notification noise signal inputted from the different analog to digital converter, each of the analog to digital converters may be synchronized with the different analog to digital converter performing the comparative voltage generation processing and the comparison processing.

Abstract: A semiconductor device includes: a plurality of input circuits each of which receives one of an analog signal and a digital signal, the input circuits being supplied a power supply; a selector that selects one of the input circuits; and an analog-to-digital (AD) converter that performs AD conversion of an analog signal input to the selected input circuit. After the selector selects one of the input circuits, the selector selects another of the input circuits. When the selector selects one of the input circuits and one digital signal of others of the input circuits is changed, the selector does not select another of the input circuits.

Abstract: A receiver for receiving an analog signal having a frequency band to be digitalized has a filter unit having at least two filters for at least two receive paths, an AD converter per receive path, and digital signal processing. The filters are coupled to a common signal source in order to obtain the analog signal having the frequency band to be digitalized, and configured to divide the frequency band to be digitalized into at least two sub-bands for the at least two receive paths. The analog-to-digital converters are configured to digitalize the signals of the at least two sub-frequency bands. The digital signal processing is coupled to the at least two analog-to-digital converters in order to obtain the at least two digitalized signals and merge the at least two signals to be digitalized. The at least two filters, with regard to their filter characteristics, are configured such that the at least two sub-frequency bands have a relative bandwidth of <1:2.

Abstract: An object of the disclosure is to provide a slope enhancement circuit, comprising an amplifier and a specific arrangement of capacitors and switches, further comprising a current digital to analog converter (IDAC), in a switched regulated current mirror. A method of sample and hold exploits the transient dynamics of the switched current mirror, to enhance the output current slope during PWM operation. A further object of the disclosure is to provide a low power, high speed switching type of regulated current mirror architecture. Still further, another object of the disclosure is to provide quick response to a sudden demand in current with a high degree of accuracy. Still further, another object of the disclosure is to provide a significant savings in circuit area.

Abstract: Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.

Abstract: To reduce fluctuations in image signals when the voltage of a negative power supply supplied to pixels changes. A pixel operates based on a first ground potential applied to a first ground line and outputs an analog image signal according to emitted light. An analog-digital converter operates based on a second ground potential applied to a second ground line, the second ground potential higher than the first ground potential, and converts the analog image signal into a digital image signal based on a reference voltage as a standard for the conversion. A reference voltage generation unit operates based on the second ground potential and generates the reference voltage. A reference voltage correction unit corrects the reference voltage generated according to a change in the first ground potential and supplies the reference voltage to the analog-digital converter.

Abstract: A method of offset calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration bit (B*LSB; B*MSB), analyzing a bit of the digital signal (COUT) and the calibration bit (B*LSB; B*MSB), determining an indication of a presence of offset error, and calibrating the offset error. As the determination of the calibration bit (B*LSB; B*MSB) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and thus can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Abstract: The equalization filter implements an equalization of at least one signal distorted by a measurement setup. The filter coefficients of the equalization filter can be determined by minimizing a cost function K in which only sequences of filter coefficients which exert significant influence on the equalization are taken into consideration.

Abstract: The present disclosure provides for dynamic resource allocation to a container on a host. For example, in a first directed acyclic graph (“DAG”), a CPU resource usage of a container may be detected. In a second DAG, an I/O resource usage of the container may be detected. In a third DAG, a network traffic resource usage of the container may be detected. Each detected resource may be associated with a distinct control group. Each detected resource usage may be compared to a detected service level objective (“SLO”). Resources that fail to meet the SLO may be adjusted. Each adjusted resource usage may be compared to the SLO, and any resources that continue to fail to meet the SLO may be further adjusted. An orchestrator may be notified when a resource has been adjusted to a threshold limit and the container may be migrated to a second host.

Abstract: A successive approximation register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal independent (can be easily measured and corrected/calibrated).

Abstract: A column-parallel dual-gain single-slope ADC comprises an input for receiving a signal Vin, a sample-and-hold stage which receives Vin and outputs sampled signal Vin,samp, a comparator, a counter, and a ramp generator which generates high-gain (HG) and low-gain (LG) ramps, with the ratio of the LG ramp slope to the HG ramp slope being greater than 1. During a coarse conversion phase, Vin,samp is compared with a threshold voltage Vthresh, and a flag is set to a first or second state depending on the comparison. During a fine conversion phase, if the flag is in the first state, the HG ramp is provided to the comparator and its output toggles when the ramp voltage becomes equal to Vin,samp. If the flag is in the second state, the LG ramp is provided to the comparator and its output toggles when the LG ramp voltage becomes equal to Vin,samp.

Abstract: Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

Abstract: Analog-to-digital conversion circuits are presented which employ magnetic tunnel junction (MTJ) elements that change state probabilistically in response to application of electrical pulses. Some implementations form a multi-channel analog-to-digital conversion circuit, with each channel comprising a magnetic tunnel junction (MTJ) element, and a pulse generator that determines characteristics of perturbation pulses to be applied to an MTJ element based at least on an analog input. The pulse generator also applies read pulses to the MTJ element to produce indications of magnetization state changes for the MTJ element due to application of the perturbation pulses. Each channel of the multi-channel analog-to-digital conversion circuit can include count circuitry that counts the indications of the magnetization state changes for an associated MTJ element. Outputs from each single-channel analog-to-digital converter are combined to determine a digital output representative of the analog input.

Abstract: One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current.

Abstract: The present technology relates to an image sensor, an electronic apparatus, a comparator, and a drive method enabling achievement of a noise reduction while maintaining high speed of AD conversion. An ADC for performing AD conversion for an electrical signal output from a pixel includes a comparator that compares the electrical signal and a reference signal, a level of which is changed and a counter that counts time necessary for a change of the reference signal to a coincidence of the electrical signal and the reference signal on the basis of output signals from the comparator. The comparator includes a differential amplifier that outputs a comparison result signal indicating a comparison result obtained by comparing the electrical signal and the reference signal and a plurality of output amplifiers that outputs signals obtained by amplifying the comparison result signal output from the differential amplifier as the output signals at different timings.

Abstract: To reduce fluctuations in image signals when the voltage of a negative power supply supplied to pixels changes. A pixel operates based on a first ground potential applied to a first ground line and outputs an analog image signal according to emitted light. An analog-digital converter operates based on a second ground potential applied to a second ground line, the second ground potential higher than the first ground potential, and converts the analog image signal into a digital image signal based on a reference voltage as a standard for the conversion. A reference voltage generation unit operates based on the second ground potential and generates the reference voltage. A reference voltage correction unit corrects the reference voltage generated according to a change in the first ground potential and supplies the reference voltage to the analog-digital converter.

Abstract: In a packet-based communication system, a transmitter and a receiver implement low power synchronization techniques. The transmitter transmits a packet that includes a two-part preamble. A first part of the two-part preamble is transmitted at a first reduced bandwidth that is smaller than a second bandwidth of the channel, and at least one of a second part of the two-part preamble and another portion of the packet is transmitted at the second bandwidth of the channel. The receiver includes an interleaved analog-to-digital converter (ADC) including multiple sub-ADCs. The receiver turns on a first subset of the multiple sub-ADCs during an idle listening period, and turns on a second subset of the multiple sub-ADCs upon detection of a completion of the first part of the two-part preamble, wherein the first subset of the multiple sub-ADCs is less than the second subset of the multiple sub-ADCs.

Abstract: A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to the digital output from the quantizer to generate a digital input to a feedforward DAC, based on which the DAC can generate a feedforward path analog output. The apparatus further includes means for applying a second, continuous-time, transfer function to the analog input provided to the quantizer to generate a forward path analog output, and a subtractor for generating a residue signal based on a difference between the forward path analog output and the feedforward path analog output. Proposed apparatus allows selecting a combination of the first and second transfer functions so that, when each is applied in its respective path, the residue signal passed to further stages of an ADC is reduced.

Abstract: A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.

Abstract: Sampling accuracy during sampling of analog input signals may be improved by performing an “auto-zero every sample” procedure. The ratio of input signal samples to zero input samples for the sampling time interval defined by the sampling frequency may be determined based on the sampling frequency. For sampling frequencies equal to or less than a specified frequency characteristic of the signal conditioning path of the analog input signal, the ratio may be set to unity (one). For sampling frequencies above the specified frequency, the ratio may be set to be greater than unity (one), and may be a power-of-two. A digital signal processing block may include independent digital signal processing paths for the input signal measurements and the zero input measurements. Each signal processing path may include a low-pass infinite impulse response filter, an average decimation finite impulse response filter, and a binary shifter to allow for the adjustable ratio.

Abstract: A method is provided in one example and includes receiving a data signal, receiving an interference signal, wherein the interference signal is copied to create a reference data interference signal, combining the data signal and the interference signal to create a combined signal, using an analog echo cancellation engine on the combined signal to create an analog echo cancellation signal, and using a digital echo cancellation engine on the analog echo cancellation signal to create a data with echo cancellation signal. The data with echo cancellation signal can be communicated using a coaxial cable.

Abstract: This application relates to modulators for providing time-encoded signals and in particular PWM signals. A modulator (200) has a first controlled oscillator (201P) configured to receive a first oscillator driving signal and output a first oscillation signal (S1). An accumulator (204) is configured to provide an accumulator value (VAL) based on a number of pulses of the first oscillation signal and a hysteretic comparator (205) alternates between first and second output states based on a hysteretic comparison of the accumulator value with a defined reference (REF). The first oscillator driving signal is based on a combination of an input signal and a feedback signal derived from an output of the hysteretic comparator.

Abstract: A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.

Abstract: A first mode in which to output analog electricity quantities of objects one by one independently to an A/D converter, a second mode in which to output none of the analog electricity quantities of the objects, a third mode in which to output none of the analog electricity quantities of the objects and cause the output to the A/D converter to be resistor, and a fourth mode in which to output to the A/D converter a plurality of the analog electricity quantities of the objects at the same time, are caused to be generated, thus acquiring the A/D conversion values of the objects individually when in the first mode, and detecting an anomaly of the A/D converter itself or a device connected to the A/D converter when in the second mode to the fourth mode.