Abstract: Capacitors and methods of making the same are disclosed herein. In one embodiment, a capacitor comprises a structure having first and second oppositely facing surfaces and a plurality of pores each extending in a first direction from the first surface towards the second surface, and each having pore having insulating material extending along a wall of the pore; a first conductive portion comprising an electrically conductive material extending within at least some of the pores; and a second conductive portion comprising a region of the structure consisting essentially of aluminum surrounding individual pores of the plurality of pores, the second conductive portion electrically isolated from the first conductive portion by the insulating material extending along the walls of the pores.

Abstract: A capacitor forming unit according to one embodiment includes a dielectric plate with a plurality of through holes; a first conductor film formed on an upper surface of the dielectric plate; a first insulator film formed on the front end portion of the upper surface of the dielectric plate; a second conductor film formed on a lower surface of the dielectric plate; a second insulator film formed on the rear end portion of the lower surface of the dielectric plate; first electrode rods disposed in some of the through holes; and second electrode rods disposed in the remaining through holes where the first electrode rods are not disposed. The first electrodes are electrically connected to the first conductor film and electrically insulated from the second conductor film. The second electrode rods are electrically connected to the second conductor film and are electrically insulated from the first conductor film.

Abstract: An apparatus having reduced phononic coupling between a graphene monolayer and a substrate is provided. The apparatus includes an aerogel substrate and a monolayer of graphene coupled to the aerogel substrate.

Abstract: An apparatus having reduced phononic coupling between a graphene monolayer and a substrate is provided. The apparatus includes an aerogel substrate and a monolayer of graphene coupled to the aerogel substrate.

Abstract: A capacitor having improved tolerance to humidity. The capacitor includes a packaging material and/or a dielectric material comprising a film having a water vapor transmission rate significantly lower than the dielectric films and/or packaging films used in conventional capacitors.

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

Abstract: A capacitor, and methods of its manufacture, having improved capacitance efficiency which results from increasing the effective area of an electrode surface are disclosed. An improved “three-dimensional” capacitor may be constructed with electrode layers having three-dimensional aspects at the point of interface with a dielectric such that portions of the electrode extend into the dielectric layer. Advantageously, embodiments of a three-dimensional capacitor drastically reduce the space footprint that is required in a circuit to accommodate the capacitor, when compared to current capacitor designs. Increased capacitance density may be realized without using high k (high constant) dielectric materials, additional “electrode—dielectric—electrode” arrangements in an ever increasing stack, or serially stringing together multiple capacitors.

Abstract: Method for producing a laminated ceramic electronic component including: forming a laminated body by layering and press-bonding a plurality of ceramic green sheets to become a protective layer and a plurality of the ceramic green sheets with metal paste printed thereon, forming an extended part by printing and drying a conductive paste for the extended part on the main face of the laminated body, forming a laminated ceramic element by cutting off the laminated body with the extended part formed and separating the laminated body into fragments, and forming a curled part by applying a conductive paste for the curled part on said end face of said laminated ceramic element. In the step of forming the laminated body, the laminated body is press-bonded so that the main face of the lead part of the laminated body is positioned lower than the main face of the function part.

Abstract: In a laminated capacitor, one additional first internal electrode layer, which has its edge connected to the first external electrode as do the first internal electrode layers, is provided to one of the five first internal electrode layers so as to face one another via the second dielectric layer having a thickness smaller than the thickness of the first dielectric layer and not contributing to the formation of capacity, and one additional second internal electrode layer, which has its edge connected to the second external electrode as do the second internal electrode layers, is provided to one of the five second internal electrode layers so as to face one another via the third dielectric layer having a thickness smaller than the thickness of the first dielectric layer and not contributing to the formation of capacity.

Abstract: The present invention relates to a highly dielectric film formed by using (A) a fluorine-containing resin comprising vinylidene fluoride unit and tetrafluoroethylene unit in a total amount of not less than 95% by mole, and provides a film for a film capacitor which has high dielectric property and high withstanding voltage and can be made thin.

Abstract: Disclosed are a multilayer ceramic condenser and a method for manufacturing the same. There is provided a multilayer ceramic condenser including: a multilayer main body in which a plurality of dielectric layers including a first side, a second side, a third side, and a fourth side are stacked; a first cover layer and a second cover layer forming the plurality of dielectric layers; a first dielectric layer disposed between the first cover layer and the second cover layer and printed with a first inner electrode pattern drawn to the first side; a second dielectric layer alternately stacked with the first dielectric layer and printed with a second inner electrode pattern drawn to the third side; and a first side portion and a second side portion each formed on the second side and the fourth side opposite to each other.

Abstract: The described embodiments relate generally to a capacitor assembly for mounting on a printed circuit board (PCB) and more specifically to designs for mechanically isolating the capacitor assembly from the PCB to reduce an acoustic noise produced when the capacitor imparts a piezoelectric force on the PCB. Termination elements in the capacitor assembly, including a porous conductive layer in the capacitor assembly may reduce an amount of vibrational energy transferred from the capacitor to the PCB. Termination elements including a soft contact layer may also reduce the amount of vibrational energy transferred to the PCB. Further, capacitor assemblies having thickened dielectric material may reduce the amount of vibrational energy transferred to the PCB.

Abstract: Provided is a laminated ceramic capacitor that can suppress the decrease in insulation resistance after a moisture-resistance loading test. It contains ceramic layers which include: main-phase grains that have a perovskite-type compound containing Ba and Ti and optionally containing Ca, Sr, Zr, and Hf; and secondary-phase grains that have an average grain size of 100 nm or more and have a Si content of 50 mol % or more per grain, the average grain boundary number, represented by (Average Thickness for Ceramic Layers 3)/(Average Grain Size for Main Phase Grains)?1, is greater than 0 and 3.0 or less, and the average grain size for the secondary-phase grains is ¼ or more of the average thickness for the ceramic layers 3.

Abstract: There is provided a multilayer ceramic capacitor. The capacitor includes: a multilayer body having a dielectric layer; and first and second internal electrodes disposed in the multilayer body, the dielectric layer being disposed between the first and second internal electrodes, wherein, in a cross-section taken in a width-thickness direction of the multilayer body, an offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap with each other, and a ratio (t1/td) of a width t1 of the offset portion to a thickness td of the dielectric layer is 1 to 10.

Abstract: In a ceramic capacitor, first and second electrode terminals each include a bonded-to-substrate portion, a first bonded-to-electrode portion bonded to a first edge of one of first and second external electrodes, a second bonded-to-electrode portion bonded to a second edge of the one of first and second external electrodes and disposed at a distance from the first bonded-to-electrode portion in the first directions, and a connecting portion connecting the first and second bonded-to-electrode portions and the bonded-to-substrate portion. W1/W0 is about 0.3 or more, and h/L is about 0.1 or more.

Abstract: A region where a plating film constituting an external electrode is formed can be accurately controlled in an electronic component in which the external electrode is formed by directly plating a particular region in a surface of a component body. In a component body, a bump is provided in a position in which a region where an external electrode should be formed is partitioned. In a plating process, growth of the plating film constituting the external electrode is substantially stopped or delayed in the bump. As a result, a termination point of the growth of the plating film constituting the external electrode can be accurately controlled in the position of the bump.

Abstract: An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source is coupled to a ground rail, and the first drain to an I/O pad; providing a gate driver control circuit including a second NMOS transistor having a second source, a second drain, and a second gate; and coupling the second drain to the first gate, the second source to the ground rail, wherein the gate driver control circuit provides a ground potential to the first gate during an ESD event occurring from the I/O pad to the ground rail.

Abstract: Solid-state thin-film capacitors are provided. Aspects of the solid-state thin-film capacitors include a first electrode layer of a transition metal, a dielectric layer of an oxide of the transition metal, and a second electrode layer of a metal oxide. Also provided are methods of making the solid-state thin-film capacitors, as well as devices that include the same. The capacitor may have one or more cathodic arc produced structures, i.e., structures produced using a cathodic arc deposition process. The structures may be stress-free metallic structures, porous layers and layers displaying crenulations. Aspects of the invention further include methods of producing capacitive structures using chemical vapor deposition and/or by sputter deposition.

Abstract: A capacitor and a manufacturing method thereof with improved capacitance density, simplified production process, and/or improved high frequency characteristic without having to form a nano-scale pattern are provided. A capacitor element 12 includes a dielectric layer made of porous oxide substrate, first and second internal electrodes formed within holes of the porous oxide substrate, a first external electrode electrically connected to the first internal electrode, a second external electrode electrically connected to the second internal electrodes.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at % carbon. The method includes forming an opening through at least the support material where the opening has an aspect ratio of at least 20:1 within a thickness of the support material. After forming the opening, the method includes processing the support material to effect a reduction in conductivity, and forming a capacitor structure in the opening.

Abstract: A capacitive device includes a first capacitor including a first wiring layer, a first dielectric film, a first conductive layer, a first insulating layer on the first capacitor, a second capacitor on the first insulating layer including a second conductive layer, a second dielectric film, and a third conductive layer, a second insulating layer on the second capacitor, a second wiring layer on the second insulating layer including first and second connection wires, a first via connecting the first wiring layer to the second conductive layer, a second via connecting the third conductive layer to the second wiring layer, a third via connecting the first connection wire to the first conductive layer, and a fourth via connecting the second connection wire to the first wiring layer.

Abstract: A structural capacitor includes a first carbon fiber material layer, a second carbon fiber material layer, and an interlayer dielectric including a diamond-like-carbon material layer.

Abstract: In a structure or device having a pair of electrical conductors separated by an insulator across which a voltage is placed, resistive layers are formed around the conductors to force the electric potential within the insulator to distribute more uniformly so as to decrease or eliminate electric field enhancement at the conductor edges. This is done by utilizing the properties of resistive layers to allow the voltage on the electrode to diffuse outwards, reducing the field stress at the conductor edge. Preferably, the resistive layer has a tapered resistivity, with a lower resistivity adjacent to the conductor and a higher resistivity away from the conductor. Generally, a resistive path across the insulator is provided, preferably by providing a resistive region in the bulk of the insulator, with the resistive layer extending over the resistive region.

Abstract: A method for manufacturing a multilayer ceramic electronic component significantly reduces and prevents swelling or distortion when a conductive paste is applied to a green ceramic element body. A ceramic green sheet used in the method satisfies 180.56?A/B wherein A is a polymerization degree of an organic binder contained in the ceramic green sheet, and B is a volume content of a plasticizer contained in the ceramic green sheet.

Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.

Abstract: An assembly includes a plurality of energy storage components. An energy storage component is electrically coupled to at least two other energy storage components of the plurality by at least two electrical pathways, each including a fusible link. The at least two electrical pathways may be formed in a circuit board. The energy storage component may be coupled to the circuit board by a fusible link.

Abstract: Provided is a package type multi-layer thin film capacitor for large capacitance, including: a ceramic sintered body formed with slots on one side and another side thereof, respectively; a plurality of first internal electrode layers formed within the ceramic sintered body; a plurality of second internal electrode layers formed within the ceramic sintered body to be positioned between the plurality of first internal electrode layers; a pair of first main connection electrode members inserted into the slots to be connected to the first internal electrode layers or the second internal electrode layers, respectively; a pair of first main lead members inserted into the slots and to be connected to the first main connection electrode members, respectively; and a sealing member sealing the ceramic sintered body to partially expose each of the pair of first main lead members.

Abstract: Disclosed herein is a composite material comprising a relaxor ferroelectric material and a hydrazine-reduced graphene oxide, wherein the weight ratio of the composite material to the hydrazine-reduced graphene oxide is 9:1 to 200:1. The composite materials have high dielectric permittivity and low dielectric losses and can be used to manufacture various high dielectric permittivity components.

Abstract: An electrical contact includes a body having a mating segment. At least a portion of the mating segment defines a first conductive element having a three-dimensional (3D) surface. A dielectric layer is formed directly on the 3D surface of the first conductive element in engagement with the 3D surface. A second conductive element is formed on the dielectric layer such that the dielectric layer extends between the first and second conductive elements. The first and second conductive elements and the dielectric layer form a capacitor.

Abstract: A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

Abstract: Disclosed are apparatus and methodology for providing a precision laser adjustable (e.g., trimmable) thin film capacitor array. A plurality of individual capacitors are formed on a common substrate and connected together in parallel by way of fusible links. The individual capacitors are provided as laddered capacitance value capacitors such that a plurality of lower valued capacitors corresponding to the lower steps of the ladder, and lesser numbers of capacitors, including a single capacitor, for successive steps of the ladder, are provided. Precision capacitance values can be achieved by either of fusing or ablating selected of the fusible links so as to remove the selected subcomponents from the parallel connection. In-situ live-trimming of selected fusible links may be performed after placement of the capacitor array on a hosting printed circuit board.

Abstract: An electrical multi-layered component includes a monolithic base member that has a plurality of ceramic layers and electrode layers disposed one on top of the other in alternating fashion. The base member includes two end surfaces opposite to one another and two side surfaces opposite to one another. The multi-layered component includes a plurality of external electrodes and a plurality of internal electrodes designed into the electrode layers. The internal electrodes at least partially overlap and form overlap areas. Each internal electrode is associated with a respective external electrode. At least one first internal electrode extending from an end surface overlaps with at least one second internal electrode (8) extending from an opposite end surface. At least a third internal electrode extends from an end surface.

Abstract: There is provided a capacitor, including: a substrate part including a first substrate having a groove portion and a second substrate positioned above the first substrate and having a protrusion portion; a first capacitance part formed on one surface of the first substrate and having a shape corresponding to that of the groove portion; and a second capacitance part formed on one surface of the second substrate and having a shape corresponding to that of the protrusion portion.

Abstract: An organic compound has the following chemical structure: wherein R is different from R*; R and R* are independently hydrogen, halogen, nitro or methoxyl; and R1 is a C1-C6 alkyl or a phenyl group. A quaternary data storage device includes a bottom electrode, a top electrode, and the organic film layer sandwiched between the bottom electrode and the top electrode.

Abstract: An electrical circuit arrangement provides a substrate and at least two conductive surfaces. The substrate comprises at least one layer disposed between the conductive surfaces. The conductive surfaces form a capacitor and overlap in part and form an overlapping area. In the event of a displacement of the conductive surfaces relative to one another, the resulting overlapping area is largely constant up to a threshold value of the displacement.

Abstract: There is provided a thin highly dielectric film for a film capacitor being excellent in mechanical strength, in which highly dielectric inorganic particles can be blended to a dielectric resin at high ratio, and rubber particles (B) and preferably highly dielectric inorganic particles (C) are dispersed in a thermoplastic resin (A).

Abstract: A feedthrough capacitor includes an inner electrode that extends coaxially within a grounded outer electrode. A non-conductive, epoxy-based potting material insulates and adhesively joins opposing roughened portions of the inner and outer electrodes. A capacitor assembly extends between the inner and outer electrode and serves to bypass relatively high frequency signals carried by the inner electrode to the grounded outer electrode. The capacitor assembly includes a plurality of monolithic multilayer ceramic capacitors, each capacitor having first and second terminals that are respectively surface mounted onto inner and outer concentric conductive rings. A plurality of deflectable tines project radially inward from the inner ring and resiliently circumferentially contact the exterior of the inner electrode. Similarly, a plurality of deflectable tines project radially outward from the outer ring and resiliently circumferentially contact the interior of the outer electrode.

Abstract: In a multilayer ceramic electronic component, when a region of a ceramic body in layers where neither of a first internal electrode and a second internal electrode is provided as viewed in a direction in which a plurality of ceramic layers are stacked on one another is defined as a non-effective layer region, a dummy lead-through conductor is arranged in the non-effective layer region so as to lead to at least two locations on portions of superficies of the ceramic body and be electrically connected to a second external electrode. When a conductive medium is brought into contact with one of a plurality of exposed edges of the dummy lead-through conductor, a current is also applied to the other exposed edges.

Abstract: A dielectric material suitable for use between electrodes of a capacitor includes dipole-impregnated fullerenes able to increase a dielectric constant of the dielectric material in order to enhance the energy storage capacity of the capacitor is provided. The dielectric material includes buckminsterfullerenes each having a dipole molecule impregnated within the buckminsterfullerene, the dipole molecules within the buckminsterfullerenes able to rotate and align with forces of an electric field when in the presence of the electric field so that, when in use between the electrodes of the capacitor, they counteract the electric field between the electrodes and increase the energy storage capacity of the capacitor.

Abstract: A capacitor includes a dielectric layer having a first plane, a second plane opposite to the first plane, and first and second through-holes communicated with the first plane and the second plane; a first external conductor layer disposed on the first plane; a second external conductor layer disposed on the second plane; a first internal electrode formed in the first through-hole, connected to the first external electrode layer, disposed in the second hole diameter part at a tip and separated from the second external electrode layer; and a second internal electrode formed in the second through-hole, connected to the second external electrode layer, and separated from the first external electrode layer.

Abstract: An article of manufacture comprises an electrically conductive plate and one or more hybrid layers stacked on the electrically conductive plate. Each of the one or more hybrid layers comprises a respective sheet comprising graphene. Each of the one or more hybrid layers also comprises a respective plurality of particles disposed on the respective sheet. Finally, each of the one or more hybrid layers comprises a respective ion conducting film disposed on the respective plurality of particles and the respective sheet.

Abstract: An integrated capacitive device includes an electrically conducting comb, at least some of whose teeth form first electrodes of capacitors, and electrically conducting fingers extending between the teeth of the comb so as to form second electrodes of the capacitors. The device includes a first finger-teeth set having a single reference finger forming a reference capacitor having a reference capacitive value, at least one second finger-teeth set including several fingers, the reference finger and the number of fingers of the second finger-teeth set or sets forming a geometric series with ratio two. At least one additional set includes a single additional finger forming, with at least one tooth of the comb, an additional capacitor having an additional capacitive value substantially equal to half the reference capacitive value.

Abstract: Methods of manufacturing metal-insulator-metal capacitor structures, and the metal-insulator-metal capacitor structures obtained, are disclosed. In one embodiment, a method includes providing a substrate, forming on the substrate a first metal layer comprising a first metal, and using atomic layer deposition with an H2O oxidant to deposit on the first metal layer a protective layer comprising TiO2. The method further includes using atomic layer deposition with an O3 oxidant to deposit on the protective layer a dielectric layer of a dielectric material, and forming on the dielectric layer a second metal layer comprising a second metal. In another embodiment, a metal-insulator-metal capacitor includes a bottom electrode comprising a first metal, a protective layer deposited on the bottom electrode and comprising TiO2, a dielectric layer deposited on the protective layer and comprising a dielectric material, and a top electrode formed on the dielectric layer and comprising a second metal.

Abstract: A thin film capacitor includes a substrate and a dielectric thin film element formed on the substrate. The substrate can include an Si plate, an SiO2 film on the Si plate, and a Ti film formed on the SiO2 film. The dielectric thin film element includes a lower electrode, a dielectric thin film on the lower electrode, and an upper electrode formed on the dielectric thin film. The dielectric thin film is a thin film formed of a nanosheet, and a void portion of the dielectric thin film is filled with a p-type conductive organic polymer. Ti0.87O2, Ca2Nb3O10 or the like, is used as a dielectric material to form a major component of the nanosheet. As the p-type conductive organic polymer, polypyrrole, polyaniline, polyethylene dioxythiophene or the like, is suitable.

Abstract: A multilayer ceramic capacitor, having a plurality of electrode layers and a plurality of substantially titanium dioxide dielectric layers, wherein each respective titanium dioxide dielectric layer is substantially free of porosity, wherein each respective substantially titanium dioxide dielectric layer is positioned between two respective electrode layers, wherein each respective substantially titanium dioxide dielectric layer has an average grain size of between about 200 and about 400 nanometers, wherein each respective substantially titanium dioxide dielectric layer has maximum particle size of less than about 500 nanometers. Typically, each respective substantially titanium dioxide dielectric layer further includes at least one dopant selected from the group including P, V, Nb, Ta, Mo, W, and combinations thereof, and the included dopant is typically present in amounts of less than about 0.01 atomic percent.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: A capacitor includes a dielectric substrate and a large number of filamentous conductors formed to penetrate through the dielectric substrate in a thickness direction thereof. An electrode is connected to only respective one ends of a plurality of filamentous conductors constituting one of groups each composed of a plurality of filamentous conductors. The electrode is disposed in at least one position on each of both surfaces of the dielectric substrate, or in at least two positions on one of the surfaces. Further, an insulating layer is formed on each of both surfaces of the dielectric substrate so as to cover regions between the electrodes, and a conductor layer is formed on the corresponding insulating layer integrally with a desired number of electrodes.

Abstract: A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; first and second external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of a formation of capacitance within the lower cover layer.

Abstract: There is provided a multi-layered ceramic capacitor having a dual layer-electrode structure formed by applying a dual layer of electrode paste to the multi-layered ceramic capacitor. The multi-layered ceramic capacitor having a dual layer-electrode structure includes a capacitor body having a preset length and width and having a plurality dielectric layers stacked therein, an internal electrode unit formed on the plurality of dielectric layers and having a preset capacitance, and an external electrode unit including first external electrodes respectively formed on both sides of the capacitor body to be electrically connected to internal electrodes, and second external electrodes formed on the first external electrodes.

Abstract: A ceramic electronic component includes a plurality of first reinforcement layers. The plurality of first reinforcement layers are arranged in a first outer layer portion so as to extend in the length direction and in the width direction, and are stacked in the thickness direction. The volume proportion of the plurality of first reinforcement layers in a region of the ceramic body in which the plurality of first reinforcement layers are provided is greater than the volume proportion of the first and second internal electrodes in an effective portion.