Abstract: A conductive structure, including an adhesion layer and a conductor in contact with the adhesion layer and having a thickness of less than six hundred Angstroms. The present invention may be used to form a capacitor, including an adhesion layer, a first conductor in contact with the adhesion layer and having a thickness of less than six hundred Angstroms, a second conductor, and a dielectric between the first and second conductors. The present invention is also directed towards structures wherein iridium or rhodium may be used in place of the combination of the adhesion layer and conductor.

Abstract: In a feed-through capacitor, a conduction unit having a plurality of conduction inner electrodes can fully secure a tolerable level of DC. A capacitor unit is formed on the mount surface side in a capacitor body, so that high-frequency noise components can be removed by the capacitor unit before reaching the conduction unit. The distance between the grounding inner electrode located closest to the conduction unit and the conduction inner electrode in the conduction unit is greater than that between the signal inner electrode and grounding inner electrode in the capacitor unit. This enhances the impedance between the capacitor unit and the conduction unit, so as to inhibit the high-frequency noise components from flowing into the conduction unit.

Abstract: A method of adjustment in the manufacture of a capacitance of a capacitor supported by a substrate, the method including the steps of: a) forming a first electrode parallel to the surface of the substrate and covering it with a dielectric layer; b) forming, on a first portion of the dielectric layer, a second electrode; c) measuring the capacitance between the first electrode and the second electrode, and deducing therefrom the capacitance to be added to obtain the desired capacitance; d) thinning down a second portion of the dielectric layer, which is not covered by the second electrode, so that the thickness of this second portion is adapted to the forming of the deduced capacitance; and e) forming a third electrode on the thinned-down portion and connecting it to the second electrode.

Abstract: A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.

Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.

Abstract: The present invention provides a nonporous highly dielectric film which can improve withstanding voltage, insulating property and dielectric constant, especially can decrease a dielectric loss at high temperatures and can be made thin, and a coating composition for forming the highly dielectric film comprising (A) a vinylidene fluoride resin, (B) a cellulose resin and (C) a solvent.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A stacked film capacitor including a resin protective film having excellent durability is provided which can stably secure desired properties. The stacked film capacitor includes a capacitor element including a plurality of dielectric layers, and a plurality of vapor-deposited metal film layers. Each dielectric layer and each vapor-deposited metal film layer are stacked with each other so as to be arranged alternately. The stacked film capacitor further includes a pair of external electrodes provided on opposing side surfaces of the capacitor element, and at least one resin protective film formed on at least one side surfaces other than the side surfaces on which the external electrodes are formed, in which the at least one resin protective film is provided by deposition polymerization.

Abstract: In a laminated capacitor, one additional first internal electrode layer, which has its edge connected to the first external electrode as do the first internal electrode layers, is provided to one of the five first internal electrode layers so as to face one another via the second dielectric layer having a thickness smaller than the thickness of the first dielectric layer and not contributing to the formation of capacity, and one additional second internal electrode layer, which has its edge connected to the second external electrode as do the second internal electrode layers, is provided to one of the five second internal electrode layers so as to face one another via the third dielectric layer having a thickness smaller than the thickness of the first dielectric layer and not contributing to the formation of capacity.

Abstract: A metallized film capacitor includes a dielectric film and two metal vapor-deposition electrodes facing each other across the dielectric film. At least one of the metal vapor-deposition electrodes is made of substantially only aluminum and magnesium. This metallized film capacitor has superior leak current characteristics and moisture resistant performances, and can be used for forming a case mold type capacitor with a small size.

Abstract: a composite dielectric thin film capable of high dielectric constant, low leakage current characteristics, and high dielectric breakdown voltage while being deposited at a room temperature, a capacitor and a field effect transistor (FET) using the same, and their fabrication methods. The composite dielectric thin film is deposited at a room temperature or less than 200° C. and comprises crystalline or amorphous insulating filler uniformly distributed within an amorphous dielectric matrix or within an amorphous and partially nanocrystalline dielectric matrix.

Abstract: There is provided a multilayer ceramic capacitor. The capacitor includes: a multilayer body having a dielectric layer; and first and second internal electrodes disposed in the multilayer body, the dielectric layer being disposed between the first and second internal electrodes, wherein, in a cross-section taken in a width-thickness direction of the multilayer body, an offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap with each other, and a ratio (t1/td) of a width t1 of the offset portion to a thickness td of the dielectric layer is 1 to 10.

Abstract: In an electronic component, a laminate includes a plurality of laminated ceramic layers and a mounting surface defined by outer edges of the plurality of laminated ceramic layers, the outer edges being continuously located adjacent to each other. Capacitor conductors are disposed on the ceramic layers and include exposed portions that are exposed at the mounting surface between the ceramic layers. An electroconductive layer defining an external electrode is arranged to directly cover the exposed portions and is formed by plating so as to be made of plated material. Another electroconductive layer covers the above-mentioned electroconductive layer and partially covers surfaces of the laminate, and it is made of a material including metal and one of glass and resin.

Abstract: A PZT-based ferroelectric thin film formed on a lower electrode of a substrate having the lower electrode in which the crystal plane is oriented in a (111) axis direction, having an orientation controlling layer which is formed on the lower electrode and has a layer thickness in which a crystal orientation is controlled in a (111) plane preferentially in a range of 45 nm to 270 nm, and a film thickness adjusting layer which is formed on the orientation controlling layer and has the same crystal orientation as the crystal orientation of the orientation controlling layer, in which an interface is formed between the orientation controlling layer and the film thickness adjusting layer.

Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.

Abstract: Systems and methods in accordance with embodiments of the invention implement micro- and nanoscale capacitors that incorporate a conductive element that conforms to the shape of an array elongated bodies. In one embodiment, a capacitor that incorporates a conductive element that conforms to the shape of an array of elongated bodies includes: a first conductive element that conforms to the shape of an array of elongated bodies; a second conductive element that conforms to the shape of an array of elongated bodies; and a dielectric material disposed in between the first conductive element and the second conductive element, and thereby physically separates them.

Abstract: A dielectric material is disclosed comprising a plurality of substantially longitudinally oriented wires which are coupled together, wherein each of the wires includes a conductive core comprising a first material and one or more insulating shell layers comprising a compositionally different second material disposed about the core. In one embodiment, a dielectric layer is disclosed comprising a substrate comprising an insulating material having a plurality of nanoscale pores defined therein having a pore diameter less than about 100 nm, and a conductive material disposed within the nanoscale pores.

Abstract: A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer including adjusting and setting a distance between a single shadow mask installed to a mask set to be rotated and revolved and having a plurality of slits, positioning a dielectric layer deposition source to be perpendicular to the single shadow mask and a conductor layer deposition source to be oblique to the single shadow mask, and forming the dielectric layer and the conductor layer in the vacuum deposition while controlling the mask set to move along the X-, Y-, and Z-axes (the X-axis is the width direction, the Y-axis is the longitudinal direction, and the Z-axis is the height direction).

Abstract: A capacitor forming unit includes a dielectric plate, a first conductor film formed on a plate upper surface region other than front and rear end portions, a first insulator film formed on the upper surface front end portion, a second insulator film formed on the upper surface rear end portion, a second conductor film formed on a plate lower surface region other than front and rear end portion, a third insulator film formed on the front end portion lower surface, and a fourth insulator film formed on the lower surface rear end portion. One or more first electrode rods are disposed in through holes, and electrically connected to the first conductor film and electrically insulated from the second conductor film. One or more second electrode rods are disposed in other through holes, and electrically connected to the second conductor film and electrically insulated from the first conductor film.

Abstract: A multilayered ceramic electronic component includes: a ceramic element having a plurality of dielectric layers laminated therein; first inner electrodes formed on the dielectric layers disposed in upper and lower portions in the ceramic element, the width of a portion of each of the first inner electrodes exposed from one end face of the ceramic element being less than that of a portion thereof disposed within the ceramic element; and second inner electrodes formed on the dielectric layers disposed in the middle portion in the ceramic element, the width of a portion of each of the second inner electrodes exposed from one end face of the ceramic element being equal to that of a portion thereof disposed within the ceramic element.

Abstract: In a method of forming an external electrode by growing plated depositions on exposed ends of a plurality of internal electrodes in a component main body, the component main body is polished to increase exposure of the internal electrodes. To prevent decreased external electrode fixing strength, a radius of curvature is reduced to about 0.01 mm or less for an R chamfered section formed in a ridge section of the component main body during polishing by ion milling, and exposed ends of the internal electrodes are recessed from end surfaces of the component main body with a recess length of about 1 ?m or less. Plating films to serve as external electrodes are formed to extend from the end surfaces of the component main body across the R chamfered section, and include end edges located on at least one of the principal surfaces and the side surfaces.

Abstract: An object of the present invention is to provide a multi-layer ceramic capacitor that includes a laminated block 4 formed by laminating ceramic dielectric layers 2 and internal electrodes 3 alternately, a pair of cover layers 5 laminated on top and bottom of the laminated block, a ceramic body 6 formed on both side surfaces of the laminated block 4, and a pair of external electrodes 7 electrically connected to the internal electrodes 3 and that can effectively prevent an occurrence of a crack. In the multi-layer ceramic capacitor 1, a silicate crystal made of an oxide including Ba and Si or a silicate crystal made of an oxide including Ti and Si is formed in boundary portions between the laminated block 4 and the ceramic bodies 6.

Abstract: A ceramic electronic component includes a first dielectric layer, a second dielectric layer, and an intermediate layer. The first dielectric layer is a layer containing BaO, Nd2O3, and TiO2, the second dielectric layer is a layer containing a different material from the material of the first dielectric layer, and the intermediate layer is a layer formed between the first dielectric layer and the second dielectric layer and containing main components that are not contained in the first dielectric layer and the second dielectric layer in common as the main components.

Abstract: A capacitor includes a capacitor body made of a dielectric, a first internal electrode, a second internal electrode, a first signal terminal, a second signal terminal, and a grounding terminal. The first and second signal terminals are connected to the first internal electrode. The grounding terminal is disposed on the outer surface of the capacitor body so as to be connected to the second internal electrode. The grounding terminal is connected to the ground potential. The grounding terminal includes a plating layer which is disposed on the capacitor body and which is connected to the second internal electrode.

Abstract: Technologies are generally described for a nanocomposite polymer dielectric that may incorporate two types of nanoparticles and a polymer. One of the two types of nanoparticle may be a first, smaller nanoparticle, that may occupy spaces between larger second nanoparticles. Another of the two types of nanoparticle may be the second, larger, “high-?” nanoparticle, which supports the overall dielectric constant of the material. In an applied electric field, the first, smaller nanoparticle may redistribute local charge to homogenize electric fields in the dielectric material, tending to avoid the development of “hot spots”. Such a two-nanoparticle nanocomposite dielectric material may provide increased dielectric breakdown strength and voltage endurance in comparison with a nanoparticle dielectric which only contains a single type of “high-?” nanoparticle.

Abstract: A capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one dielectric layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.

Abstract: In an electronic component, a first capacitor conductor includes a first exposed portion exposed between insulating layers at a surface of a laminate including a first shorter side and two longer sides. A second capacitor conductor includes a second exposed portion exposed between the insulating layers at a surface of the laminate including a second shorter side and the two longer sides. First and second external electrodes are arranged on the laminate so as to cover the first and the second exposed portions, respectively. A first width of the first capacitor conductor in a region located between the second shorter side and a first straight line obtained by connecting two edges of the second external electrode is greater than a width of the first capacitor conductor in a region located between the first straight line and a straight line obtained by connecting two edges of the first external electrode.

Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.

Abstract: The disclosure provides a capacitor structure. A first dielectric layer is disposed over the first electrode layer. A second electrode layer is disposed over the first dielectric layer. At least one of the first electrode layer and the second electrode layer has a peak-valley like structure to create at least two different gap distances therebetween, thereby providing parallel combinations of at least two different capacitances.

Abstract: There is provided a multilayer ceramic electronic component including: a ceramic body including a dielectric layer; and first and second inner electrode layers formed within the ceramic body, wherein, when a thickness of the dielectric layer is defined as td and a maximum thickness and a minimum thickness of the first or second inner electrode layer are defined as tmax and tmin, respectively, td?0.6 ?m and (tmax?tmin)/td<0.30 are satisfied. According to the present invention, a large-capacity multilayer ceramic electronic component capable of improving withstand voltage characteristics and having excellent reliability can be realized by improving uniformity in the thickness of the inner electrode layers.

Abstract: The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition, to form a dielectric layer of hafnium oxide doped with dysprosium and a method of fabricating such a combination produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure can include depositing hafnium oxide onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of dysprosium doping is optimized improves memory function.

Abstract: A biaxially oriented polypropylene film has projections on both surfaces of the film, wherein the height of the most common projection (PhZ) among the projections on each surface is not less than 100 nm and less than 400 nm on both surfaces, and the number of projections per 0.1 mm2 (Pc) on each surface is not less than 150 and less than 500 on both surfaces. The biaxially oriented polypropylene film is easily processed into an element and that, when processed into a capacitor, provides a capacitor having high withstand voltage characteristics and excellent noise characteristics.

Abstract: To provide a thin film capacitor having a device structure for suppressing peeling between an insulating film and a substrate. A thin film capacitor 100 has a laminate structure that is formed by laminating a lower electrode 20, a dielectric film 30, and an upper electrode 40 in sequence on a substrate 10. An adhesion layer 41 is formed on a side surface of the lower electrode 20 via the dielectric film 30, and an insulating film 50 in contact with the adhesion layer 41 covers the laminate structure. According to this device structure, the adhesion layer 41 having excellent adhesiveness to the insulating film 50 is disposed between the insulating film 50 and the dielectric film 30, so that peeling of the insulating film 50 can be suppressed.

Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.

Abstract: The invention provides a compact, electrical energy storage device which has large capacity and can produce a high electrical energy. In accordance with the electrical energy storage device of the invention, the electrical energy storage device 1 comprising a first electrode 4, a dielectric layer 6 and a second electrode 7 is characterized in that between the first electrode 4 and the dielectric layer 6 and between the second electrode 7 and the dielectric layer 6 there is formed an electron collector layer 6 comprising electron collector microparticles 5a made up of metal, semiconductor or surface-modified ceramics.

Abstract: In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out.

Abstract: A circuit substrate includes a resin layer; and an inorganic insulating layer including a groove portion penetrating the inorganic insulating layer in a thickness direction thereof. A part of the resin layer is in the groove portion.

Abstract: Dielectric ceramic composition includes a hexagonal type barium titanate as a main component shown by a generic formula of (Ba1-?M?)A(Ti1-?Mn?)BO3 and having hexagonal structure wherein an effective ionic radius of 12-coordinated “M” is ?20% or more to +20% or less with respect to an effective ionic radius of 12-coordinated Ba2+ and the A, B, ? and ? satisfy relations of 1.000<(A/B)?1.040, 0??<0.003, 0.03???0.2, and as subcomponents, with respect to the main component, certain contents of alkaline earth oxide such as MgO and the like, Mn3O4 and/or Cr2O3, and CuO and Al2O3 and rare earth element oxide and glass component including SiO2. According to the present invention, it can be provided the hexagonal type barium titanate powder and the dielectric ceramic composition which are preferable for producing electronic components such as a capacitor and the like showing comparatively high specific permittivity, having advantageous insulation property and having sufficient reliability.

Abstract: A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; first and second external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of a formation of capacitance within the lower cover layer.

Abstract: There is provided a multilayer ceramic capacitor capable of controlling equivalent series resistance (ESR) characteristics. The multilayer ceramic capacitor includes: a ceramic laminate including dielectric layers and a plurality of internal electrodes having different polarities and alternately stacked between the dielectric layers; and external electrodes formed on both sides of the ceramic laminate, wherein each of the internal electrodes includes a main electrode and a lead for connecting the main electrode to the external electrode, and an equivalent series resistance (ESR) value is determined by adjusting a ratio of a width to a length of the lead, whereby the ESR characteristics of the multilayer ceramic capacitor may be controlled.

Abstract: Electrostatic capacitors with high capacitance density and high-energy storage are implemented over conventional electrolytic capacitor anode substrates using highly conformal contact layers deposited by atomic layer deposition. Capacitor films that are suitable for energy storage, electrical and electronics circuits, and for integration onto PC boards endure long lifetime and high-temperature operation range.

Abstract: High precision capacitors and methods for forming the same utilizing a precise and highly conformal deposition process for depositing an insulating layer on substrates of various roughness and composition. The method generally comprises the steps of depositing a first insulating layer on a metal substrate by atomic layer deposition (ALD); (b) forming a first capacitor electrode on the first insulating layer; and (c) forming a second insulating layer on the first insulating layer and on or adjacent to the first capacitor electrode. Embodiments provide an improved deposition process that produces a highly conformal insulating layer on a wide range of substrates, and thereby, an improved capacitor.

Abstract: The present invention carries out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once, or adjusts slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.

Abstract: A substrate-incorporated capacitor includes a first electrode extending in a predetermined direction, a dielectric layer arranged on part of the first electrode, a second electrode arranged on the dielectric layer and facing the first electrode through the dielectric layer, and an electrode layer arranged on the first electrode surrounding the dielectric layer and connected to the first electrode. Part of the electrode layer is arranged on an end of the dielectric layer and is spaced apart from the second electrode in the predetermined direction, and the part of the electrode layer faces the first electrode through the dielectric layer.

Abstract: A composite dielectric material having a plurality of particle cores, each surrounded by polymer strands that are chemically bonded to the surface of the particle core. Each polymer strand includes a linker, through which the polymer strand is attached to the surface, an interfacial core-shielding (ICS) group bound to the linker, and a polymer molecule bound to the ICS group. The ICS groups are designed to inhibit electrical breakdown of the composite dielectric material by (i) deflecting or scattering free electrons away from the particle cores and/or (ii) capturing free electrons by being transformed into relatively stable radical anions. Representative examples of the particle core material, linker, ICS group, and polymer molecule are titanium dioxide, a phosphonate group, a halogenated aromatic ring, and a polystyrene molecule, respectively.

Abstract: There is provided a multilayer ceramic electronic component, including: a ceramic body including a dielectric layer having an average thickness of 0.6 ?m or less; and first and second inner electrode layers within the ceramic body, disposed to face each other with the dielectric layer interposed therebetween, wherein the dielectric layer includes contact dielectric grains in contact with the first or second inner electrode layer and non-contact dielectric grains not in contact with the first or second inner electrode layer, and, when an average thickness of the dielectric layer is defined as td and an average diameter of the contact dielectric grains is defined as De, De/td?0.35 is satisfied. The multilayer ceramic electronic component has improved continuity of the inner electrode layer, large capacitance, extended accelerated lifespan and excellent reliability.

Abstract: In a ceramic capacitor according to the present invention, the electrode strips of an internal electrode and the dielectric strips of a ceramic dielectric member are arranged perpendicularly to the surface of a substrate, and as such, the plurality of electrode strips and the plurality of dielectric strips are arranged alternately along a parallel direction relative to the substrate surface. That is, the electrode strips and the dielectric strips are multi-layered along a parallel direction relative to the substrate surface, thereby facilitating the realization of multi-layering in the ceramic capacitor by a known patterning technology.

Abstract: A method for forming a Metal-Insulator-Metal Capacitor (MIMCAP) structure and the MIMCAP structure thereof are described. An example electronic device includes a first electrode, and a layer of a dielectric material including titanium oxide and a first dopant ion. The layer of the dielectric material is formed on the first electrode. The first dopant ion has a size mismatch of 10% or lower compared to the Ti4+ ion and the dielectric material has a rutile tetragonal crystalline structure at temperatures below 650° C. The example electronic device further includes a second electrode, formed upon the dielectric material layer.

Abstract: A capacitor (1) for application in high pressure environments has at least two electrodes (2.1, 2.2) and at least one electrically insulating film (5) forming a dielectric between the electrodes (2.1, 2.2), each electrode (2.1, 2.2) having at least one metallic foil (3.1, 3.2) or at least one metallic layer on the electrically insulating film (5), wherein the capacitor (1) is unencapsulated and designed to allow a surrounding liquid to fill cavities of the capacitor (1). Furthermore, an electric device has at least one such capacitor (1) in a device housing, whereby the device housing is filled with an electrically insulating liquid.

Abstract: A power converter utilizes one or more nonlinear composite film capacitors constructed solely of polymer anti-ferroelectric (AFE) particle composites and configured as DC-link bus capacitors providing an energy buffer to reduce DC-link voltage ripple.