Abstract: A reading method for a cell string using multiple pass voltages includes a pre-charging step and a reading step to read a selected word line cell WL[k]. The pre-charging step comprises applying a positive pass voltage (Vpass1) to the selected word line (WL[k]), the upper word lines (Upper WL) of the selected word line (WL[k]), at least one the lower word lines adjacent to the selected word line (WL[k]); and applying a negative pass voltage (Vpass2) to the remaining lower word lines (Lower WL) except for WL[k?1]. The reading step comprises applying sequentially a first voltage which is lower than a read voltage (Vverify) and the read voltage (Vverify) to the selected word line WL[k], applying a second voltage to a common source line CSL and the unselected word lines and sensing a current or a voltage of the selected word line WL[k], thereby reading information stored in the selected word line WL[k].

Abstract: A semiconductor device and a method for forming the same. The semiconductor device includes a tunnel insulating layer, a charge storage layer including a dopant, and a diffusion barrier layer including at least one of carbon, nitrogen, or oxygen interposed between the tunnel insulating layer and the charge storage layer.

Abstract: A three-dimensional NAND device includes a first set of word line contacts in contact with a contact portion of respective odd numbered word lines in a first stepped word line contact region, and a second set of word line contacts in contact with a contact portion of respective even numbered word lines in a second stepped word line contact region. The even numbered word lines in the first word line contact region do not contact a word line contact while the odd numbered word lines in the second word line contact region do not contact a word line contact.

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

Abstract: A package can include a first semiconductor device and a second semiconductor device stacked in a first direction. The first semiconductor device can include a first through via providing a first electrical connection in the first direction between a first side and a second side opposite the first side of the first semiconductor device, and a first circuit that provides a first potential greater than a ground potential at a first circuit output. The first circuit output can be directly connected with wiring layers to the first via at the first side. The second semiconductor device can be electrically connected to the first through via at the second side of the first semiconductor device to receive the first potential.

Abstract: A memory device includes a semiconductor pillar, a first memory cell that includes a first memory film between a first word line and a side surface of the semiconductor pillar, a second memory cell that includes a second memory film between a second word line and the side surface of the semiconductor pillar, and a control circuit configured to carry out first and second operations on the first memory cell and the second memory cell during a reading operation. During the first operation, a read voltage is applied to the first word line and a read pass voltage is applied to the second word line, and during the second operation following the first operation, a first voltage is applied to the second word line, such that a potential of the second word line is lower than a potential of the semiconductor pillar.

Abstract: On an IC chip, a first ground wiring line and a second ground wiring line that extends from a connection site with the first ground wiring line are disposed in a doubled manner. Among EPROMs storing identical data, the source of a first EPROM is connected to the second ground wiring line and the source of a second EPROM is connected to the first ground wiring line. The drains of the EPROMs are electrically connected to a write voltage line. An OR circuit outputs as 1-bit data of the memory circuit, the logical sum of the data stored by at least two of the EPROMs storing identical data. The EPROMs and the OR circuit are disposed near each other on the IC chip.

Abstract: In a non-volatile memory, a method of performing a sensing operation to read a non-volatile (NV) element includes a first and a second phase. During the first phase, the NV element is coupled via a sense path transistor to a first capacitive element at a first input of an amplifier stage and a reference cell is coupled via a reference sense path transistor to a second capacitive element at a second input of the amplifier stage. During the second phase, the NV element is coupled via the sense path transistor to the second capacitive element and the reference cell is coupled via the reference sense path transistor to the first capacitive element. During the first phase, the first and second capacitive elements are initialized to voltages representative of states of the NV element and reference cell, respectively. During the second phase, the voltage differential between the two voltages is amplified.

Abstract: A nonvolatile memory device includes a floating gate formed over a substrate; a contact plug formed on a first side of the floating gate and disposed parallel to the floating gate with a gap defined therebetween; and a spacer formed on a sidewall of the floating gate and filling the gap, wherein the contact plug and the floating gate have a sufficiently large overlapping area to enable the contact plug to operate as a control gate for the floating gate.

Abstract: A voltage switching circuit includes: a control signal generation block configured to include a high voltage switching block which controls an electric current flowing according to a high voltage in response to a voltage level of a low voltage control signal and generates complementary high voltage control signals; and a high voltage transfer block configured to be driven according to the complementary high voltage control signals, and generate a switching signal, the voltage level of which is raised based on the high voltage so that the switching signal has substantially the same level as the high voltage.

Abstract: A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor pillar extending in a first direction in a first region. The semiconductor memory device also includes a first electrode film provided on a side of the semiconductor pillar and extending in a second direction different from the first direction in the first region and in a second region adjacent to the first region in the second direction. The semiconductor memory device also includes a second electrode film provided between the semiconductor pillar and the first electrode film in the first region. Film thickness in the first direction of the first electrode film in the first region is smaller than film thickness in the first direction of the first electrode film in the second region.

Abstract: A memory device including multiple word lines, multiple bit lines and a memory cell array is provided. The word lines intersect the bit lines, and an included angle between the word lines and the bit lines is not a right angle. The memory cell array includes multiple memory cells respectively disposed at the intersections of the word lines and the bit lines. Each row of the memory cells is electrically connected to one of the word lines, and each column of the memory cells is electrically connected to one of the bit lines.

Abstract: A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

Abstract: A package can include a plurality of semiconductor devices stacked in a first direction and commonly sharing at least a first reference potential and a data signal; each semiconductor device including a first through via electrically connected to receive the first reference potential and a second through via electrically connected to receive the data signal, each first through via provides an electrical connection in the first direction between a first side and a second side opposite the first side of one of the plurality of semiconductor devices. A total first through via capacitance value is substantially greater than the total second through via capacitance value.

Abstract: An array structure of a single-poly nonvolatile memory includes a first MTP section and a first OTP section. The first MTP section includes a plurality of MTP cells and the first OTP section includes a plurality of OTP cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, stacks, a blocking layer-trapping layer-tunneling layer structure, channel layers, a first insulating material and a dielectric layer. The stacks are formed on the substrate. Each stack comprises a group of alternating conductive strips and insulating strips as well as a first string select line formed on the group. The blocking layer-trapping layer-tunneling layer structure and the channel layers are formed conformally with the stacks. The first insulating material is formed between the stacks and covers portions of the channel layers. The dielectric layer is formed on portions of the channel layers that are not covered by the first insulating material. The semiconductor structure further comprises second string select lines formed between the stacks on the first insulating material, wherein the second string select lines are separated from the channel layers by the dielectric layer.

Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Abstract: A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.

Abstract: A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.

Abstract: A memory circuit includes a pre-charging unit configured to charge a metal bit line during a pre-charging period, a sensing unit configured to sense a status of a memory cell coupled to the metal bit line during the pre-charging period, and a sink circuit configured to provide a sink current during the pre-charging period based on the status of the memory cell sensed by the sensing unit.

Abstract: A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a nonvolatile memory device.

Abstract: A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.

Abstract: A low power consuming read circuit for a memory array is disclosed. The circuit is particularly useful in applications where oxide breakdown one-time programmable memory is integrated into a system having low power available from the power sources supplying the system.

Abstract: A nonvolatile memory device includes a shared port block, a plurality of decoded address signals, a read signal, and a read word line. The shared port block includes a shared port communicatively coupled to a block, the block comprising a plurality of memory cells, wherein the shared port is operable to sense a voltage level at each of the plurality of memory cells. The plurality of decoded address signals are communicatively coupled to the block. Each of the plurality of decoded address signals is operable to enable a corresponding one of the plurality of memory cells. The read signal is communicatively coupled to the shared port. The read signal is operable to enable a read operation associated with the block. The read word line signal is communicatively coupled to the shared port block. The read word line signal is operable to enable the read operation.

Abstract: A memory device includes a plurality of strings of memory cells. A plurality of stacks of conductive strips includes first upper strips configured as first string select lines for the strings in the plurality of strings, second upper strips configured as second string select lines for the strings in the plurality of strings, and intermediate strips configured as word lines for the strings in the plurality of strings. The memory device includes control circuitry coupled to the first string select lines and the second string select lines, and configured to select a particular string in the plurality of strings by applying a first turn-on voltage to a first string select line in the first string select lines coupled to the particular string, and a second turn-on voltage to a second string select line in the second string select lines coupled to the particular string.

Abstract: A flash memory device is disclosed. The flash memory device includes: a cell array region; an X-decoder region arranged adjacent to the cell array region in a first direction; a discharge transistor region disposed between the cell array region and the X-decoder region; a first metal line formed to pass through the X-decoder region, the discharge transistor region, and the cell array region, and arranged to extend in the first direction; and a second metal line including a first line patterns arranged parallel to the first metal line between the first metal lines, and a second line pattern interconnecting both ends of the first line patterns and extending in a second direction crossing the first direction.

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

Abstract: A package can include a first, second and third semiconductor devices stacked in a first direction. A first semiconductor device can include a first through via between a first side and a second side opposite the first side of the first semiconductor device and a first circuit that provides a first reference potential at a first circuit output, electrically connected to the first through via in a normal mode of operation. A second semiconductor device can include a second through via, a second circuit, and a third circuit. A second circuit can be electrically connected to the first through via at the second side. A third circuit can provide a second reference potential and can be electrically connected to the second through via at the first side. The third circuit and the third semiconductor device can receive the second reference potential exclusive of the first semiconductor device.

Abstract: According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.

Abstract: A memory array (101) includes a plurality of twin cells (104), each of which is composed of a first memory element (102) and a second memory element (103) which are each electrically rewritable and configured to memorize binary data according to a difference in threshold voltages therebetween. A power supply control circuit (105), upon receiving a request for erasing data in a twin cell, increases both the threshold voltage of the first memory element (102) and the threshold voltage of the second memory element (103) during the pre-writing, and after the pre-writing, differentiates the voltage of a first bit line (BL) which is connected to the first memory element (102) and the voltage of a second bit line (/BL) which is connected to the second memory element (103) during the application of erase pulse.

Abstract: Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from the control circuit.

Abstract: The invention provides a non-volatile memory cell structure and non-volatile memory apparatus using the same. The non-volatile memory cell structure includes a substrate, first to three wells and first to three transistors. The first to three wells are disposed in the substrate, and the first to three transistors are respectively forming on the first to three wells. The first to third transistors are coupled in series. Wherein, a control end of the first transistor is floated, a control end of the second transistor receives a bias voltage, and a control end of the third transistor is coupled to a word line signal. Moreover, the third well and the second cell are in same type, and the type of the first well is complementary to a type of the third well.

Abstract: A semiconductor device including a substrate, a bottom insulating layer disposed on the substrate, two stacked structure disposed on the bottom insulating layer, a charge trapping structure, and a channel layer disposed on the charge trapping structure is provided. Each of the stacked structures includes a plurality of semiconductor layers and insulating layers, a top insulating layer disposed on the semiconductor layers and the insulating layers, and a high-doped semiconductor layer disposed on the top insulating layer. The semiconductor layers and the insulating layers are alternately stacked on the bottom insulating layer. The charge trapping layer is disposed on a lateral surface of each of the stacked structures and a top surface of the bottom insulating layer. The channel layer is directly contacted the high-doped semiconductor layer.

Abstract: A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. The controller is configured to cause the memory device to apply a programming pulse to control gates of the group of memory cells. The controller is configured to determine an amount of disturb experienced by the group of memory cells responsive to the programming pulse. The controller is configured to determine a program window responsive to the amount of disturb.

Abstract: A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. A source diffusion layer, which is common to the first and second blocks, is disposed in a semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above at least three conductive layers, is interposed between the first and second blocks.

Abstract: The disclosed invention provides a semiconductor storage device that creates no trouble, independently of power-on sequence. A semiconductor storage device includes a first power supply for the memory cells, a second power supply which is turned on independently of the first power supply and provided for a peripheral circuit which is electrically coupled to the memory cells, and a word line level fixing circuit for fixing the level of the word lines, which operates in accordance with turn-on of the first power supply. The word line level fixing circuit includes multiple level fixing transistors which are provided to correspond respectively to the word lines and provided between one of the word lines and a fixed potential and a level fixing control circuit which controls the level fixing transistors in accordance with input of a signal responding to turn-on of the second power supply.

Abstract: A plurality of semiconductor memory devices on a multi-chip package is disclosed. Each semiconductor device may include a plurality of through vias and a plurality of capacitance enhanced through vias. The through vias may provide an electrical connection for signals that may transition between logic states. The capacitance enhanced through vias may provide an electrical connection from a first side to a second side of the respective semiconductor device for transmission signals that remain substantially stable such as reference voltages, power supply voltages or the like. In this way, noise may be reduced and a reservoir of charge for circuits that provide a load for reference voltages and/or power supply voltages may be provided.

Abstract: The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device.

Abstract: A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.

Abstract: An oscillation module includes a frequency generator, a signal calibrator, a multiplexer, and a controller. The oscillation module is calibrated by using calibration parameters and a control instruction of which the frequency and phase are the same as the oscillation frequency signal generated by the frequency generator. As a consequence, an electronic pin used for processing asynchronous signals can be saved so as to reduce the chip area of the oscillation module.

Abstract: A storage device is provided. The storage device includes a memory controller and at least one nonvolatile memory device including memory blocks having a pipe-shaped bit cost scalable (PBiCS) structure. Each of the memory blocks penetrates word lines stacked on a substrate in the form of plates and includes a first pillar, a second pillar, and a back-gate. The second pillar includes a semiconductor layer, an insulating layer, and a charge storage layer. The back-gate includes a pillar connection portion to connect the first and second pillars to each other and is disposed between the substrate and the word lines. The memory controller includes an adjacent cell management unit configured to control the at least one nonvolatile memory device such that a program operation, an erase operation or a read operation is performed on memory cells adjacent to the back-gate, unlike the other memory cells.

Abstract: A memory device includes a memory array and a logic unit communicatively coupled to the memory array. The memory array includes a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The logic unit is configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.

Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

Abstract: The nonvolatile memory device includes a plurality of memory cells being stacked in a direction perpendicular to a substrate. A string select transistor is connected between the memory cells and a bit line. A string select line is connected to the string select transistor. A one directional device is connected between the substrate and the string select line and configured to transmit a bias voltage from the substrate toward the string select line in an erase operation.