Abstract: A memory array structure is provided. The memory array structure comprises a ring-shaped electrical pattern comprising a plurality of word lines, an array area comprising a first array, a second array and a plurality of bit lines, and a contact area comprising a plurality of contact points. The first array comprises one part of the word lines, and a first ground select line and a first string select line disposed on both sides of the word lines. The second array comprises another part of the word lines, and a second ground select line and a second string select line disposed on both sides of the word lines. The bit lines are disposed on the first array and the second array, and cross both of the first array and the second array. The word lines electrically contact with an external circuit through the contact points.

Abstract: A method is provided for operating a nonvolatile memory comprising memory cells stacked on a substrate. The method comprises counting a number of program loops performed in a first program operation of selected memory cells connected to a selected wordline, and controlling an increment of a program voltage between successive program loops of a second program operation of the selected memory cells according to the counted number.

Abstract: A source of charge carriers in thin film transistor-based memory devices is provided for a memory. The source of charge carriers can include a diode having a first and second terminal. A NAND string coupled on a first end via a first switch to a bit line, is coupled on a second end via a second switch to the first terminal of the diode. Separately drivable first and second supply lines are coupled to the first and second terminals, respectively of the diode. Circuitry is included that is coupled to the first and second supply lines, that is configured to bias the first and second supply lines with different bias conditions depending on the mode of operation, including forward bias conditions and reverse bias conditions.

Abstract: A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.

Abstract: An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment.

Abstract: Disclosed herein are 3D stacked memory devices having WL select gates. The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area of a word line plate. The word line plate may be driven by a word line plate driver and may have many word lines. The WL select gates may select individual word lines or groups of word lines. Therefore, smaller units that the entire block may be selected. This may reduce capacitive loading. The WL select gates may include thin film transistors. 3D decoding may be provided in a 3D stacked memory device using the WL select gates.

Abstract: A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.

Abstract: A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate.

Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.

Abstract: A semiconductor memory device includes memory strings each of which includes a drain select transistor, memory cells, and a source select transistor, a first bit line coupled to drain select transistors of first group memory strings among the memory strings, a second bit line coupled to drain select transistors of second group memory strings among the memory strings, and source lines coupled to source select transistors of the memory strings; and peripheral circuits configured to turn on source select transistors of non-selected memory strings coupled to source lines to which a precharge voltage is supplied or turn on drain select transistors of non-selected memory strings coupled to bit lines to which a program inhibition voltage is supplied in order to precharge channel regions of non-selected memory strings before a program voltage is supplied to a memory cell included in a selected memory string among the memory strings.

Abstract: A novel NVM-based 2T or 2nT NAND-cell for a NAND-array for PLD, PAL and matching functions is disclosed. The preferable NVM cell can be ROM or Flash. The 2T flash cell preferably uses FN for both program and erase operation, while 2T ROM cell preferably to use phosphorus for ROM code implant to get negative Vt0.

Abstract: Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.

Abstract: Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed.

Abstract: Memory hole diameter in a three dimensional memory array may be calculated from characteristics that are observed during programming. Suitable operating parameters may be selected for operating a block based on memory hole diameters. Hot counts of blocks may be adjusted according to memory hole size so that blocks that are expected to fail earlier because of small memory holes are more lightly used than blocks with larger memory holes.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of cell columns each configured by a plurality of memory cells, and a column control circuit that includes a plurality of sense amplifier-data latch units each including a plurality of sense amplifiers that detect and amplify data of the memory cells and a plurality of data latches. One of the plurality of sense amplifier-data latch units is a first sense amplifier-data latch unit and another of the plurality of sense amplifier-data latch units is a second sense amplifier-data latch unit, the first sense amplifier-data latch unit and the second sense amplifier-data latch unit having different numbers of the cell columns capable of being handled.

Abstract: A three-dimensional semiconductor device and a method of fabricating the same, the device including a lower insulating layer on a top surface of a substrate; an electrode structure sequentially stacked on the lower insulating layer, the electrode structure including conductive patterns; a semiconductor pattern penetrating the electrode structure and the lower insulating layer and being connected to the substrate; and a vertical insulating layer interposed between the semiconductor pattern and the electrode structure, the vertical insulating layer crossing the conductive patterns in a vertical direction and being in contact with a top surface of the lower insulating layer.

Abstract: An embodiment of an apparatus includes a substrate, a body semiconductor, a vertical memory access line stack over the body semiconductor, and a body connection to the body semiconductor.

Abstract: Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines being sensed. Data line shielding methods and apparatus disclosed can reduce effects of source line bounce occurring during a sense operation of a memory device.

Abstract: Nonvolatile memory devices including memory cell arrays with first bit line regions and common source tapping regions which are alternately disposed on a substrate along a direction, a page buffer including second bit line regions aligned with the first bit line regions and page buffer tapping regions aligned with the common source tapping regions, and a plurality of bit lines spaced apart from one another and extending to the second bit line regions from the first bit line regions.

Abstract: A semiconductor memory device includes a memory string and a peripheral circuit. The memory string has a pipe cell, a plurality of memory cells, and at least one channel layer having a three-dimensional U-shaped structure. The peripheral circuit is configured to perform an erase operation on the pipe cell. A method of operating the semiconductor memory device includes selecting the memory string and performing the erase operation on the pipe cell.

Abstract: The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply a first control voltage to a control terminal of the first control gate transistor through a first current limiter, and a second control circuit to supply a second control voltage to a control terminal of the second control gate transistor through second current limiter.

Abstract: A semiconductor memory device includes stacked memory strings in which at least some adjacent memory strings share a common source line. During a read operation for a selected memory string, a first current path is formed from a bit line of the selected memory string to the common source line through the selected memory string. A second current path is formed from the bit line of the selected memory string, through the common source line, to a bit line of an adjacent unselected memory string. This reduced path resistance enhances device reliability in read mode.

Abstract: A system including a read module to perform a first read operation to determine a state of a memory cell, and in response to a first failure to decode data read from the memory cell, perform second and third read operations to determine the state of the memory cell. The memory cell has first and second threshold voltages when programmed to first and second states, respectively. A shift detection module detects, in response to a second failure to decode data read from the memory cell in the second and third read operations, a shift in a distribution of at least one of the first and second threshold voltages. A binning module divides the distribution into a plurality of bins. A log-likelihood ratio (LLR) module generates LLRs for the plurality of bins based on a variance of the distribution and adjusts the LLRs based on an amount of the shift.

Abstract: A memory device may include a plurality of cell pairs each including insulator regions interposed between opposing sides of at least one common word line gate and first and second vertical sides formed by a spacing within at least one semiconductor material; and at least one selector gate vertically aligned with the word line gate within the spacing configured to enable first and second source regions in the first and second vertical sides, respectively; wherein when the selector gate is enabled, the first and second source regions are connected to different source diffusion regions.

Abstract: A memory device includes: a plurality of nonvolatile memory sections configured to allow one memory cell to record data of a plurality of bits, and to include a corresponding number of pages to the plurality of bits in accordance with a plurality of the memory cells as a write control unit; and a control section configured to control writing and reading data to and from the plurality of nonvolatile memory sections, wherein among the plurality of nonvolatile memory sections, if data is written into one of the nonvolatile memory sections, the data is written for each page in sequence from a low-order page to a high-order page, and when the data is written into the low-order page, control is performed such that the data to be written into the low-order page is written into any area of the other of the nonvolatile memory sections at same timing.

Abstract: A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first negative voltage generation unit configured to generate a first negative voltage, a boost unit configured to boost a voltage and generate a boosted voltage, and a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, and configured to switch a voltage between the first negative voltage and the boosted voltage, the voltage being applied to the first P-well.

Abstract: Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the cell strings; applying a ground voltage to string selection lines connected with selection transistors of the cell strings; applying a word line erase voltage to word lines connected with memory cells of the cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.

Abstract: A nonvolatile programmable logic switch according to an embodiment includes first and second cells, each of the first and second cells including: a first memory having a first to third terminals, the third terminal being receiving a control signal; a first transistor connected at one of source/drain to the second terminal; and a second transistor connected at a gate to the other of the source/drain of the first transistor, the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common. When conducting writing into the first memory in the first cell, the third terminal is connected to a write power supply generating a write voltage, the first terminals in the first and second cells are connected to a ground power supply and a write inhibit power supply generating a write inhibit voltage respectively.

Abstract: In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.

Abstract: This invention provides a 3D stacked NAND flash memory array and operation method thereof enabling to operate by LSM (a layer selection by multi-level operation) and to get rid of the waste of unnecessary areas by minimizing the number of SSLs needed for a layer selection though the number of layers vertically stacked is increased.

Abstract: A variable resistance memory device includes: first and second structures that each include a first electrode, a second electrode, and a variable resistance material layer interposed between the first and second electrodes and configured to switch between different resistance states depending on a voltage applied across the variable resistance material layer; and a material layer interposed between the first and second structures and configured to pass a bidirectional current according to a voltage applied across the material layer. The first and second structures are symmetrical with respect to the material layer.

Abstract: According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.

Abstract: According to an embodiment, an interface circuit is provided with an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor and a driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor.

Abstract: A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection.

Abstract: Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device. When an erase command is made to erase memory cells, the select gate transistors are read to determine whether their Vth is above an acceptable range. If their Vth is above the acceptable range, the select gate transistors can be erased concurrently with the erasing of the memory cells.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: In one embodiment of the invention, a system is disclosed including a master memory controller and a plurality of memory modules coupled to the master memory controller. Each memory module includes a plurality of read-writeable non-volatile memory devices in a plurality of memory slices to form a two-dimensional array of memory. Each memory slice in each memory module includes a slave memory controller coupled to the master memory controller. When the master memory controller issues a memory module request, it is partitioned into a slice request for each memory slice.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: A device includes a first transistor coupled between first and second nodes, and including a control gate supplied with a first control signal, a second transistor coupled between the first node and a third node, and including a control gate supplied with the first control signal, a third transistor coupled between the third node and a fourth node, and including a control gate supplied with a second control signal, a fourth transistor coupled between the fourth node and a fifth node, and including a control gate supplied with the second control signal, and a fifth transistor coupled between the fifth node and the second nodes, and including a control gate supplied with the first control signal. Each of the second and fifth transistors is smaller in threshold voltage than the first transistor.

Abstract: A non-volatile semiconductor memory device includes first through third memory strings, a first word line group shared by first and second memory strings and a second word line group shared by second and third memory strings, the first and second word line groups extending in a first direction and disposed adjacent to each other in a second direction that is perpendicular to the first direction. The first word line group includes laminated first word lines with each upper first word line extending in the first direction less than the first word line directly below, and the second word line group includes laminated second word lines with each upper second word line extending in the first direction less than the second word line directly below.

Abstract: According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.

Abstract: Embodiments of a circuit and method for setting initial trim bits in an integrated circuit (IC) are described. The circuit includes a memory array including a plurality of trim bit cells to store and provide trim bits to trim registers in a main circuit of the IC following energizing of the IC. The memory array further includes replica bit circuitry to generate a number of replica bits. A logic circuit coupled to the memory array and the main circuit of the IC is configured to receive the replica bits, and to provide a signal to the IC that indicates when the trim bits are valid. In one embodiment, the circuit further includes redundancy check logic configured to receive a number of the trim bits from the memory array, compare the number of trim bits to a pre-determined or computed value, and to provide a BITS_OK signal to the logic circuit.

Abstract: A source line floating circuit includes a plurality of floating units. The floating units directly receive decoded row address signals or voltages of word lines as floating control signals, respectively. The decoded row address signals are activated selectively in response to a row address signal. The floating units control electrical connections between source lines and a source voltage in response to the floating control signals in a read operation. Related devices and methods are also described.

Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The electrical charge of a bit line is discharged, the potential of the bit line is charged via a transistor for writing data, and the potential of the bit line which is changed by the charging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

Abstract: A non-volatile memory system includes a bit line and a plurality of memory cells associated with the bit line and coupled in a serial manner. The system further has a control circuitry in communication with the memory cells, wherein the control circuitry programs a target cell selected from the memory cells by applying a bit line voltage on the bit line in order to promote hot carrier injection into the target cell. The circuit also applies a programming voltage on the target cell under a hot carrier injection mechanism. Moreover, the circuit also applies a control voltage on a control cell, which is adjacent to the target cell when programming the target cell, wherein the control voltage is dependant on the threshold voltage of the control cell and the control voltage is less than the programming voltage.

Abstract: Improved sensing circuits and improved bit line layouts for advanced nanometer flash memory devices are disclosed.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.