Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Abstract: In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions.

Abstract: Methods and carbon ion precursor compositions for implanting carbon ions generally includes vaporizing and ionizing a gas mixture including carbon oxide and methane gases in an ion source to create a plasma and produce carbon ions. The ionized carbon within the plasma is then extracted to form an ion beam. The ion beam is mass analyzed with a mass analyzer magnet to permit the ionized carbon to pass therethrough and implant into a workpiece.

Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon dioxide on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including an oxygen atom.

Abstract: The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage.

Abstract: Some embodiments include methods of forming patterns utilizing copolymer. A copolymer composition is formed across a substrate. The composition includes subunits A and B, and will be self-assembled to form core structures spaced center-to-center by a distance of L0. The core structures are contained within a repeating pattern of polygonal unit cells. Distances from the core structures to various locations of the unit cells are calculated to determine desired distributions of subunit lengths.

Abstract: The effects of random telegraph noise signal (RTS) or equivalently 1/f noise on MOS devices, circuits, and sensors is described. Techniques are disclosed for minimizing this RTS and low frequency noise by minimizing the number of ionized impurity atoms in the wafer, substrate, well, pillar, or fin behind the channel of the MOS transistors. This noise reduction serves to reduce the errors in devices, sensors, and analog integrated circuits and error rates in digital integrated circuits and memories.

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; an insulator layer disposed over the semiconductor substrate; a fin structure disposed over the insulator layer, the fin structure having a source region, a drain region, and a channel region disposed between the source region and the drain region; a gate structure disposed adjacent to the channel region of the fin structure; and a doped region disposed in the semiconductor substrate below the channel region of the fin structure. The gate structure includes a first gate dielectric layer disposed adjacent to the fin structure, a second gate dielectric layer, a charge storing layer disposed between the first gate dielectric layer and the second gate dielectric layer, and a gate electrode layer disposed adjacent to the second gate dielectric layer.

Abstract: A process for fabricating a semiconductor device includes depositing n-type dopant on a p-type substrate, implanting n-type material into the substrate, and growing an n-type epitaxial layer atop the n+ layer. Trenches surrounding the device region are formed and an n+ layer on the sidewalls of the trenches is formed. The trenches are filled by growing a layer of thermal oxide on the sidewalls of the trenches and deposition of plasma enhanced oxide or polysilicon into the trenches, and planarizing the top surface. n+ region of the device is formed by forming an oxide layer on the top surface of the device layer and etching the oxide, depositing n-type dopant material and driving in by high temperature diffusion. p+ region of the device is formed by etching the oxide, depositing p-type dopant material and driving in by high temperature diffusion so that the breakdown voltage is set for circuit protection.

Abstract: When forming sophisticated transistors, the channel region may be provided such that the gradient of the band gap energy of the channel material may result in superior charge carrier velocity. For example, a gradient in concentration of germanium, carbon and the like may be implemented along the channel length direction, thereby obtaining higher transistor performance.

Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.

Abstract: A method is disclosed for manufacturing a semiconductor device. The method includes providing a substrate and forming a well region in the substrate by an ion implantation. The method also includes forming, by rapid thermal oxidation and on the substrate having the well region, an oxide layer for repairing the substrate damaged by the ion implantation. Further, the method includes removing the oxide layer and forming a gate oxide layer on the repaired substrate having the well region.

Abstract: A field effect transistor having a gate structure comprising a high-K dielectric layer, a gate electrode located on the high-K dielectric layer, and an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor. The interfacial layer comprises a layer of SiO2 containing a regrowth inhibiting agent. A method of forming the gate structure includes forming a gate stack comprising, in order: a SiO2 layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO2 layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing a regrowth inhibiting agent into the SiO2 layer and then annealing the gate structure. The presence of the regrowth inhibiting agent in the SiO2 interfacial layer inhibits regrowth of the SiO2 layer into the channel region during the annealing step.

Abstract: A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.

Abstract: A method for forming a polysilicon layer includes forming an amorphous silicon layer over a substrate, performing a first thermal treatment of the amorphous silicon layer by performing an implantation with a gas that includes silicon (Si), and performing a second thermal treatment on the thermally treated layer at a temperature higher than a temperature of the first thermal treatment.

Abstract: According to one embodiment, a semiconductor device includes a substrate and a first transistor. The substrate has a major surface. The first transistor is provided on the major surface. The first transistor includes a first stacked body, first and second conductive sections, a first gate electrode, and a first gate insulating film. The first stacked body includes first semiconductor layers and first insulating layers alternately stacked. The first semiconductor layers have a side surface. The first conductive section is electrically connected to one of the first semiconductor layers. The second conductive section is apart from the first conductive section and electrically connected to the one of the first semiconductor layers. The first gate electrode is provided between the first and second conductive sections and opposed to the side surface. The first gate insulating film is provided between the first gate electrode and the first semiconductor layers.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method of manufacturing a semiconductor device, a first layer containing Si is formed on a semiconductor substrate. An impurity region and a non-impurity region are formed in the first layer by selectively diffusing an impurity into the first layer. A second layer containing a metal material is formed on the first layer. The metal material is diffused into the non-impurity region by annealing the second layer.

Abstract: A first species is implanted into an entire surface of a workpiece and helium is implanted into this entire surface with a non-uniform dose. The first species may be, for example, hydrogen, helium, or nitrogen. The helium has a higher dose at a portion of a periphery of the workpiece. When the workpiece is split, this split is initiated at the periphery with the higher dose. The non-uniform dose may be formed by altering a scan speed of the workpiece or an ion beam current of the helium. In one instance, the non-uniform dose of the helium is larger than a uniform dose of the hydrogen.

Abstract: A method of manufacturing flash memory device is provided and includes the following steps. First, a substrate is provided. Then, a stacked gate structure is formed on the substrate. Subsequently, a first oxide layer is formed on the stacked gate structure. Following that, a nitride spacer is formed on the first oxide layer, wherein a nitrogen atom-introducing treatment is performed after the forming of the first oxide layer and before the forming of the nitride spacer. Accordingly, the nitrogen atom-introducing treatment of the presentation invention can improve the data retention reliability of the flash memory device.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.

Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake at a temperature lower or equal to 800° C., a subsequent deposition step will prevent deposition in the first surface region. This allows selective deposition in the second surface region, which is not doped with the Boron (or doped with another dopant or not doped). Several devices are, thus, provided. The method saves a usual photolithography sequence, which according to prior art is required for selective deposition of Si or SiGe in the second surface region.

Abstract: A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.

Abstract: Methods of fabricating a semiconductor device, and related devices, include forming a gate electrode on a substrate, forming a first buffer layer, a second buffer layer and a third buffer layer on side surfaces of the gate electrode and on the substrate near the gate electrode, forming a spacer covering the side surfaces of the gate electrode on the third buffer layer, the third buffer layer on the substrate being exposed, exposing the second buffer layer on the substrate by removing the exposed third buffer layer, exposing the first buffer layer on the substrate by removing the exposed second buffer layer, forming deep junction in the substrate using the spacer as a mask, and removing the spacer. The third buffer layer is a material layer having a higher dielectric constant than the second buffer layer. The spacer includes a material layer different than the third, second and first buffer layers.

Abstract: The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.

Abstract: A method includes epitaxially growing a germanium (Ge) layer onto a Ge substrate and incorporating a compensating species with a compensating atomic radius into the Ge layer. The method includes implanting an n-type dopant species with a dopant atomic radius into the Ge layer. The method includes selecting the n-type dopant species and the compensating species in such manner that the size of the Ge atomic radius is inbetween the n-type dopant atomic radius and the compensating atomic radius.

Abstract: A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.

Abstract: A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer formed over the substrate having an insulating surface or an insulating layer formed over the planarization layer.

Abstract: A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer, layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and grows as the temperature rises. The luminous flux may be applied in several places of the surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer.

Abstract: Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

Abstract: A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).

Abstract: The present invention belongs to the technical field of semiconductors and specifically relates to a method for manufacturing a vertical-channel tunneling transistor. In the present invention, the surrounding gate gate structure improves the control capacity of the gate and the source of narrow band gap material can enhance the device driving current. The method for manufacturing a vertical-channel tunneling transistor put forward by the present invention capable of controlling the channel length precisely features simple process, easy control and reduction of production cost.

Abstract: A method for making a thin-film structure includes a thin film stabilized on a substrate. The structure of the thin film is defined by a material which includes at least one first chemical species. The method includes a step of inputting particles of the first chemical species into the thin film so as to compensate for the flow of vacancies from the surface of the film.

Abstract: Crack formation and propagation in a silicon substrate may be reduced by forming a crack reducing portion. The silicon substrate includes a silicon main portion and a silicon edge portion formed around the silicon main portion. The crack reducing portion is formed on the silicon edge portion of the silicon substrate such that the directions of crystal faces in the crack reducing portion are randomly oriented.

Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

Abstract: A lateral stack-type super junction power semiconductor device includes a semiconductor substrate; an epitaxial stack structure on the semiconductor substrate, having a first epitaxial layer and a second epitaxial layer; a drain structure embedded in the epitaxial stack structure and extending along a first direction; a plurality of gate structures embedded in the epitaxial stack structure and arranged in a segmental manner along the first direction; a source structure between the plurality of gate structures; and an ion well encompassing the source structure.

Abstract: In a pattern forming method, a pattern having at least either a recess or a protrusion of a curable composition is formed of a curable composition by curing the curable composition into a cured film with a mold having a surface provided with at least either a recess or a protrusion, and separating the mold from the curable composition. The method includes (i) forming a gas generation region containing a gas generator agent so that the gas generation region will be disposed in contact with both the mold and the cured film between the mold and the cured film, (ii) generating a gas from the gas generation region, and (iii) separating the mold from the cured film during or after the step of (ii).

Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor buried layer. The method includes: preparing a substrate which includes a first oxide layer; forming a first buried layer region in the surface of the substrate by using a photoresist layer with a first buried layer region pattern as a mask, in which a doping state of the first buried layer region is different from a doping state of other region of the substrate; forming a second oxide layer on the surface of the substrate and the first buried layer region; and forming a second buried layer region in the surface of the substrate through self alignment process by using the second oxide layer as a mask. The method disclosed by the present disclosure reduces the complexity of the buried layer procedures and the cost thereof, as well as the probability of crystal defects.

Abstract: According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.

Abstract: A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively.

Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise a platen to hold a wafer in a single-wafer process chamber during ion implantation, the platen including: a wafer clamping mechanism to secure the wafer onto the platen and to provide a predetermined thermal contact between the wafer and the platen, and one or more heating elements to pre-heat and maintain the platen in a predetermined temperature range above room temperature. The apparatus may also comprise a post-cooling station to cool down the wafer after ion implantation. The apparatus may further comprise a wafer handling assembly to load the wafer onto the pre-heated platen and to remove the wafer from the platen to the post-cooling station.

Abstract: An ion implanter and an ion implant method are disclosed. Essentially, the wafer is moved along one direction and an aperture mechanism having an aperture is moved along another direction, so that the projected area of an ion beam filtered by the aperture is two-dimensionally scanned over the wafer. Thus, the required hardware and/or operation to move the wafer may be simplified. Further, when a ribbon ion beam is provided, the shape/size of the aperture may be similar to the size/shape of a traditional spot beam, so that a traditional two-dimensional scan may be achieved. Optionally, the ion beam path may be fixed without scanning the ion beam when the ion beam is to be implanted into the wafer, also the area of the aperture may be adjustable during a period of moving the aperture across the ion beam.

Abstract: An electro-static discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first silicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode.

Abstract: A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.

Abstract: A semiconductor device includes a trench MOS barrier Schottky diode having an integrated PN diode and a method is for manufacturing same.

Abstract: The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer.

Abstract: A semiconductor process for removing oxide layers comprises the steps of providing a substrate having an isolation structure and a pad oxide layer, performing a dry cleaning process and a wet cleaning process to remove said pad oxide layer, forming a sacrificial oxide layer on said substrate, and performing an ion implantation process to form doped well regions on both sides of the isolation structure.

Abstract: A method for amorphizing a layer on a substrate is described. In one embodiment, the method includes treating the substrate with a first gas cluster ion beam (GCIB) using a first beam energy selected to yield an amorphous sub-layer within the substrate of a desired thickness, which produces a first interfacial roughness of an amorphous-crystal interface between the amorphous sub-layer and a crystalline sub-layer of the substrate. The method further includes treating the substrate with a second GCIB using a second beam energy, less than the first beam energy, to reduce the first interfacial roughness of the amorphous-crystal interface to a second interfacial roughness.

Abstract: A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers. Cooling channels in the processing chucks are used to create air cushion to assist in aligning the wafers when delivered by the pickup head.