Abstract: An electronic circuit for Euclidean distance determination includes two floating gate transistors (M1, M2) connected in parallel. Voltages representing a reference point and its complement are applied to input lines (22, 24) and corresponding charges become stored on the transistors' floating gates (F1, F2). Voltages representing a data point and its complement are input to control gates (G1, G2). The transistors (M1, M2) produce a combined output current which is a quadratic or exponential function of the distance between the data and reference points according to whether the transistors are above or below threshold. The circuit (10 ) includes a diode-connected load device (M3) for deriving the square root of the output current, which is proportional to Euclidean distance when the transistors are operated above threshold. Refresh means (M44, M45) may be provided for resetting reference points. An array of circuits of the invention is employed for determination of distances between vector quantities.

Abstract: A general purpose charge mode, analog operation circuit provides adder, multiplier, divider (D/A converter) and other functions using a single hardware configuration to be used in different modes. A two-dimensional lattice circuit including electrical charge transfer devices, each driven by charge transfer electrodes, all or a portion of which having structures allowing independent control, and a plurality of the electrical charge transfer devices adjacent to each other in the circuit are controlled successively with respect to the analog circuit charge signals to provide operation functions such as addition, multiplication, division, and sign inversion.

Abstract: A highly accurate vector absolute-value calculation circuit uses analog processing and minimal hardware. Signal voltages corresponding to an I component (real number part) and a Q component (imaginary number part) are input to a first absolute-value calculation circuit 13 and a second absolute-value calculation circuit 14 through terminals 11 and 12, respectively, and they are each converted into absolute-value signals. The component I absolute-value and component Q absolute-value are compared in a comparison circuit 20. According to the result, the larger absolute-value signals are output to an input capacitor 23 of a neural computation circuit, and the smaller absolute-value signals are output to an input capacitor 24 by controlling multiplexers 21 and 22. The capacity ratio of a feedback capacitor 26 of a neural computation circuit and input capacitors 23 and 24 is 11:10:5. The complex number absolute-value calculated by the following formula is output from an output terminal 27.

Abstract: In order to attain a high arithmetic operation precision, small circuit scale, high arithmetic operation speed, and low consumption power in a semiconductor device having multiple input terminals, the terminals, on one side, of capacitance means are connected to the multiple input terminals or one terminal of a capacitance means is commonly connected to a plurality of terminals, the terminals, on the other side, of the capacitance means are commonly connected, and the commonly connected terminal is connected to a sense amplifier via an analog amplifier as needed.