Abstract: Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.

Abstract: A circuit arrangement for handling write and read requests between a master circuit and a slave circuit in different clock domains includes first and second write FIFO circuits, a read FIFO circuit, and a write acknowledgment circuit. The first write FIFO circuit is configured and arranged to receive and buffer write addresses of write requests received from a master circuit and addressed to a slave circuit. The second write FIFO circuit is configured and arranged to receive and buffer write data associated with the write addresses of the write requests. The read FIFO circuit is configured and arranged to receive and buffer read addresses of read requests received from the master circuit and addressed to the slave circuit. The write acknowledgment control circuit is configured and arranged to transmit an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request.

Abstract: Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also determined, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable. The two or more threads are scheduled based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads.

Abstract: A connection section 112 is connected to a client apparatus through a network. A service providing unit provides a service of reception/distribution of a digital broadcast in accordance with a service providing request supplied from the client apparatus. A client information storage section 116 stores therein information associated with the client apparatus connected to the connection section 112. When the service providing request is supplied from a second client apparatus while the service providing unit provides an exclusive service to a first client apparatus, a client information presentation section 110 presents information associated with at least one client apparatus to the other client apparatus. An arbitration section 114 causes at least one of the first client apparatus and the second client apparatus to select whether or not to stop the service for the first client apparatus and to start the provision of the service to the second client apparatus.

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes N machines configured to handle requests from the requesting interconnect and for handling allocated responses from the serving interconnect, wherein each of the N machines has an allocated local count; a tracking entity configured to track priorities of the N machines for issuing received requests to the serving interconnect and for issuing received responses to the requesting interconnect based on the N local counts; a first arbiter configured to arbitrate the received requests to be issued to the serving interconnect based on the tracked priorities; and a second arbiter configured to arbitrate the received responses to be issued to the requesting interconnect based on the tracked priorities.

Abstract: In some embodiments, the present invention provides for an exemplary inventive system that includes at least the following components: an electronic control unit having a service oriented architecture (SOA ECU), where the SOA ECU includes: at least one exemplary inventive SOA server; where the SOA ECU is located within a vehicle; where the at least one SOA server is configured to provide at least one service to at least one client ECU that is located within the vehicle; and where the at least one SOA server is configured to assign at least one dedicated processing resource and at least one dedicated memory resource to provide the at least one service.

Abstract: Provided is a method and system for scheduling computing so as to meet the quality of service (QoS) expected in a system by identifying the operation characteristic of an application in real time and enabling all nodes in the system to dynamically change the schedulers thereof organically between each other. The scheduling method includes: detecting an event of requesting a scheduler change; selecting a scheduler corresponding to the event among schedulers; and changing a scheduler of a node, which schedules use of the control unit, to the selected scheduler, without rebooting the node.

Abstract: A method, computer program product, and computing system for monitoring the availability of multiple redundant data sources within a high-availability data environment. The inaccessibility of at least one of the multiple redundant data sources is detected, thus defining at least one inaccessible data source. Which software applications are impacted by the at least one inaccessible data source is determined, thus defining at least one impacted software application. A notification is provided to one or more parties associated with the at least one impacted software application concerning the inaccessibility of the at least one inaccessible data source.

Abstract: A server capable of supporting and automatically identifying an IP hard disk and a SATA hard disk is operated under SDN. The server includes a machine body device. The machine body device is provided with a baseboard. The baseboard is electrically connected with electronic devices thereon. The electronic devices include an embedded controller IC on a back board; a multiplexer and a plurality of SoC modules on a load board; and a plurality of hard disks including at least one IP hard disk and one SATA hard disk. The embedded controller IC identifies each hard disk as the SATA hard disk or the IP hard disk according to a first potential signal of the telecommunication signal of the second pin of the signal terminals of each hard disk. The present invention meets the market for both IP hard disks and SATA hard disks and brings better economic benefits.

Abstract: A method includes transmitting, by a first processing device, a signal to a second relay processing device. The signal includes a message for the second relay processing device to transmit a read command and/or a write command to an I/O device that is not accessible by the first processing device. The method also includes receiving, by the first processing device, an indication that the second relay processing device has transmitted the read command and/or the write command to the I/O device.

Abstract: A semiconductor device in which unwanted change in the secondary data which must be reliable is suppressed and the need for a considerable increase in the capacity of a memory unit can be avoided. Also it ensures efficient data processing by asymmetric access to the memory unit. It includes a memory unit having a first memory without an error correcting function, a second memory with an error correcting function, and a plurality of access nodes for the memories. A plurality of buses is coupled to the access nodes and a plurality of data processing modules can asymmetrically access the memory unit through the buses. The first memory stores primary data before data processing by the data processing modules, and the second memory stores secondary data after data processing by the data processing modules.

Abstract: An internet protocol (IP) allocation method involves assigning network domains and IP address domains thereof to network elements (NEs) at the periphery of the domains, connecting the other new NEs in the domains to the (EMS) element management system server (EMS) through random addresses and information carried by Link Layer Discovery Protocol (LLDP) packets, enabling the EMS server to automatically configure, manage, allocate and assign the new NEs so as for the NEs to operate at the IP addresses. If NEs are newly introduced into the telecommunication network, the new NEs can get connected to the EMS server easily and successfully by receiving LLDP packets multicast by the NEs at the periphery of the domains and other NEs which are already connected to the EMS server before.

Abstract: Described herein are integrated circuit structures having a package substrate with microstrip architecture as the uppermost layers and a surface conductive layer that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit package substrate may have an internal ground plane, a dielectric layer, a microstrip signal layer as the top transmission line layer, a solder resist layer, and a surface conductive layer that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit package substrate may include altering thicknesses of the dielectric and/or solder resist layers to optimize electrical performance by having the microstrip signal layer closer in proximity to the internal ground layer as compared to the surface conductive layer.

Abstract: Identifying data for placement in a storage system having a plurality of storage classes includes subdividing the data into portions, for each of the portions, independently determining at least one score for a particular portion based on a metric corresponding to access of the particular portion, where the at least one score for the particular portion is independent of scores for other ones of the portions, and identifying sub-portions of data for placement in a particular storage class based on the at least one score of a portion of data corresponding to the sub-portions. The at least one score may be based on short term access statistics and long term access statistics. The access statistics may include read misses, writes, and prefetches.

Abstract: Method and device for acquiring stream of the precisely time-stamped images, including the modulated light source, controlled by the absolute global real-time-base (e.g. provided by global navigation satellite system (GNSS) controller) and the image acquisition and processing unit, decoding the light modulation waveform and determining the time-stamp for every image frame. The GNSS time and position messages can be used to provide the full time- and location stamps for each frame. Multi-element light sources can be used to have more informative light modulation in the time domain. For time-stamping of several image streams (e.g. from several cameras) multiple light sources with the same modulation can be used.

Abstract: A servo actuator default disconnected ID setting method is performed by a servo actuator controlling system, which includes a plurality of servo actuators. A first message is broadcasted which indicates that an original ID is replaced with a non-default-disconnected to the plurality of servo actuators. The original ID of each actuator is replaced with the non-default-disconnected according to the first message. A second message is broadcasted which indicates that the non-default-disconnected ID is replaced with a default disconnected ID. And the non-default-disconnected ID of each servo actuator is replaced with the default disconnected ID according to the second message.

Abstract: To control publication of messages within a social networking server (SRS) from a communication terminal (TC), a server (SC) capable of communicating with the social networking server (SRS) intercepts a message (Mes) containing text data (DonT), the message being provided by a user registered on the social networking server (SRS) and intended to be published by the social networking server (SRS). The server (SC) extracts keywords associated with the text data (DonT) based on a semantic analysis of the text data, and blocks publication of the message (Mes) if at least one extracted keyword is included in a set of keywords (EnsMC) associated with another user registered on the social networking server (SRS), said user being included on a list (LC) initially defined by said other user.

Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.

Abstract: Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion.

Abstract: A data transmission method, a memory storage device and a memory control circuit unit are provided. The method includes: obtaining a first command from a host system and counting a first time value; performing a first access operation corresponding to the first command on the rewritable non-volatile memory module; and generating a first completion message corresponding to completion of the first access operation and buffering the first completion message in a buffer area; and transmitting the first completion message buffered in the buffer area to the host system if the first time value meets a first waiting time value. Accordingly, a data access speed detected by the host system is stabilized.

Abstract: A memory device includes a non-volatile memory (NVM) array and a memory controller. The NVM array has four partitions in which each partition has as plurality of groups of NVM cells. The memory controller that performs a written operation on each of the four partitions in four cycles per group of NVM cells beginning a clock cycle apart in which two of the four clock cycles for the write operation are for an array write that requires a relatively high current and that the array write for each partition overlaps no more than one other array write so that a peak current of all four write operations is no more than twice the peak current of one group. The NVM cells may be magnetic tunnel junctions (MTJs) which have significantly faster written times than typical NVM cells.

Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialize transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behavior at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behavior. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behavior for those write transactions.

Abstract: A memory device may include an input/output control unit for receiving input signals through an input/output bus, and a control logic unit for receiving control signals, and when the control signals satisfy first through fourth conditions, the control logic unit identifies a command, an address, data and an identifier of the memory device in the input signals, and latches the input signals. The fourth condition is different from the first through third conditions.

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Abstract: A system that facilitates direct communication of a transaction between an automation controller and a business system comprises a request analyzer that receives a request for data relating to the automation controller and locates a transaction definition within the automation controller based upon the request. A subscribing component subscribes the business system to the automation controller based at least in part upon the located transaction definition.

Abstract: A method and apparatus for automatically generating/changing Wireless Local Area Network (WLAN) access information are provided. The apparatus includes an access information management database for storing pre-registered WLAN access information of a plurality of WLAN Access Points (APs). The apparatus also includes an access information collector for collecting information for WLAN APs being accessible at a current position of the apparatus, and an access information analyzer for analyzing the collected information, and creating a list of the accessible WLAN APs. The apparatus further includes a comparator for comparing the list with the WLAN access information to determine if the WLAN APs match. The apparatus additionally includes an access information automatic changer for automatically changing current WLAN access information according to matched APs.

Abstract: The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The memory buffer may be employed in various types of systems, such as a computer server system, a network system, or a data center.

Abstract: A method and a system for dynamically controlling at least one electronic device of a plurality of electronic devices in a common operating environment are provided. According to an embodiment, a method for dynamically controlling at least one electronic device comprises storing, in a memory, user input for automatically controlling operation of a first electronic device of a plurality of electronic devices while a second electronic device of the plurality of electronic devices is being operated, detecting, by a processor, a first state transition event affecting an operating state of at least one of the first electronic device or second electronic device and, based on the stored input and detected state transition event, processing instructions for at least one of modifying or suspending operation of at least one feature of the first or second electronic devices.

Abstract: Disclosed are a splitter module and a transmission extender having the same. The splitter module comprises a processing unit, a first USB port, a second USB port and a third USB port. An extender is electrically connected to a plurality of input devices through a hub. The extender transmits a USB signal to the third USB port of the splitter module through a USB port. The processing unit processes the USB signal by splitting it into a HID signal and a high speed signal not from any HID device. After that, the HID signal is transmitted to the KVM switch through the first USB port, and the high speed signal not from any HID device is transmitted to the KVM switch through the second USB port.

Abstract: Communications plugs are provided that include a housing that receives the conductors of the communication cable. A printed circuit board is mounted at least partially within the housing. A plurality of plug contacts are on the printed circuit board, and the printed circuit board includes a plurality of conductive paths that electrically connect respective ones of the conductors to respective ones of the plug contacts. First and second of the conductive paths are arranged as a first differential pair of conductive paths that comprise a portion of a first differential transmission line through the communications plug, where the first differential transmission line includes a first transition region where the impedance of the first differential transmission line changes by at least 20% and a second transition region impedance of the first differential transmission line changes by at least 20%.

Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: A write preference determination unit (30A) compares a reception rate of packets received from the lines of a first network (NW1) with a reception rate threshold for write preference determination, and in a case where the reception rate exceeds the reception rate threshold, determines that preference of a write operation is necessary. A write preference control unit (30B) increases, out of a total access bandwidth of a packet buffer (BUF), a write bandwidth for a packet write operation to the packet buffer (BUF) as compared to a read bandwidth for a packet read operation from the packet buffer (BUF) in a case where the write preference determination unit (30A) determines that the preference is necessary, thereby preferentially executing the packet write operation to the packet buffer. This suppresses occurrence of linked discard of reception packets caused by a shortage of the write bandwidth.

Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

Abstract: A computing device receives one or more questions. The computing device determines at least one of an urgency factor, an importance factor, and a difficulty level associated with the received one or more questions and determines at least one of an availability factor, a skill factor, and a quality level associated with the received one or more questions. The computing device determines an incentive based on the determined at least one of an urgency factor, an importance factor, and a difficulty level associated with the received one or more questions, and the determined at least one of an availability factor, a skill factor, and a quality level associated with the received one or more questions.

Abstract: A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.

Abstract: A method and system for adjusting bandwidth within a portable computing device based on danger signals monitored from one on more elements of the portable computing device are disclosed. A danger level of an unacceptable deadline miss (“UDM”) element of the portable computing device may be determined with a danger level sensor within the UDM element. Next, a quality of service (“QoS”) controller may adjust a magnitude for one or more danger levels received based on the UDM element type that generated the danger level and based on a potential fault condition type associated with the particular danger level. The danger levels received from one UDM element may be mapped to at least one of another UDM element and a non-UDM element. A quality of service policy for each UDM element and non-UDM element may be mapped in accordance with the danger levels.

Abstract: A computing device receives one or more questions. The computing device determines at least one of an urgency factor, an importance factor, and a difficulty level associated with the received one or more questions and determines at least one of an availability factor, a skill factor, and a quality level associated with the received one or more questions. The computing device determines an incentive based on the determined at least one of an urgency factor, an importance factor, and a difficulty level associated with the received one or more questions, and the determined at least one of an availability factor, a skill factor, and a quality level associated with the received one or more questions.

Abstract: In one embodiment a system comprises an integrated circuit, a plurality of voltage regulators; and a data bus coupled to the integrated circuit and the plurality of voltage regulators. In some embodiments the integrated circuit comprises logic to embed a timing signal on the data bus. Other embodiments may be described.

Abstract: A method for programming a wiper system for operating a vehicle windscreen wiper where a wiper module on the driver's side is programmed as a master module and a wiper module on the passenger's side is programmed as a slave module. The wiper modules include a reversing motor, a gear, a holder, and a control. A program sequence, vehicle-specific characteristic data and data for the operation of the wiper module as master or slave module are stored in the control. The wiper module on the driver's side is connected via an on-board wiring system interface and a first data communication line with a vehicle control unit. Provision is made that before the activation of the wiper module on the driver's side via the first data communication line in its control the wiper module is defined or respectively pre-programmed neither as master module nor as slave module.

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes N machines configured to handle requests from the requesting interconnect and for handling allocated responses from the serving interconnect, wherein each of the N machines has an allocated local count; a tracking entity configured to track priorities of the N machines for issuing received requests to the serving interconnect and for issuing received responses to the requesting interconnect based on the N local counts; a first arbiter configured to arbitrate the received requests to be issued to the serving interconnect based on the tracked priorities; and a second arbiter configured to arbitrate the received responses to be issued to the requesting interconnect based on the tracked priorities.

Abstract: Cryptographic communication systems and methods can utilize a base interface and a channel interface. Plug-ins can be utilized to provide cryptographic functions configured for either a first customer or a second customer. The first customer can be a United States domestic customer and the second customer can be an international customer.

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes N machines configured to handle requests from the requesting interconnect and for handling allocated responses from the serving interconnect, wherein each of the N machines has an allocated local count; a tracking entity configured to track priorities of the N machines for issuing received requests to the serving interconnect and for issuing received responses to the requesting interconnect based on the N local counts; a first arbiter configured to arbitrate the received requests to be issued to the serving interconnect based on the tracked priorities; and a second arbiter configured to arbitrate the received responses to be issued to the requesting interconnect based on the tracked priorities.

Abstract: A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, an access controller, a real-time clock, and a basic input/output system. The access controller may be communicatively coupled to the processor and configured to execute a client for retrieving real time via a network communicatively coupled to the access controller. The real-time clock may be communicatively coupled to the access controller. The basic input/output system may be embodied in one or more instructions readable and executable by the processor and configured to, during a power-on/self-test of the basic input/output system, read real time from the access controller and write the real time to the real-time clock.

Abstract: Some embodiments include apparatus and methods having a circuit board, a device located on the circuit board, a first Peripheral Component Interconnect Express (PCIe) connector located on the circuit board and coupled to the device, and a second PCIe connector located on the circuit board and coupled to the device. The first PCIe connector is arranged to couple to a first connector of an additional circuit board. The second PCIe connector is arranged to couple to a second connector of the additional circuit board.

Abstract: One embodiment provides a communication device for transmitting a video to an external device through first to third transmission lines, the communication device including: a transmission module configured to transmit first color difference information and second color difference information concerned with adjacent two pixels through the first transmission line, to transmit first luminance information concerned with one of the two pixels through the second transmission line, and to transmit second luminance information concerned with the other of the two pixels through the third transmission line.

Abstract: A method for authenticating messages is provided. The method includes calculating a hash value based on a key and a message count value and receiving a data message associated with the message count value. The method includes receiving an authentication message that includes the message count value and a message authentication code derived from the data message, the message count value and the key. The method includes applying portions of the data message to look up portions of the hash value and combining the portions of the hash value to form a verification version of the message authentication code. The method includes determining whether the message authentication code matches the verification version of the message authentication code.

Abstract: Systems and methods for providing information services are disclosed. A method includes passing an instance an object, invoked by a user, to a memory device at a hardware layer of a network information system, the object being hosted for a tenant of a network information service. The method further includes determining by a processing unit of the memory device that storage of the object is not authorized by the tenant based on a security map provided by the tenant and accessible by the processing unit within the hardware layer. The method further includes preventing storage of the instance in the memory device based on the result of the determining.

Abstract: An extendable and retractable cellular shade may include a plurality of vertically aligned shade cells and one or more divider webs extending within each shade cells to as to divide the shade cell into two or more cell structures. By adjusting one or more design parameters associated with the cellular shade, the configuration of the shade cells, such as the size and/or shape of the cell structures, and/or the illumination or lighting effects associated with the cellular shade may be specifically tailored to provide a desired aesthetic look or feel for the shade.