Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Abstract: A computing environment, such as an data mirroring or replication storage system, may need to process synchronous I/O requests having different priorities in addition to handling I/O requests on the basis of synchronous or asynchronous groupings. The system described herein provides a data storage system that addresses issues involving efficient balancing of response times for servicing synchronous I/O requests having different priorities. Accordingly, the system described herein provides for maintaining an optimal response time for the host-synchronous I/O requests and the optimal throughput of non-host-synchronous I/O requests using a host-synchronous request time window within which processing of non-host-synchronous I/O requests is throttled. The host-synchronous request time window may be selected to enable the optimal response time for the host-synchronous I/O and also to minimize the impact on the overall throughput of the I/O processor of the storage device.

Abstract: A semiconductor device is provided, which can supply efficiently plural pieces of data required for operation to an arithmetic unit processing plural pieces of data concurrently. The microcomputer includes a data transfer controller and a filter arithmetic unit. The data transfer controller transfers plural pieces of data from a source address area to a destination address area continuously, based on data transfer information, when a start request is received. The filter arithmetic unit performs operation using concurrently plural pieces of data received from the data transfer controller.

Abstract: A method for transmitting data over a single-wire bus wherein a first communication channel is defined by pulses of different durations according to the state of the transmitted bit and depending on a reference duration, and a second communication channel is defined by the reference duration.

Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.

Abstract: The present invention relates to communications systems incorporating peripheral devices such as a push-to-talk (PTT) or similar and interface cables to connect these to a headset and/or a communication device such as a man worn two-way radio, vehicle intercom system, mobile phone, etc. In particular, the invention relates to such interface cable having an integrated functionality. The basic idea of the invention is to use an interface between a first and a second device in a voice communication system, which interface is specific to the second device and holds digital information allowing the first device to identify or adapt to the second device. This allows the first device to automatically adapt its settings and/or functionality to, and thus to function with, several different second devices without any need for updating, re-configuration, or user intervention.

Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

Abstract: A configurable mission processor (CMP) is disclosed that includes a chassis with a plurality of reprogrammable processor modules (RPMs) disposed within the chassis. Each RPM has a baseboard with at least one field programmable gate array (FPGA) and a configuration manager configured to accept a configuration file through an externally accessible signal connector, store the configuration file, and selectably program the at least one FPGA using the configuration file. The RPM includes a power submodule that accepts unregulated power through an externally accessible power connector, generates regulated power at a plurality of voltages, and provide the regulated power to the RPM. The RPM may also include an input/output submodule configured to provide a communication channel between the at least one FPGA and external devices through its own externally accessible signal connector. The CMP also includes a backplane that provides only signal and ground interconnections between the baseboards.

Abstract: Provided are methods and systems for selectively communicating data between a source device and one or more sink devices. The method includes generating a selection signal based on received configuration data associated with the sink device(s). Based at least in part on the selection signal, the data can be caused to be selectively provided to the sink device(s) by the first device. The data includes Universal Serial Bus (USB) protocol data, uncompressed high definition media data, or a combination thereof. In forward connections, the data may be provided variously at one of the following rates: 2.7 Gbps, 5.4 Gbps, 3.375 Gbps, and 6.75 Gbps. At 6.75 Gbps, the data may include a combination of USB data and audio/video data (having high resolution high definition video) or just standalone audio/video data (having higher resolution high definition video). In backward connections, the data includes USB data and can be transferred at either 2.7 Gbps and 3.375 Gbps.

Abstract: For efficiently storing and retrieving data and metadata in phases, in a first phase, metadata tokens, which are assigned to metadata-emitting entities, are used for storing the data and the metadata together in a single input/output operation while piggybacking the metadata of least active metadata-emitting entities onto one of the metadata-emitting entities having one of the metadata tokens. In a second phase, the metadata is re-written to a metadata delta journal for reclaiming the metadata tokens. In a third phase, the metadata journal is applied to a metadata structure containing the metadata of the storage system, the metadata delta journal is then cleared after successfully updating the main metadata structure with the metadata of the metadata journal. The metadata journal is swapped with an empty metadata journal for concurrently adding metadata while retaining the metadata journal until applying the metadata delta journal to the metadata structure.

Abstract: In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.

Abstract: A method, computer program product, and system to implement access control from a master device to a slave device over an inter-integrated circuit (I2C) interface are described. The method includes generating, using a processor, a control block defining the access control to the slave device over the I2C interface. The generating the control block is performed by the trusted code layer and the generating the control block is prohibited by the user-modifiable code layer. The method also includes controlling a command over the I2C interface to the slave device based on a generated command from the trusted code layer and the user-modifiable code layer in accordance with the control block.

Abstract: A hot water supply system includes a plurality of water heaters, one of which is designated as a master, and the rest(s) of which is/are designated as (a) slave(s). A control unit that is provided for each of the water heaters operates a water heater, for which the control unit is provided, as the master or the slave, the master controls the slave(s), and the master and the slave(s) control hot water supply.

Abstract: Systems and methods are disclosed for processing messages using a dynamic messaging bus. An example system includes a plurality of services residing in a dynamic messaging bus including a plurality of sub-buses. Each service is assigned to a sub-bus of the plurality of sub-buses. The example system also includes a performance monitoring module that monitors a performance of one or more services executing on a sub-bus to which the respective one or more services is assigned. A first service is assigned to a first sub-bus and a second service is assigned to a second sub-bus. The example system further includes a swapping module that determines, based on the monitored performances of the first and second services, whether to swap the assignments of the first and second services such that the first service is assigned to the second sub-bus and the second service is assigned to the first sub-bus.

Abstract: A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.

Abstract: Provided are a device and method of controlling a dish cache, wherein a time of seeking a disk cache may be shortened and a hit rate of a disk cache may be increased. The device includes a main memory including a buffer cache, a flash memory including a flash cache, and a controller controlling the buffer cache and the flash cache, wherein the buffer cache and the flash cache are enabled to cache a data block stored in a disk, and the controller identifies a position where the data block is cached using metadata.

Abstract: A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.

Abstract: A wrapping burst read determination unit determines whether or not a read request is a request of a wrapping read. If the read request is the request of the wrapping read, a memory address conversion unit extracts a plurality of addresses that includes an address in which payload data requested by the read request is stored, and designates a read out order of data from the plurality of addresses extracted. If the read request is the request of the wrapping read, a first data holding unit inputs first data read out from an address to which a forefront position in the read out order has been designated among the plurality of addresses, and stores the first data. If the read request is the request of the wrapping read, a data alignment unit, inputs trailing data read out from an address to which an end position in the read out order has been designated, and extracts payload data and an ECC which are correlated with each other from the first data and the trailing data.

Abstract: Microprocessors with multi-core dies that include bypass buses are provided. Each microprocessor comprises a plurality of physical pins for coupling the microprocessor to a processor bus coupled to a chipset. The multi-core die has at least two complementary sets of one or more processing cores, each providing a bus interface coupling respective core inputs and outputs to corresponding processor bus lines. A bypass bus on the die enables cores of the complementary sets to bypass the processor bus and communicate directly with each other. The bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-drive signals from the processor bus. Moreover, the microprocessor is operable to detect whether the chipset or a complementary core is driving the processor bus, and if the latter, to select the higher quality bypass bus signals over the corresponding processor bus signals.

Abstract: A data transmission circuit includes a first data selection unit suitable for alternately outputting data of first and second input lines as first driving data in synchronization with a clock; a data delay unit suitable for generating first and second delay data by delaying the data of the first and second input lines in synchronization with the clock; a second data selection unit suitable for: alternately outputting the data of the first and second input lines as second driving data in synchronization with the clock during a first mode, and alternately outputting inverted first and second delay data, which are inverted from the first and second delay data, as the second driving data in synchronization with the clock during a second mode; a first driving unit suitable for driving an output line in response to the first driving data; and a second driving unit suitable for driving the output line in response to the second driving data.

Abstract: An integrated circuit device includes a cut-through forwarding module. The cut-through forwarding module includes at least one receiver component arranged to receive data to be forwarded, and at least one transmitter component arranged to transmit data stored within at least one transmitter buffer thereof. The cut-through forwarding module further includes at least one delimiter component arranged to trigger a transmission of frame data within the at least one transmitter buffer, upon receipt of a first number elements of a respective data frame by the at least one receiver component, the first number of data elements comprising a first predefined integer value.

Abstract: A method of manufacturing a system on a chip and a system on a chip including a set of pre-designed modules. These modules are place on a semiconductor and connecting by a set of busses formed according to a set of design rules specifying tracks having a minimum size of conductors and a minimum spacing between conductors. The busses are routed in a preferred direction. The busses include minimum size conductors at alternate tracks within a selected metal layer of the semiconductor and minimum size conductors at alternate tracks in a different metal layer. The conductors in the different metal layer are connected to corresponding connectors in the selected metal layer by vias. Shields of conductors not connected to the bus may be included in tracks not including bus conductors.

Abstract: The present disclosure discloses a method for indicating port states and a switch. A main panel of the switch is provided with port indicators one-to-one corresponding to physical ports and N channel indicators. The switch further includes a main chip and a control component. The control component is configured to: receive a port state indication signal from the main chip, and parse the port state indication signal to obtain usage state information of each logical port; generate N enable signals, and control at most one enable signal to be valid at any time point; and control the states of the N channel indicators by using the N enable signals sent from the enable signal controlling module, and control the state of each port indicator according to the N enable signals and the usage state information of each logical port.

Abstract: A data storage device includes a signal source. A load is responsive to the signal source. A method includes adjusting an impedance of the load to reduce an impedance mismatch between the signal source and the load.

Abstract: A system-on-chip integrated circuitry includes interconnect circuitry for connecting transaction sources with transaction destinations. A buffer circuit buffers a plurality of access transactions received from the transaction sources before they are passed on to respective transaction destinations. Hazard checking circuitry, such as identifier reuse circuitry, performs hazard checks for access transactions in parallel with snoop operations performed by snoop circuitry for managing coherence between data values stored within the plurality of cache memories. The snoop circuitry includes snoop reordering circuitry for permitting reordering of snoop responses. The snoop circuitry may issue a snoop request for a given access transaction in parallel with the hazard checking circuitry performing one or more hazard checks for that transaction.

Abstract: A system for power control includes a power supply having a power supply line and a standby power line, a logic circuit having a first output terminal connected to the power supply and three input terminals, a processing device connected to the standby power line and the power supply line, and a power switch. The processing device includes at least one processor, a storage storing a code executable by the processor, and four input/output (I/O) interfaces. A first, second and third I/O interfaces of the processing device are electrically connected to a first, second and third input terminals of the logic circuit, and a fourth I/O interface is connected to the third I/O interface. The power switch electrically connects or disconnects the standby power line to the first I/O interface and the first input terminal. The processing device has a power on state, a power off state, and a suspend state.

Abstract: The invention relates to a reconfiguration process for an aircraft environment surveillance device including at least two redundant electronic systems (2, 2?), where each system includes at least two surveillance sets (4-10, 4?-10?) able to provide information about the aircraft's environment. The inventive method and apparatus includes the following steps and structures: detection of simultaneous unavailability (S1, S4) of at least one surveillance set of the first system (4-10) and of at least one surveillance set of a second system (4?-10?); and, in the case where at least two unavailable sets (4-10, 4?-10?) are not redundant sets, automatic selection (S3, S6) of the information obtained, on the one hand, from the available surveillance sets of the first system (4-10), and, on the other hand, from the redundant surveillance set or sets of the second system (4?-10?) that matches the unavailable surveillance set or sets of the first system (4-10).

Abstract: A linecard includes at least one pluggable device, a linecard processor, and a centralized host processor. The linecard also includes an interface that supports a pluggable device. A pluggable device is electrically coupled to the interface and is controlled by the centralized host processor. A flash memory stores data for the pluggable device. The pluggable device can include at least one of an optical amplifier and a ROADM pluggable device.

Abstract: An electronic device can communicate with an external device according to a predetermined method. The electronic device includes a power switch operable to receive an operation for switching on and off the electronic device, a detector operable to detect a connection between the electronic device and the external device according to the predetermined method, and a requestor operable to request the external device to supply power. When the detector detects the connection between the electronic device and the external device with the power switch being ON, the requestor does not request the external device to supply the power in an establishing process for establishing the communication with the external device. When the detector detects the connection between the electronic device and the external device and the power switch is switched from ON into OFF, the requestor requests the external device to supply the power in the establishing process.

Abstract: A method and corresponding apparatus of managing transport operations between a first memory cluster and one or more other memory clusters, include receiving, in the first cluster, information related to one or more transport operations with related data buffered in an interface device, the interface device coupling the first cluster to the one or more other clusters, selecting at least one transport operation, from the one or more transport operations, based at least in part on the received information, and executing the selected at least one transport operation.

Abstract: A USB SSIC thin card device and a data transfer method thereof are provided. A first universal serial bus (USB) physical layer circuit is controlled by a USB device control unit to transmit data through a pair of first differential signal pins and a pair of a second differential signal pins, wherein the first USB physical layer circuit is used to transmit data complied with a USB 3.0 SSIC transmission specification.

Abstract: The present invention relates to a computing system which includes a processor and a memory. It also includes a memory access optimizer which is arranged to affect memory access of a program during runtime execution of the software. The program includes a plurality of application elements, each comprising a text field containing a text section, and a memory access field. The memory access optimizer is arranged to implement memory access data in the memory access field in order to affect memory access of the application element. The text section is unchanged by the memory access data implementation.

Abstract: A computer implemented method, system and product for transferring information between systems of record connected to a bus comprising generating an event in response a change in a system of record of the systems of record; transforming the change event into a generic event at an adapter for the system of record, wherein the adapter is communicatively coupled to the system of record and the bus; conveying the generic event to the bus from the adapter; reasoning on the generic event to determine if at least some information of the generic event should be propagated to another system of record; based on a positive determination, using a policy based system of record information filter to determine what information of the event to send to the another system of record, and propagating at least some of the information of the generic event in a new event to another adapter communicatively coupled to the another system of record; and translating the new event, at the adapter, to an event able to be understood by the

Abstract: The bandwidth allocation apparatus includes a high bandwidth arbitration module, a low bandwidth arbitration module and a multiplexer. The high bandwidth arbitration module is used to select one downstream device from the high bandwidth downstream device group for allowing uplink. The low bandwidth arbitration module is used to select one downstream device from the low bandwidth downstream device group for allowing uplink. The multiplexer selects the one of the access requests from the high bandwidth arbitration module or the low bandwidth arbitration module for allowing to uplink the access request to an upstream device. The access transmission times of the high bandwidth arbitration module and the low bandwidth arbitration module are counted respectively by a counting circuit.

Abstract: A computing environment, such as an data mirroring or replication storage system, may need to process synchronous I/O requests having different priorities in addition to handling I/O requests on the basis of synchronous or asynchronous groupings. The system described herein provides a data storage system that addresses issues involving efficient balancing of response times for servicing synchronous I/O requests having different priorities. Accordingly, the system described herein provides for maintaining an optimal response time for the host-synchronous I/O requests and the optimal throughput of non-host-synchronous I/O requests using a host-synchronous request time window within which processing of non-host-synchronous I/O requests is throttled. The host-synchronous request time window may be selected to enable the optimal response time for the host-synchronous I/O and also to minimize the impact on the overall throughput of the I/O processor of the storage device.

Abstract: In one embodiment, a communication circuit is configured for automated addressing in a network of series connected communication circuits. The communication circuit includes a voltage source and a switch connected in parallel between first and second data ports of the circuit. While operating in an addressing mode, a first voltage is sampled from a first data port while the switch is closed. The switch is opened to provide a voltage potential between the first and second data port and a second voltage is sampled from the second data port. An address of the communication circuit in the network is determined based on a difference of the first and second voltages.

Abstract: The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The memory buffer may be employed in various types of systems, such as a computer server system, a network system, or a data center.

Abstract: Managing data in a storage system having a plurality of classes of storage includes determining an amount of data to be provided on at least one of the classes of storage according to a policy, dynamically setting a threshold according to the amount of data to be provided on the at least one of the classes or an expected performance based on the threshold, and placing data on particular classes of storage based on the threshold. Dynamically setting a threshold may include sorting data portions according to at least one score thereof and may include determining a particular score corresponding to the amount of data to be provided. The data portions may be provided in a histogram having a horizontal scale corresponding to a score value and a vertical scale corresponding to a number of data portions having a particular value.

Abstract: A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.

Abstract: A docking station can be coupled to a tablet computing device. A tablet computing device can include a home key that is disabled when the tablet is connected to the docking station. The docking station can include a release to separate the tablet computing device from the docking station.

Abstract: A method and apparatus are provided for monitoring the thermal state of a data center. According to the method and apparatus, thermal sensors are placed at various locations in a data center and readings from those sensors are collected. Once collected, the readings are used in controlling the operation of the data center.

Abstract: Techniques and solutions are described for multi-threaded processing of data, which may include dividing incoming data content stream into a plurality of fragments, for processing by a corresponding plurality of parallel parser threads running within one or more computing devices. A fragment order is assigned to the plurality of fragments. During a first processing phase of the parser threads, for each of one or more selected fragments of the plurality of fragments, a first available delimiter is determined within data content of the selected fragment. The data content within the selected fragment is parsed, starting from the first available delimiter to a last available delimiter within the fragment. During a second processing phase, for each of the one or more selected fragments, data content in a fragment suffix for the selected fragment is parsed with data content from a fragment prefix from a subsequent fragment.

Abstract: A method and apparatus for determining whether to enable a functionality of a battery powered device upon connection to a battery is embodied by providing at least one voltage threshold in a memory of the battery that corresponds to a usable operating range limit of the battery and that is accessible by the battery powered device. Upon connection to the battery, the battery powered device acquires the voltage threshold or thresholds from the battery and programs itself with the threshold or thresholds. The battery powered device then compares a voltage of the battery to the threshold or threshold to determine whether the enable the functionality.

Abstract: Systems and methods are provided for updating configuration settings, updating an OS image, and booting an alternate OS on a portable data reader including a reading engine for reading data from an object. Configuration settings of a portable data reader may be updated by detecting whether a storage device having a set of updated configuration settings stored thereon has been coupled to the portable data reader and, if so, updating one or more configuration settings on the portable data reader with one or more of the updated configuration settings from the storage device.

Abstract: A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.

Abstract: A portable electronic device and an accessory device thereof, and an operating method for a portable electronic device. According to the disclosure, an accessory device coupled at a universal serial bus connector of a portable electronic device is detected and identified via the identification pin of the universal serial bus connector. When it is identified that the accessory device supports 1-wire communication via the identification pin, the accessory device is accessed via the 1-wire communication via the identification pin.

Abstract: A computing device identifies a data packet received at a computing device. The computing device allocates memory having a fixed size to store the network data packet. A latency reducer identifies a free space in the memory allocation, the free space comprising a difference between the fixed size of the memory allocation and a size of the network data packet. The latency reducer creates a socket buffer list for the network data packet in the free space, the socket buffer list comprising a plurality of entries to serve as socket queue objects for a plurality of applications.

Abstract: A memory system is disclosed. The memory system includes first and second memory devices, and a memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first and second memory devices. The first memory device is configured to provide a notification to the memory controller on the first line and the second memory device is configured to provide a notification to the memory controller on the second line. The first memory device is further configured not to load the first line and the second memory device is further configured not to load the second line when the memory controller is writing to the enabled memory device.

Abstract: A parallel computing system includes: each computing node including: a first channel receiving data which a preceding node transfers, and transferring received data to a subsequent node; a second channel receiving data which a preceding node transfers, and transferring received data to a subsequent node; and a computational processor receiving data which the first or second channel has received, and transferring processed data to a subsequent node; an input-output node including: a third channel receiving data which the first channel or the computational processor of a preceding node transfers; a fourth channel receiving data which the first channel or the computational processor of a preceding computing node transfers, and transferring the received data to the second channel of a subsequent computing node; and an input-output processor receiving data which the third channel has received, and transferring inputted and outputted data to the first channel of a subsequent computing node.

Abstract: The present invention provides a display control method and system, and a display device. The method includes acquiring a status value of a display buffer; comparing the status value of the display buffer with a preset warning value of the display buffer; and adjusting a value of a depth of outstanding bus commands according to a comparison result. In the embodiments of the present invention, a status value of the display buffer is compared with a preset warning value of the display buffer, where the status value of the display buffer reflects a change to a current load; it may be determined whether a status value of the display buffer corresponding to the current load is normal according to a comparison result; and a value of a depth of outstanding bus commands is adjusted accordingly, effectively resolve a data real-timeness issue, and ensure that an entire system efficiently runs.