Input/output Access Regulation Patents (Class 710/36)
  • Patent number: 8706948
    Abstract: A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: April 22, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Hua Chu, Hong-Lipp Ko
  • Patent number: 8700819
    Abstract: A communication link between a host device and a client device can be suspended based on a suspend request or notification provided by the client device. The suspend request can be transmitted by a client device to a host device if the client device determines that suspension is appropriate, and can be sent in response to receiving a polling request from the host device. After receiving a suspend request, the host device can initiate an operation to suspend the communication link between the devices.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: April 15, 2014
    Assignee: Apple Inc.
    Inventors: Anand Dalal, Haining Zhang, Mitchell D. Adler
  • Patent number: 8700810
    Abstract: A semiconductor device includes at least one endpoint communicating with a host, and an endpoint controller dividing each of the at least one endpoint into a majority of sub-endpoints and performing numbering to each of the divided sub-endpoints. The endpoint controller transmits a packet generated by the host to any one of the sub-endpoints.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Geun Park, Chul Joon Choi, Keon Han Sohn
  • Patent number: 8700821
    Abstract: A device, method, and system are disclosed. In one embodiment the device includes a router to transmit data packets between multiple host controllers and one or more peripheral devices. The router can receive a data packet from a host controller and transmit the data packet to a peripheral device across a data transmission path. The peripheral device is coupled to the first data transmission path through a first universal multi-transport medium (UMTM) connector. The connector includes an optical coupling capable of transporting the first data packet within an optical signal and an electrical coupling capable of transporting the first data packet within an electrical signal.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 15, 2014
    Assignee: Intel Corporation
    Inventors: Prashant R. Chandra, Ajay V. Bhatt, Kevin Kahn, Steve McGowan
  • Patent number: 8700811
    Abstract: Disclosed are methods for exposing multiple interfaces of a communications fabric (Ethernet, FiberChannel, Serial-Attached-SCSI, Infiniband, etc.) of a virtual machine and automatically mapping those interfaces onto separate physical interfaces. Such an approach may preserve the simple management experience of a single connection point into the virtual machine while allowing the OS and application within the virtual machine to supply information necessary to efficiently use the multiply underlying physical links.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: April 15, 2014
    Assignee: Microsoft Corporation
    Inventors: Jacob Oshins, Tejas Karandakar
  • Patent number: 8701114
    Abstract: An apparatus for dynamically redirecting a file descriptor includes an identification module, a disassociation module, and an association module. The identification module identifies a first executing process using a second executing process. The first executing process may include a file descriptor and the first executing process may be independent of the second executing process. The disassociation module disassociates the file descriptor from a first data stream using the second executing process without involvement of the first executing process. The association module associates the file descriptor with a second data stream using the second executing process without involvement of the first executing process in response to the disassociation module disassociating the file descriptor from the first data stream.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: April 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sukadev Bhattiprolu, Matthew Lee Helsley
  • Patent number: 8700820
    Abstract: A method for accessing a Universal Serial Bus (USB) device attached to the home gateway is provided to solve the problem that after the USB device is attached to the home gateway, the USB device becomes an exclusive device of the home gateway, and application software on a personal computer (PC) or other terminals can not be directly used to transparently access the USB device. The method includes: receiving a USB message of the USB device attached to the home gateway; and adapting the USB message to a network packet and sending the network packet to a virtual USB device interface of a terminal to be read by an application program of the terminal; or parsing a network packet sent by the terminal through the virtual USB device interface into a USB data frame and writing the USB data frame into the USB device.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: April 15, 2014
    Assignee: Huawei Device Co., Ltd.
    Inventor: Bichao Chen
  • Patent number: 8688870
    Abstract: According to one embodiment, a communication device includes a first interface, a wireless communication unit, and a memory unit. The memory unit includes a first region used for first access from the first interface and a second region used for second access from the wireless communication unit. Writing to the second region by the first access and writing to the first region by the second access are inhibited.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Youichirou Shiba
  • Patent number: 8683103
    Abstract: Exemplary system and computer program embodiments for hierarchy multi-tenancy support for configuration of a plurality of host attachment through a plurality of resource groups in a computing storage environment are provided. In one embodiment, multiple data storage subsystems are configured with multiple operators for configuration and management of multiple host attachments to multiple logical volumes. A logical operator is designated with the responsibility of designating authority to a host attachment operator and the ability to configure multiple logical volumes. Limited authority is provided for the host attachment operator to configure multiple volume groups and multiple host ports to a specific user.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventor: Richard A. Ripberger
  • Patent number: 8683104
    Abstract: Exemplary method embodiments for hierarchy multi-tenancy support for configuration of a plurality of host attachment through a plurality of resource groups in a computing storage environment are provided. In one embodiment, multiple data storage subsystems are configured with multiple operators for configuration and management of multiple host attachments to multiple logical volumes. A logical operator is designated with the responsibility of designating authority to a host attachment operator and the ability to configure multiple logical volumes. Limited authority is provided for the host attachment operator to configure multiple volume groups and multiple host ports to a specific user.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventor: Richard A. Ripberger
  • Patent number: 8683094
    Abstract: A method for enhancing data transmission efficiency in a data transmission system having a host, a subsystem and a transmission interface, utilized for the host to transmit and receive a data from a memory of the subsystem via the transmission interface includes steps of the host outputting a query command to the subsystem via the transmission interface for querying available memory utilization of the subsystem; the subsystem outputting a return message to the host via the transmission interface for indicating the available memory utilization according to the query command; and controlling data transmission from the host to the subsystem according to the return message.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: March 25, 2014
    Assignee: Ralink Technology, Corp.
    Inventors: Ching-Hwa Yu, Chen-Hai Yu
  • Patent number: 8683089
    Abstract: One or more client engines issues write transactions to system memory or peer parallel processor (PP) memory across a peripheral component interconnect express (PCIe) interface. The client engines may issue write transactions faster than the PCIe interface can transport those transactions, causing write transactions to accumulate within the PCIe interface. To prevent the accumulation of write transactions within the PCIe interface, an arbiter throttles write transactions received from the client engines based on the number of write transactions currently being transported across the PCIe interface.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: March 25, 2014
    Assignee: Nvidia Corporation
    Inventors: Raymond Hoi Man Wong, Samuel H. Duncan, Lukito Muliadi
  • Patent number: 8683105
    Abstract: The modular avionics system may include one or more centralized processing line-replaceable units (LRUs), the centralized processing LRUs including at least one multi-core computer processor, one or more multi-function display (MFD) units configured to receive imagery data from the centralized processing LRUs and display the imagery data on a display device, one or more control display units (CDUs) configured to receive imagery data from the centralized processing LRUs and display the imagery data on a display device, the MFD units and the CDUs including one or more user input devices, the MFD units and the CDUs including at least one logic module, the CDUs and the MFD units configured to transmit user input data from the user input devices to the centralized processing LRUs, the centralized processing LRUs constructed from a plurality of component slices, wherein a first component slice and at least a second component slice are reversibly couplable.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: March 25, 2014
    Assignee: Rockwell Collins, Inc.
    Inventors: Roger K. Shultz, Raymond E. Knoff, Joshua R. Bertram
  • Publication number: 20140082231
    Abstract: For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks, is initiated for waking a predetermined number of the waiting I/O operations. A total number of I/O operations to be awoken at each of an iterated instance of the waking is limited.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin John ASH, Michael Thomas BENHASE, Lokesh Mohan GUPTA, David Blair WHITWORTH
  • Patent number: 8677034
    Abstract: An I/O control system for controlling I/O devices in a multi-partition computer system. The I/O control system includes an IOP partition containing an I/O processor cell with at least one CPU executing a control program, and a plurality of standard partitions, each including a cell comprising at least one CPU executing a control program, coupled, via shared memory, to the I/O processor cell. One or more of the standard partitions becomes an enrolled partition, in communication with the I/O processor cell, in response to requesting a connection to the IOP cell. After a partition is enrolled with the I/O processor cell, I/O requests directed to the I/O devices from the enrolled partition are distributed over shared I/O resources controlled by the I/O processor cell.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: March 18, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Blaine Douglas Gaither
  • Patent number: 8676974
    Abstract: Embodiment of the present invention include a method, system and computer program product for a data processing system for QoS based planning in a Web services aggregation. The system can include Web service aggregation and coordination logic configured to identify accessible Web services in a registry and to arrange an aggregation of the Web services for invocation responsive to requests received from communicatively coupled clients over a computer communications network. The system further can include QoS planning logic coupled to the Web service aggregation and coordination logic. The QoS planning logic can be enabled to measure both the individual performance of the Web services in an aggregation of Web services and also the cumulative performance of the aggregation of Web services.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ronald P. Doyle, David L. Kaminsky
  • Patent number: 8675679
    Abstract: A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 18, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Gerard Hofmann, Terence J. Lohman
  • Publication number: 20140075057
    Abstract: A multi-modem device is disclosed. The multi-modem device includes a housing. Included within the housing is a plurality of modems, wherein the modems send and receive data along a common data bus. The multi-modem device further includes an interface that provides a connection that enables the modems to communicate with a computer, wherein each of the modems is made available to the computer so that the modems may be selected either individually or in parallel to provide one or more communication links to the computer.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 13, 2014
    Applicant: HOBNOB, INC.
    Inventors: Hisham Atef Sakr, Jared Go, Aron B. Hall
  • Patent number: 8671249
    Abstract: An apparatus, system, and method are disclosed for managing storage capacity recovery. A monitor module determines a workload write bandwidth for a sequential log-based data storage device. The workload write bandwidth includes a rate at which workload write operations generate reclaimable storage capacity on the data storage device. A target module determines a target reclamation write bandwidth for the data storage device. A capacity reclaim rate is associated with the target reclamation write bandwidth. The capacity reclaim rate satisfies the workload write bandwidth for the data storage device. A reclaim rate module determines a prospective reclamation write bandwidth for the data storage device, based on the workload write bandwidth, to correspond to the capacity reclaim rate associated with the target reclamation write bandwidth.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: March 11, 2014
    Assignee: Fusion-io, Inc.
    Inventors: Nisha Talagala, James Peterson
  • Patent number: 8671229
    Abstract: A method, computer program product, and computing system for receiving an IO request from a host concerning an IO operation to be performed on a data array. The IO request is processed to generate an IO descriptor. The IO descriptor defines a unique and proprietary memory space for each of a plurality of IO processing routines.
    Type: Grant
    Filed: June 30, 2012
    Date of Patent: March 11, 2014
    Assignee: EMC Corporation
    Inventors: Alan L. Taylor, Miles A. de Forest, Michael D. Haynes
  • Patent number: 8671138
    Abstract: A network interface adapter includes a network interface and a client interface, for coupling to a client device so as to receive from the client device work requests to send messages over the network using a plurality of transport service instances. Message processing circuitry, coupled between the network interface and the client interface, includes an execution unit, which generates the messages in response to the work requests and passes the messages to the network interface to be sent over the network. A memory stores records of the messages that have been generated by the execution unit in respective lists according to the transport service instances with which the messages are associated. A completion unit receives the records from the memory and, responsive thereto, reports to the client device upon completion of the messages.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 11, 2014
    Assignee: Mellanox Technologies Ltd.
    Inventors: Michael Kagan, Diego Crupnicoff, Gilad Shainer, Ariel Shahar
  • Publication number: 20140068317
    Abstract: The present subject matter discloses methods and systems of sharing of peripheral devices in multi host computing systems (100). In one implementation, the method of sharing a peripheral device (116) amongst a plurality of hosts of the multi-host computing system (100) comprises receiving a request to switch the peripheral device (116) from a first operating system running on a first host from amongst the plurality of hosts to a second operating system running on a second host from amongst the plurality of hosts; generating a request for the first operating system to relinquish control of the peripheral device (116); determining the status of the relinquishment based on response generated by the first operating system; initiating a request for the second operating system to install a device driver for the peripheral device (116) upon determining successful relinquishment; and transferring ownership of the peripheral device (116) to the second operating system.
    Type: Application
    Filed: April 30, 2012
    Publication date: March 6, 2014
    Applicant: INEDA SYSTEMS PVT. LTD
    Inventors: Balaji Kanigicherla, Krishna Mohan Tandaboina, Siva Raghuram Voleti, Chandra Kumar Chettiar, Surya Narayana Dommeti, Kishor Arumilli, Dhanumjai Pasumarthy, Rajani Lotti
  • Publication number: 20140059256
    Abstract: The invention may be embodied in a SAS expander with register bits within Phys associated with I/O devices. Setting and unsetting the register bit in the Phy associated with a particular physical or logical device allows I/O traffic to be blocked and unblocked, as desired, to the selected physical or logical devices. In a particular embodiment, when the register bit is set to a blocking state, an OPEN request that comes in on the SAS link is rejected using OPEN_REJECT (RETRY). Phy register bits may be provided for multiple different SAS protocols that can be controlled individually for each attached SAS device. The Phy register bit may also be used to reject only SAS connection requests that attempt to leave a particular SAS link.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: LSI CORPORATION
    Inventors: Brett J. Henning, Harold L. Johnson, William K. Petty
  • Patent number: 8661175
    Abstract: Disclosed is a method of synchronizing a plurality of processors accesses to at least one shared resource. One of a plurality of processors requests an exclusive region lock for a shared resource using a logical block address (LBA) of a dummy target. The LBA is defined in a region map that associates LBAs to shared resources. The exclusive region lock request is inserted as a node in a region lock tree of the dummy target. Access to the shared resource is granted based on a determination whether there is an existing region lock in the region lock tree that is overlaps with the new exclusive region lock request.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: February 25, 2014
    Assignee: LSI Corporation
    Inventors: Kapil Sundrani, Lakshmi Kanth Reddy Kakanuru
  • Patent number: 8656070
    Abstract: The present disclosure is directed to a method for communication between an initiator system and a block storage cluster. The method may comprise initiating an input/output (I/O) request from the initiator system to a first storage system included in a plurality of storage systems of the block storage cluster, each of the plurality of storage systems comprising a plurality of data segments; receiving a referral response from the first storage system, the referral response providing information describing a layout of data requested in the I/O request; obtaining a virtual disk count, a segment size, and at least one indexed port identifier based on the referral response; and directing the I/O request from the initiator system to the block storage cluster based on the virtual disk count, the segment size, and the at least one indexed port identifier.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: February 18, 2014
    Assignee: LSI Corporation
    Inventors: Ross E. Zwisler, Andrew J. Spry, Gerald J. Fredin, Kenneth J. Gibson
  • Patent number: 8656068
    Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: February 18, 2014
    Assignee: CommVault Systems, Inc.
    Inventors: Rajiv Kottomtharayil, Manoj Kumar Vijayan
  • Patent number: 8656067
    Abstract: In one implementation, a pairing device provides an identify instruction to a peripheral device during a pairing process. The peripheral device generates an identification output in response to the identify instruction.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: February 18, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: David H Hanes
  • Patent number: 8656487
    Abstract: Deterring output of data from a computing platform may be accomplished by launching a driver to filter write requests to selected output ports of the computing platform, receiving a write request, and denying the write request when the write request is for a selected output port identified as being in a read-only mode.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: February 18, 2014
    Assignee: Intel Corporation
    Inventors: Michael A. Rothman, Vincent J. Zimmer
  • Patent number: 8656058
    Abstract: A method for back-off retry with priority routing in a single, cohesive SAS expander includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the single, cohesive SAS expander, wherein the single, cohesive expander includes a first SAS expander, and at least one additional SAS expander via at least one inter-expander link (IEL). The routing of data may further include routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes determining link availability between the second SAS expander and the port of the device, and, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: February 18, 2014
    Assignee: LSI Corporation
    Inventors: Stephen B. Johnson, Christopher McCarty, Wiliam Petty, Jeffrey J. Gauvin
  • Patent number: 8656066
    Abstract: Provided are techniques for storing one or more storage rules for each of one or more storage locations, along with one or more actions to be taken for each storage rule that is violated, intercepting an I/O operation issued to the storage subsystem, and determining whether the I/O operation violates one or more of the storage rules. In response to determining that the I/O operation violates one or more of the storage rules, an application that issued the I/O operation is identified and each of the one or more actions associated with the one or more violated storage rules are performed.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gavin S. Johnson, Michael J. Koester, John R. Paveza, Carrie J. Van Noorden
  • Publication number: 20140047138
    Abstract: An expansion module is configured to provide expansion functions to a mobile electronic device. The expansion module includes a cloud device and at least one first expansion device. The cloud device includes a first expansion bus interface and a network interface. The first expansion device is coupled to the cloud device in a daisy-chain manner, wherein each of the first expansion device includes at least one first peripheral device. The cloud device is coupled to the mobile electronic device through the first expansion bus interface or the network interface, and provides the first peripheral device to the mobile electronic device for use.
    Type: Application
    Filed: December 13, 2012
    Publication date: February 13, 2014
    Applicant: ACER INCORPORATED
    Inventor: Kim Yeung Sip
  • Patent number: 8645591
    Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: February 4, 2014
    Assignee: AFTG-TG, LLC
    Inventor: Phillip M. Adams
  • Patent number: 8645592
    Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: February 4, 2014
    Assignee: Microsoft Corporation
    Inventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington
  • Publication number: 20140032797
    Abstract: In order to be able to replace a first signal box, connected to an electronic second signal box, in relay engineering with a further electronic third signal box in a time- saving fashion, the electronic second signal box used is an electronic second signal box having such generic functionality for its inputs/outputs that setting up a databus connection between the databus input/output of the further electronic third signal box and a databus input/output of the electronic second signal box involves a databus input/output of the electronic second signal box being activated and the relay interface input/output thereof being deactivated. An interruption of the databus connection involves the databus input/output of the electronic second signal box being deactivated and the relay interface input/output thereof being activated.
    Type: Application
    Filed: April 3, 2012
    Publication date: January 30, 2014
    Applicant: Siemens Aktiengesellschaft
    Inventor: Thomas Vierling
  • Patent number: 8639864
    Abstract: A diplex FPGA is utilized to fan out a single high speed host universal asynchronous receiver transmitter (“UART”) channel into a number of diplex UART channels. The diplex FPGA includes a microprocessor, memory, a host UART and a number of diplex UARTs. In operation, the microprocessor polls each of the UARTs in a “round robin” manner and accepts packets from the host UART for transmission downstream and from the diplex UARTs for transmission upstream.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 28, 2014
    Assignee: EMC Corporation
    Inventors: Douglas R. Sullivan, Howard G. Drake, Matthew Yellen
  • Patent number: 8639855
    Abstract: Provided is a method for the collection and storage of information related to the operation of a chip module. The disclosed technology provides a chip data collection and storage controller. In one embodiment, a chip module is provided with a stand-alone memory that records information relevant to potential debugging operations. The stand-alone memory is on the same chip module as the chip die but is not part of the chip die. A data bus is provided between the chip module and the memory. In addition, the memory has I/O access so that information can be accessed in the event that the chip module cannot be accessed. Stored information includes, but is not limited to, environmental conditions, performance information, errors, time usage, run time, number of power on cycles, the highest temperature experience by the chip, wafer and x, y data, manufacturing info, FIR errors, and PRSO, SRAM PSRO values.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael W. Harper, Larry S. Leitner, Mack W. Riley
  • Patent number: 8626970
    Abstract: Access to an input/output adapter by a configuration is controlled. For each requested access to an adapter, checks are made to determine whether the configuration is authorized to access the adapter. If it is not authorized, then access is denied. If it is authorized, but access should be temporarily blocked, then instruction execution is altered to indicate such. If access is permitted, but should be blocked for another reason (other than temporarily), then access is denied.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: David Craddock, Mark S. Farrell, Beth A. Glendening, Thomas A. Gregg, Dan F. Greiner
  • Patent number: 8626966
    Abstract: Systems and methods and computer program products are disclosed to determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method includes, forming a logical channel from a source device to a sink device where the logical channel is configured to carry the source data stream and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel. Another method includes, detecting a logical channel in a received data stream where the logical channel includes the source data stream, recovering one or more rate parameters from the received data stream, determining a data rate of the logical channel, and determining the data rate of the source data stream based on the data rate of the logical channel and the one or more rate parameters.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: January 7, 2014
    Assignee: ATI Technologies ULC
    Inventors: Nicholas J. Chorney, Collis Q. Carter
  • Patent number: 8621119
    Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: December 31, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyoshi Serizawa, Yasutomo Yamamoto, Norio Shimozono, Akira Deguchi, Hisaharu Takeuchi, Takao Sato, Hisao Homma
  • Publication number: 20130346644
    Abstract: A system and method for effectively implementing an electronic image hub device includes a peripheral device, such as a digital camera, that may be periodically connected to the image hub device by a system user. The system user may then utilize the image hub device to transfer captured data from the peripheral device to a specific data destination, such as a user service on a distributed computer network. The peripheral device also may utilize the image hub device to recharge batteries that become depleted through operation of the peripheral device. The system user may then subsequently access and utilize the captured data from the data destination in accordance with the present invention.
    Type: Application
    Filed: August 25, 2013
    Publication date: December 26, 2013
    Applicants: Sony Electronics Inc., Sony Corporation
    Inventors: Clay Fisher, Steven Goldstein, David Longendyke
  • Patent number: 8615608
    Abstract: A method, storage medium, and system for a managed audio bell/intercom including a controller and audio devices connected by an industry standardized network, wherein the controller contains logic to distribute action via the network to the audio devices.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 24, 2013
    Inventor: Terry Daniel Weidig
  • Patent number: 8612644
    Abstract: A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: December 17, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Kumasawa, Takashi Chikusa, Satoru Yamaura
  • Patent number: 8612640
    Abstract: Functions of platform layer based on platform program are separated into a resource manager layer that performs logical controls for hardware resources and a resource controller layer that performs physical controls for the hardware resources. The resource manager layer requires identifying a desired data based on an application program, but does not require knowing the actual address of the desired data in a storing unit. The resource controller layer knows the actual address, and physically reads out and replies the data instructed by the resource controller layer.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: December 17, 2013
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Yuri Kishita
  • Patent number: 8605719
    Abstract: Source circuits (10) produce messages that may each be processed by any one of a plurality of processing circuits (14). A network of distributor circuits is provided between the source circuits and the processing circuits (14). Local decisions by the distributor circuits in the network decide for each message to which one of the processing circuits the message will be routed. Messages are supplied to at least two parallel distributor circuits. These distributor circuits (12a) select from further distributor circuits (12b) in the network on the basis of current availability of individual ones of the further distributor circuits (12b). The respective messages are in turn forwarded from the selected further distributor circuits (12b) to data processing circuits (14) along routes selected by the selected further distributor circuits (12b) on the basis of current availability of the data processing circuits (14) and/or subsequent distributor circuits (12c) in the network.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: December 10, 2013
    Assignee: ST-Ericsson SA
    Inventor: Cornelis H. Van Berkel
  • Patent number: 8607061
    Abstract: Methods of operating memory systems and memory systems are disclosed, such as a memory system having a memory array storing a code generating program to instruct a processor to generate a code, and a register to store a code generated by the processor, where the register is configured to allow a write operation to the memory array in response to a match of a code stored in the register and where the match is controlled in response to a request from a utility program being executed by the processor.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: December 10, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Robert Gentile
  • Patent number: 8606976
    Abstract: A data stream flow-controller controls a transfer of data between a data processing device and an interconnection network. The flow controller includes interfaces for interfacing the controller on the network side and on the processing device side, a configurable storage for buffering queues of data in the controller before transfer to destination, and a programmable controller to control the storage to define queue parameters.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: December 10, 2013
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l.
    Inventors: Giuseppe Desoli, Jean-Philippe Cousin, Gilles Pelissier, Badr Bentaybi
  • Patent number: 8607214
    Abstract: In a data processing system which runs a plurality of operating systems, a channel device can be shared by the plurality of operating systems. In addition, a channel device which supports port multiplexing can also be shared by a plurality of operating systems. The channel device includes a plurality of IDs each indicating that the channel device is a medium for performing input/output processing, and an input/output processing controller for assigning one operating system to each of the IDs, and controlling a data transfer independently for each ID to control a plurality of data transfers. Further, in a channel device which has a plurality of ports, an input/output processing controller is provided for assigning an operating system to each of the ports, and transferring data independently for each port to control the plurality of ports.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: December 10, 2013
    Assignee: Hitachi Ltd.
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Megumu Hasegawa, Takeshi Shigeno
  • Patent number: 8605307
    Abstract: A communication device that communicates as a device with a plurality of hosts by using a communication interface that is designed to be used for a point-to-multipoint network on which a single host is connected to a plurality of devices, includes a control unit that controls to cause a disconnecting unit to disconnect the communication device from a destination host that is among the hosts capable of establishing a communication path with the communication device and is connected to the communication device using host identification information and device control information stored in a storage unit, and cause a connecting unit to connect the communication device to a next destination host from among the hosts to switch the hosts sequentially.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: December 10, 2013
    Assignee: Ricoh Company, Limited
    Inventor: Tomohide Takano
  • Patent number: 8601296
    Abstract: For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 3, 2013
    Assignee: Intel Corporation
    Inventors: Jaya L. Jeyaseelan, Jim Walsh, Robert E. Gough, Barnes Cooper, Neil W. Songer
  • Patent number: 8593960
    Abstract: In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 26, 2013
    Assignee: Intel Corporation
    Inventors: Michael Kauschke, Gautam B. Doshi