Abstract: According to one embodiment, a memory system includes a non-volatile memory, a resource managing unit that reclaims resources associated with the non-volatile memory and increases the resources, when the usage of the resources associated with the non-volatile memory reaches the predetermined amount, a transmission rate setting unit that calculates a setting value of the transmission rate to receive the write data from a host device, and a transmission control unit that receives the write data from the host device and transmits the received write data to the non-volatile memory. The transmission rate setting unit calculates a small setting value when the usage of the resources associated with the non-volatile memory increases. The transmission control unit executes the reception of the write data from the host device at the transmission rate of the setting value, while the resource managing unit reclaims the resources.

Abstract: According to one embodiment, a memory system includes a chip including a cell array and first and second caches configured to hold data read out from the cell array; an interface configured to manage a first and a second addresses; a controller configured to issue a readout request to the interface; and a buffer configured to hold the data from the chip. The interface transfers the data in the first cache to the buffer without reading out the data from the cell array if the readout address matches the first address, transfers the data in the second cache to the buffer without reading out the data from the cell array if the readout address matches the second address, and reads out the data from the cell array and transfers the data to the buffer if the readout address does not match either one of the first or second address.

Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.

Abstract: When a command to restore a logical unit is issued after a command to delete the logical unit, the logical unit is restored easily. When a controller receives an LU deletion command from a management terminal and if the relevant LU is a normal LU, it retains information about the deletion target LU, from among information in an LU management table, as reset information; and if the relevant LU is a virtual LU, the controller retains information about the deletion target LU, from among information in a virtual address table, as the reset information. If the controller receives an LU restoration command to restore the deletion target LU as an access target LU, from the management terminal, it restores the retained reset information as setting information corresponding to the access target LU and manages the restored setting information by using the LU management table or the virtual address table, thereby processing an access request from a host computer.

Abstract: Disclosed is a software architecture supporting a large-capacity collective memory layer in a multi-node system by using a remote direct memory access technique and a software virtualization technique and a computing system performing computing processing by using the architecture. In particular, provided is a software architecture including: a memory region managing module collectively managing a predetermined memory region of a node, a memory service providing module providing a large-capacity collective memory service to a virtual address space in a user process, and a memory sharing support module supporting sharing of the large-capacity collective memory of the multi-node system.

Abstract: The present invention is directed towards systems and methods for integrating cache managing and application firewall processing in a networked system. In various embodiments, an integrated cache/firewall system comprises an application firewall operating in conjunction with a cache managing system in operation on an intermediary device. In various embodiments, the application firewall processes a received HTTP response to a request by a networked entity serviced by the intermediary device. The application firewall generates metadata from the HTTP response and stores the metadata in cache with the HTTP response. When a subsequent request hits in the cache, the metadata is identified to a user session associated with the subsequent request. In various embodiments, the application firewall can modify a cache-control header of the received HTTP response, and can alter the cookie-setting header of the cached HTTP response.

Abstract: Systems and methods for destaging storage tracks from cache are provided. One system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes writing data to the plurality of storage tracks and incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes scan each of the storage tracks in each of multiple scan cycles, decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count. Also provided are physical computer storage mediums including a computer program product for performing the above method.

Abstract: A technique for limiting an amount of write data stored in a cache memory includes determining a usable region of a non-volatile storage (NVS), determining an amount of write data in a current write request for the cache memory, and determining a failure boundary associated with the current write request. A count of the write data associated with the failure boundary is maintained. The current write request for the cache memory is rejected when a sum of the count of the write data associated with the failure boundary and the write data in the current write request exceeds a determined percentage of the usable region of the NVS.

Abstract: One or more requests from a client for data representation items can be received by an items manager. The data representation items can represent data items in a data source. In response, the items manager can perform the following: generating placeholders corresponding to the data representation items; returning the placeholders to the client; fetching the data items from the data source; providing the data representation items to the client; and informing the client that the placeholders are to be replaced with the data representation items. The items manager may determine whether each data representation item can be synchronously returned to the client. If so, the items manager may return that data representation item synchronously, and may forego providing the client with a placeholder for that data representation item. This may allow a client to interact with a single interface for both synchronous and asynchronous data sources.

Abstract: Provided are a computer program product, system, and method for determining server write activity levels to use to adjust write cache size. Information on server write activity to the cache is gathered. The gathered information on write activity is processed to determine a server write activity level comprising one of multiple write activity levels indicating a level of write activity. The determined server write activity level is transmitted to a storage server having a write cache, wherein the storage server uses the determined server write activity level to determine whether to adjust a size of the storage server write cache.

Abstract: A method for optimizing processing in a SIMD core. The method comprises processing units of data within a working domain, wherein the processing includes one or more working items executing in parallel within a persistent thread. The method further comprises retrieving a unit of data from within a working domain, processing the unit of data, retrieving other units of data when processing of the unit of data has finished, processing the other units of data, and terminating the execution of the working items when processing of the working domain has finished.

Abstract: An L2 cache, method and computer program product for transferring an inbound bus operation to a processor side handling machine. The method includes a bus operation handling machine accepting the inbound bus operation received over a system interconnect, the bus operation handling machine identifying a demand operation of the processor side handling machine that will complete the bus operation, the bus operation handling machine sending the identified demand operation to the processor side handling machine, and the processor side handling machine performing the identified demand operation.

Abstract: A method for providing DRM files using caching includes identifying DRM files to be displayed in a file list in response to a request, decoding a number of first DRM files from among the identified DRM files and caching the first DRM files in a first memory space, and reading the first DRM files in the first memory space in response to the request. Then, a system displays the first DRM files as a file list in a display area. The second DRM files from among the identified DRM files other than the first DRM files are not initially decoded, and file data related to the second DRM files are cached in a second memory space. DRM files from among the second DRM files are subsequently decoded in response to a subsequent command.

Abstract: A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like.

Abstract: A method and apparatus are described for selectively performing explicit and implicit data line reads. A controller, located in a cache, individually monitors the data resource availability for each of a plurality of sub-caches also located in the cache. The controller receives a data line request, generates an individual implicit tag request for each of the sub-caches that currently have sufficient data resources to perform an implicit data line read, and generates an individual explicit tag request for each of the sub-caches that do not currently have sufficient data resources to perform an implicit data line read. Each tag request includes an address of the requested data line and an indicator, (represented by at least one bit), of whether the tag request is an explicit or implicit tag request.

Abstract: An apparatus and method is described herein for providing instantaneous, efficient cache state recover upon an end of speculative execution. Speculatively accessed entries of a cache memory are marked as speculative, which may be on a thread specific basis. Upon an end of speculation, the speculatively marked entries are transitioned in parallel by a speculative port to their appropriate, thread specific, non-speculative coherency state; these parallel transitions allow for instantaneous commit or recovery of speculative memory state.

Abstract: A method of managing memory of a computing device includes providing a first memory that can be allocated as cache memory or that can be used by a computing device component. A first memory segment can be allocated as cache memory in response to a cache miss. Cache size can be dynamically increased by allocating additional first memory segments as cache memory in response to subsequent cache misses. Cache memory size can be dynamically decreased by reallocating first memory cache segments for use by computing device components. The cache memory can be a cache for a second memory accessible to the computing device. The computing device can be a mobile device. The first memory can be an embedded memory and the second memory can comprise embedded, removable or external memory, or any combination thereof. The maximum size of the cache memory scales with the size of the first memory.

Abstract: Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.

Abstract: A method and apparatus for accelerated shared data migration between cores is disclosed.

Abstract: A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The present invention is further configured to enable processing core and memory utilization by external systems through virtualization.

Abstract: A processing pipeline 6, 8, 10, 12 is provided with a main query stage 20 and a fetch stage 22. A buffer 24 stores program instructions which have missed within a cache memory 14. Query generation circuitry within the main query stage 20 and within a buffer query stage 26 serve to concurrently generate a main query request and a buffer query request sent to the cache memory 14. The cache memory returns a main query response and a buffer query response. Arbitration circuitry 28 controls multiplexers 30, 32 and 34 to direct the program instruction at the main query stage 20, and the program instruction stored within the buffer 24 and the buffer query stage 26 to pass either to the fetch stage 22 or to the buffer 24. The multiplexer 30 can also select a new instruction to be passed to the main query stage 20.

Abstract: A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like.

Abstract: An object is to efficiently set configurations of a storage apparatus. Provided is an information apparatus communicably coupled to a storage apparatus 10, which validates a script executed by the storage apparatus 10 for setting a configuration of the storage apparatus 10, the information apparatus generating configurations of the storage apparatus 10 when after each command described in a script is executed sequentially; and performing consistency validation on the script by determining whether or not the command described in the script is normally executable in a case the command is executed on an assumption that the storage apparatus 10 has the configuration immediately before the execution.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The system is further configured to delegate computational or memory resource needs to a plurality of sub-processing cores for processing to satisfy application demands.

Abstract: Data storage apparatus and methods are disclosed. A disclosed example data storage apparatus comprises a cache layer and a processor in communication with the cache layer. The processor is to dynamically enable or disable the cache layer via a cache layer enable line based on a data store access type.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.

Abstract: Target data is allocated into caches of a shared-memory multiprocessor system during a runtime environment. The target data includes a plurality of data items that are allocated onto separate cache lines. Each data item is allocated on a separate cache line regardless of the size of the cache line of the system. The data items become members of a wrapper types when data items are value types. The runtime environment maintains a set of wrapper types of various sizes that are of typical cache line sizes. Garbage data is inserted into the cache line in cases where data items are reference types and data is stored on a managed heap. The allocation also configures garbage collectors in the runtime environment not to slide multiple data items onto the same cache line. Other examples are included where a developer can augment the runtime environment to be aware of cache line sizes.

Abstract: A selective cache includes a set configured to receive data evicted from a number of primary sets of a primary cache. The selective cache also includes a counter associated with the set. The counter is configured to indicate a frequency of access to data within the set. A decision whether to replace data in the set with data from one of the primary sets is based on a value of the counter.

Abstract: Methods and structure for automated determination and reconfiguration of the size of a cache memory in a storage system. Features and aspects hereof generate historical information regarding frequency of hits on cache lines in the cache memory. The history maintained is then analyzed to determine a desired cache memory size. The historical information regarding cache memory usage may be communicated to a user who may then direct the storage system to reconfigure its cache memory to a desired cache memory size. In other embodiments, the storage system may automatically determine the desired cache memory size and reconfigure its cache memory. The method may be performed automatically periodically, and/or in response to a user's request, and/or in response to detecting thrashing caused by least recently used (LRU) cache replacement algorithms in the storage system.

Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Abstract: A computing system is provided. A flash memory device includes at least one mapping block, at least one modification block and at least one cache block. A processor is configured to perform: receiving a write command with a write logical address and predetermined data, loading content of a cache page from the cache block corresponding to the modification block according to the write logical address to a random access memory device in response to that a page of the mapping block corresponding to the write logical address has been used, the processor, reading orderly the content of the cache page stored in the random access memory device to obtain location information of an empty page of the modification block, and writing the predetermined data to the empty page according to the location information. Each cache page includes data fields to store location information corresponding to the data has been written in the pages of the modification block in order.

Abstract: There are provided a mass storage system comprising a control layer operatively coupled to a physical storage space and operable to interface with one or more clients and to present to said clients a plurality of logical volumes. The method of operating the storage system comprises: dividing one or more logical volumes into a plurality of statistical segments with predefined size; assigning to each given statistical segment a corresponding activity level characterizing statistics of I/O activity with regard to data portions within the given statistical segment, said statistics collected over a plurality of cycles of fixed counting length; and managing one or more data storage processes in the storage system (e.g. a background defragmentation process, a background garbage collection process, a destage management process, etc.) using said activity level.

Abstract: Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.

Abstract: A method of virtual cache window headers for long term access history is disclosed. The method may include steps (A) to (C). Step (A) may receive a request at a circuit from a host to access an address in a memory. The circuit generally controls the memory and a cache. Step (B) may update the access history in a first of the headers in response to the request. The headers may divide an address space of the memory into a plurality of windows. Each window generally includes a plurality of subwindows. Each subwindow may be sized to match one of a plurality of cache lines in the cache. A first of the subwindows in a first of the windows may correspond to the address. Step (C) may copy data from the memory to the cache in response to the access history.

Abstract: A method and apparatus to utilize a strong ordering scheme to be performed on memory operations in a processor to prevent performance degradation caused by out-of-order memory operations is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing information associated with a first load operation in a load queue, the first load operation being executed out-of-order with respect to one or more second load operations. The method also includes detecting a snoop hit on the first load operation. The method further includes re-executing the first load operation in response to detecting the snoop hit.

Abstract: Some described embodiments provide a system that performs stores in a memory system. During operation, the system receives a store for a first thread. The system then creates an entry for the store in a store queue for the first thread. While creating the entry, the system requests a store-mark for a cache line for the store, wherein the store-mark for the cache line indicates that one or more store queue entries are waiting to be committed to the cache line. The system then receives a response to the request for the store-mark, wherein the response indicates that the cache line for the store is store-marked. Upon receiving the response, the system updates a set of ordered records for the first thread by inserting data for the store in the set of ordered records, wherein the set of ordered records include store-marked stores for the first thread.

Abstract: Systems and methods for cache defeat detection are disclosed. Moreover, systems and methods for caching of content addressed by identifiers intended to defeat cache are further disclosed. In one aspect, embodiments of the present disclosure include a method, which may be implemented on a system, of resource management in a wireless network by caching content on a mobile device. The method can include detecting a data request to a content source for which content received is stored as cache elements in a local cache on the mobile device, determining, from an identifier of the data request, that a cache defeating mechanism is used by the content source, and/or retrieving content from the cache elements in the local cache to respond to the data request.

Abstract: A method of operation of a data storage system includes: enabling a system interface for receiving host commands; updating a mapping register for monitoring transaction records of a logical block address for the host commands including translating a host virtual block address to a physical address for storage devices; accessing by a storage processor, the mapping register for comparing the transaction records with a tiering policies register; and enabling a tiered storage engine for transferring host data blocks by the system interface and concurrently transferring between a tier zero, a tier one, or a tier two if the storage processor determines the transaction records exceed the tiering policies register.

Abstract: A directory of a private cache hierarchy is provided to maintain coherency between data stored in the cache hierarchy, where the directory is to enable concurrent cache-to-cache transfer of data to two private caches from another private cache. This directory can be implemented in a system having a multi-core processor. Other embodiments are described.

Abstract: Improved methods and systems for granular opportunistic locking mechanisms (oplocks) are provided for increasing file caching efficiency. Oplocks can be specified with a combination of three possible granular caching intentions: read, write, and/or handle. An oplock can be specified with an identifier that indicates a client/specific caller to avoid breaking the original oplock due to an incompatibility from other requests of the same client. An atomic oplock flag is added to create operations that allow callers to request an atomic open with an oplock with a given file.

Abstract: A system includes logic to cache at least one block in at least one cache if the block has a popularity that compares favorably to the popularity of other blocks in the cache, where the popularity of the block is determined by reads of the block from persistent storage and reads of the block from the cache.

Abstract: A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.

Abstract: To aim to provide a cache memory device that performs a line size determination process for determining a refill size, in advance of a refill process that is performed at cache miss time. According to the line size determination process, the number of reads/writes of a management target line that belongs to a set is acquired (S51), and in the case where the numbers of reads completely match one another and the numbers of writes completely match one another (S52: Yes), the refill size is determined to be large (S54). Otherwise (S52: No), the refill size is determined to be small (S55).

Abstract: A remote copy system includes a first storage system including a first storage controller arid a first data volume. The first storage controller is configured to control data access requests to the first data volume. The first storage system is configured to store write data in the first data volume upon receiving a write request from a first host associated with the first storage system and generate a journal including control data and journal data A second storage system includes a journal volume and configured to receive and store the journal generated by the first storage system in the journal volume. A third storage system includes a second data volume and configured to receive the journal from the second storage system and store the journal data of the journal to the second storage system according to information provided in the control data.

Abstract: A technique for determining a data window size allows a set of predicted blocks to be transmitted along with requested blocks. A stream enabled application executing in a virtual execution environment may use the blocks when needed.

Abstract: A system and method for storing data in a content-addressable system is provided. The system includes a content-addressable storage system and a persistent cache. The persistent cache includes a temporary address generator that is configured to generate a temporary address which is associated with data to be stored in the persistent cache, and a non-content-addressable storage system configured to store and retrieve data in the persistent cache using the temporary address. The persistent cache further comprises an address translator configured to map a temporary address associated with the data in the non-content addressable storage system with a content address associated with the data in the content-addressable storage system.

Abstract: A false sharing detecting apparatus for analyzing a multi-thread application, the false sharing detecting apparatus includes an operation set detecting unit configured to detect an operation set having a chance of causing performance degradation due to false sharing, and a probability calculation unit configured to calculate a first probability defined as a probability that the detected operation set is to be executed according to an execution pattern causing performance degradation due to false sharing, and calculate a second probability based on the calculated first probability. The second probability is defined as a probability that performance degradation due to false sharing occurs with respect to an operation included in the detected operation set.

Abstract: A cloud storage appliance receives one or more read requests for data stored in a storage cloud. The cloud storage appliance determines, for a time period, a total amount of bandwidth that will be used to retrieve the requested data from the storage cloud. The cloud storage appliance then determines an amount of remaining bandwidth for the time period. The cloud storage appliance retrieves the requested data from the storage cloud in the time period to satisfy the one or more read requests. The cloud storage appliance additionally retrieves a quantity of unrequested data from the storage cloud in the time period, wherein the quantity of retrieved unrequested data is based on the amount of remaining bandwidth for the time period.

Abstract: According to one embodiment, a computing machine includes a virtual machine operated on a virtual machine monitor, the computing machine includes a first memory device, and a second memory device. The virtual machine monitor is configured to assign a part of a region of the first memory device as a third memory device to the virtual machine and to assign a part of a region of the second memory device as a fourth memory device to the virtual machine. The virtual machine comprises a first cache control module configured to use the fourth memory device as a read cache of the third memory device.