Abstract: A method for recovery of lost and/or corrupted data transmitted from a transmitter device to a receiver device. The data is coded by an encoder connected to the transmitter device. The data is transmitted from the transmitter device to the receiver device via a transmission system and is decoded by means of a decoder connected to the receiver device. This is performed through application of a low density parity check method, wherein lost and/or corrupted data is restored during decoding. The decoding is performed by solving the equation system of the parity check matrix H. The parity check matrix H is brought into a triangular form by column and/or row permutations. Columns of a sub-matrix B of the matrix H which impede the triangulation process are shifted into a sub-matrix P of the matrix H so that the triangulation process can be continued until the matrix H except for the sub-matrix P has been completely brought into a triangular form.

Abstract: Techniques for generating soft values for parity bits in a convolutional decoding process are disclosed. An exemplary method comprises, for each of at least one iteration in at least one soft-input soft-output decoder, calculating intermediate probability values for each possible transition between a first plurality of candidate decoder states at a first time and a second plurality of candidate decoder states at a second time. Two or more partial sums are then computed from the intermediate probability values, wherein the partial sums correspond to possible combinations of two or more systematic bits, two or more parity bits, or at least one systematic bit and at least one parity bit. Soft values, such as log-likelihood values, are then estimated for each of at least one systematic bit and at least one parity bit of the received communications data corresponding to the interval between the first and second times, based on the partial sums.

Abstract: A method for providing data protection for data stored within a Random Access Memory element. The method comprises receiving data to be written to memory, dividing the received data into a plurality of data sections, applying error correction codes to the data sections to form codeword sections, interleaving the codeword sections to form an interleaved data codeword, and writing within a single clock cycle the interleaved data codeword to memory.

Abstract: LDPC codes robust to non-stationary narrowband ingress noise. Particularly designed LDPC codes are adapted to address deleterious noise-effects incurred within LDPC coded signals that propagate via a communication channel (such as from a transmitting communication device to a receiving communication device). Such LDPC matrices employed for encoding and/or decoding such LDPC coded signals are composed of sub-matrices (e.g., all-zero values sub-matrices and/or CSI (Cyclic Shifted Identity) sub-matrices). The sub-matrices are generally uniform in size and square in shape. Based on certain operational conditions, such as communication channel noise, various operations within a communication device are adaptively modified (e.g., signaling, modulation, demodulation, symbol mapping, metric generation, decoding, etc.).

Abstract: Systems and methods for encoding user information and decoding signal vectors using fractional encoding/decoding and set partitioning. A fractional encoder can select a coset for transmitting or storing user information based on one or more deterministic bits and on encoded user information. The deterministic bits limit the encoder to using only a subset of the available signal vectors in a modulation scheme. A fractional decoder can receive a signal vector, and can find at least two nearest neighbors in each dimension. The fractional decoder can form a set of potential signal vectors using only the at least two nearest neighbors. The decoder may determine which of these potential signal vectors are valid within the fractional signaling scheme, and can decode the received signal vector based on the valid potential signal vectors.

Abstract: Certain embodiments of the present invention are efficient run-time methods for creating and updating a RAM list of dominant trapping-set profiles for use in (LDPC) list decoding. A decoded correct codeword is compared to a near codeword to generate a new trapping-set profile, and the profile written to RAM. Record is kept of how many times RAM has been searched since a profile was last matched. Profiles that have not been matched within a specified number of searches are purge-eligible. Purge-eligible profiles are further ranked on other factors, e.g., number of times a profile has been matched since it was added, number of unsatisfied check nodes, number of erroneous bit nodes. If there is insufficient free space in RAM to store a newly-discovered profile, then purge-eligible profiles are deleted, beginning with the lowest-ranked profiles, until either (i) sufficient free space is created or (ii) there are no more purge-eligible profiles.

Abstract: LDPC (Low Density Parity Check) coding and interleaving implemented in multiple-input-multiple-output (MIMO) communication systems. As described herein, a wide variety of irregular LDPC codes may be generated using GRS or RS codes. A variety of communication device types are also presented that may employ the error correcting coding (ECC) using a GRS-based irregular LDPC code, along with appropriately selected interleaving, to provide for communications using ECC. These communication devices may be implemented to in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).

Abstract: Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).

Abstract: An error detection unit performs erasure decoding for physical layer packets and an assembler assembles the received data into higher layer packets. Higher layer packets that are incomplete are not erased if the higher layer packets contain some data indicated as valid by the error detection unit. In the case of incomplete packets, the data is labeled by assigning a value to a reliability attribute for the data to enable the decoder to discriminate between valid and invalid data in the same packet. The decoder is modified to use “dimmed” data from the incomplete packets to perform decoding.

Abstract: A method and apparatus encode a source data stream via convolutional encoding or selected encoding scheme. Plural encoded data streams are interleaved and transmitted on a transmission channel. Data groups generated via convolutional or selected encoding are interleaved via time-interleaving functions to disperse selected bits within data groups, bits in between data groups, and bits in selected sets of data groups to facilitate reconstruction of the source data stream from at least a portion of the interleaved data stream received on at least one transmission channel. Subsets of bits of data groups are selected to allow reconstruction of the source data stream from more than one of plural transmission channels using a minimum number of subsets. Multiple combinations of subsets can be received on both transmission channels to reconstruct the source data stream following blockage of one channel.

Abstract: An approach is provided for processing structure Low Density Parity Check (LDPC) codes. Memory storing edge information and a posteriori probability information associated with a structured parity check matrix used to generate Low Density Parity Check (LDPC) coded signal are accessed. The edge information represent relationship between bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge information.

Abstract: Coded video data may be transmitted between an encoder and a decoder using multiple FEC codes and/or packets for error detection and correction. Only a subset of the FEC packets need be transmitted between the encoder and decoder. The FEC packets of each FEC group may take, as inputs, data packets of a current FEC group and also an untransmitted FEC packet of a preceding FEC group. Due to relationships among the FEC packets, when transmission errors arise and data packets are lost, there remain opportunities for a decoder to recover lost data packets from earlier-received FEC groups when later-received FEC groups are decoded. This opportunity to recover data packets from earlier FEC groups may be useful in video coding and other systems, in which later-received data often cannot be decoded unless earlier-received data is decoded properly.

Abstract: Method and apparatus for generating a set of generator polynomials for use as a tail biting convolutional code to operate on data transmitted over a channel comprises: (0) specifying a constraint and a low code rate for a tail biting convolutional code, where the low rate code is lower than 1/n (n being an integer greater than 4); (1) selecting valid combinations of generator polynomials to include in a pool of potential codes, each valid combination being a potential code of the low rate code; (2) determining first lines of a weight spectrum for each potential code in the pool and including potential codes of the pool having best first lines in a candidate set; (3) determining best codes of the candidate set based on the first L number of lines in the weight spectrum; (4) selecting an optimum code(s) from the best codes; and (5) configuring a circuit(s) of a data transceiver to implement the optimum code(s).

Abstract: LDPC coding systems for 60 GHz millimeter wave based physical layer extension. LDPC (Low Density Parity Check) encoding in cooperation with sub-carrier interleaving, in the context of orthogonal frequency division multiplexing (OFDM), and appropriate symbol mapping is performed in accordance with transmit processing as may be performed within a communication device. In a receiving communication device, receive processing may be performed on a received signal based on the type of LDPC, sub-carrier interleaving, and symbol mapping thereof. The LDPC code employed in accordance with such LDPC encoding may have a partial-tree like structure. In addition, appropriate manipulation of the bits assigned to respective sub-carriers may be performed to ensure that the bits emplaced in the MSB (Most Significant Bit) location of various symbols has some desired diversity (e.g., from different codewords, from appropriately different locations within a given codeword, etc.).

Abstract: A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.

Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.

Abstract: A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255,239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.

Abstract: A system and method are provided for parallel processing data that is forward error correction (FEC) protected with multiple codewords. The method accepts an electrical waveform representing a digital wrapper frame of interleaved FEC codewords. Typically, the codeword encoding is solved using an algorithm such as linear block codes, cyclical block codes, Hamming, Reed-Solomon, or Bose-Chaudhuri-Hocquenghem (BCH). The method calculates a first set of syndromes for a first codeword. In parallel with the calculation of the first set of syndromes, a second set of syndromes is calculated for a second codeword with a data component shared with the first codeword. Using the first set of syndromes, an error magnitude and location (EML) of the first codeword is performed. Using the second set of syndromes, an EML of the second codeword is performed in parallel with the EML of the first codeword.

Abstract: Data to be more robustly transmitted within 8VSB broadcast DTV signals are turbo coded using parallel concatenated convolutional coding (PCCC) and incorporated within the segments of data fields, the bytes of which are convolutionally interleaved before trellis coding and 8VSB symbol mapping. Packing the PCCC into payload fields of MPEG-2-compatible null data packets and Reed-Solomon coding the packets to generate the segments of data fields, the bytes of which are convolutionally interleaved, conditions legacy DTV receivers to disregard PCCC components not useful to them. Transversal packing turbo-coded Reed-Solomon codewords into the payload fields of MPEG-2-compatible null data packets increases the capability of those turbo-coded Reed-Solomon codewords to overcome burst errors. Repeated transmissions of the transversally packed turbo-coded Reed-Solomon codewords in whole or in part allows them to overcome protracted deep fades encountered during mobile reception of 8VSB DTV signals.

Abstract: Systems and methods enabling ultra-high-speed optical transport The systems and methods include receiving a modulated, encoded input stream. Channel impairments are removed using MAP equalization. Symbols are detected in the input stream to produce a stream of encoded data. The stream of encoded data is decoded with one or more low density parity check (LDPC) decoders that use an LDPC code built by modified progressive edge growth. The LDPC code is built by iteratively expanding trees from each variable node until all check nodes are connected to the respective variable node, while controlling both the local girth and the global girth of the code.

Abstract: An apparatus, and an associated method, for correcting errors in decoded data, decoded by a convolutional decoder, such as an SOVA (Soft Output Viterbi Algorithm). A CRC check is performed upon the decoded data. If the CRC check fails, a conclusion is made that the decoded data contains errors. Portions of the decoded data indicated to exhibit low levels of reliability are toggled with values of most-likely error events. A corrected sequence of the decoded data is formed that corrects for the errors in the decoded data.

Abstract: The original MCS of a system fault tree includes sufficient conditions required for a top system hazard. If a fault occurs in a component and the component is restored, the current MCS of a system and the critical components can be calculated on the basis of the original MCS by means of several calculation patterns.

Abstract: The invention is directed to a method and apparatus for decoding encoded data symbols. The invention is also directed to corresponding encoding methods. The decoder arrangement comprises an input for receiving encoded data and an identifier associated with a coding scheme used to create said encoded data. A processor in the decoding arrangement determines from the identifier, a mapping between said encoded data and the original data. A decoder uses the mapping to extract the original data from the encoded data. The operation of the decoder is independent of the coding scheme used in the encoding process.

Abstract: A method of generating a set of generator polynomials for use as a tail biting convolution code to operate on data transmitted over a channel comprises: (1) selecting valid combinations of generator polynomials to include in a pool of potential codes, each valid combination being a potential code; (2) determining first lines of a weight spectrum for each potential code in the pool and including potential codes of the pool having best first lines in a candidate set; (3) determining best codes of the candidate set based on the first L number of lines in the weight spectrum; (4) selecting an optimum code(s) from the best codes; and (5) configuring a shift register circuit(s) of a data transceiver to implement the optimum code(s).

Abstract: k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n?<n bits. The punctured codeword is exported to a corrupting medium such as a communication channel or a memory. A representation of the punctured codeword is imported from the corrupting medium and is decoded using a matrix H? that is smaller than H. For example, H? is m?=m?(n?n?)×n? and is derived by merging selected rows of H.

Abstract: Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.

Abstract: A receiving apparatus includes: a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data; a storing means for storing the decoded data; a second decoding means for applying decoding processing employing the outer code to the decoded data; and a control means for controlling storage and output of the decoded data in and from the storing means to suspend, while the control means causes the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the secon

Abstract: An optical device transmits ECC codewords using an interleaved technique in which a single ECC codeword is transmitted over multiple optical links. In one particular implementation, the device may include an ECC circuit configured to supply ECC codewords in series, the codewords being generated by the ECC circuit based on input data and each of the codewords including error correction information and a portion of the data. The device may further include a serial-to-parallel circuit configured to receive each of the codewords in succession, and supply data units in parallel, each of the data units including information from a corresponding one of the codewords; an interleaver circuit to receive the data units in parallel and output a second data units in parallel, each of the second data units including bits from different ones of the data units; and a number of output lines, each of which supplying a corresponding one of the second data units.

Abstract: Outputting information for recovering a sequence of data is disclosed. Outputting includes making a decision that selects a first sequence of states corresponding to a surviving path, determining a second sequence of states corresponding to a non-surviving path associated with the decision, and defining a possible error event based at least in part on the second sequence of states.

Abstract: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

Abstract: The present invention discloses a coding method, a coding device, a decoding method and a decoding device for low density generator matrix codes.

Abstract: A bandwidth sensing system operates to sense the existence of additional bandwidth available for transmitting data over a best effort communication. The operations include receiving an original block of data from a transmitting node and calculating error correction data based on the original block of data. The original block of data and the error correction data is then transmitted toward a receiving node. The data may be simply appended or, the entire block may be modified during the error correction data process. When the original block of data and error correction data is received at the receiving end associated with the receiving node, the data is analyzed to determine if any errors occurred in the transmission. If so, the error correction data is used to maintain the integrity of the transmitted data by restoring the original block.

Abstract: The present invention aims at providing an encoding device for error correction, encoding method for error correction and encoding program for error correction wherein countermeasures against eavesdropping are taken into account. To achieve this, in accordance with an aspect of the present invention there is provided an encoding device for error correction, the device comprises a generation means for generating randomly a vector u=(xk+1, . . . , xm) composed of m-k digit(s); a creation means for creating an x?=[xu]=(x1, . . . , xm) by concatenating the vector u=(xk+1, . . . , xm) composed of m-k digit(s) randomly created by the creation means to data x=(x1, . . . , k) to send; and an output means for outputting a vector of length n by carrying out [n, m] encoding of the x? created by the creation means.

Abstract: Detecting, avoiding and/or correcting problematic puncturing patterns in parity bit streams used when implementing punctured Turbo codes is achieved without having to avoid desirable code rates. This enables identification/avoidance of regions of relatively poor Turbo code performance. Forward error correction comprising Turbo coding and puncturing achieves a smooth functional relationship between any measure of performance and the effective coding rate resulting from combining the lower rate code generated by the Turbo encoder with puncturing of the parity bits. In one embodiment, methods to correct/avoid degradations due to Turbo coding are implemented by puncturing interactions when two or more stages of rate matching are employed.

Abstract: A method and apparatus for transmitting and receiving convolutionally coded data in a communication system employing a combination of Pulse Position Modulation (PPM) and Binary Phase Shift Keying (BPSK), wherein the code is selected to have error rate performance that is as good as the best convolutional code used with systems employing only BPSK.

Abstract: Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy.

Abstract: The present invention discloses a method and apparatus for performing forward error correction with a multi-dimensional Bose Ray-Chaudhuri Hocquenghem (BCH) product code, and a method for detecting false decoding errors in frame-based data transmission systems.

Abstract: An apparatus and method for reducing power consumption in a mobile communication system are provided. The apparatus includes a time slicing processor. When a frame border of the last section for determining a burst reception end time is not detected during a burst reception operation, the time slicing processor receives a burst enough to restore the whole MPE-FEC frame to the former state or receives an early burst reception end request for notifying that it is impossible to restore the whole MPE-FEC frame to the former state, and terminates the burst reception process.

Abstract: A method for determining a contribution of burst noise to a bit error rate in a digital system for reception of an interleaved forward error correction-enabled digital symbol stream is described. The method is based on identifying errored symbols at a decoding stage, determining their positions in the interleaved stream, and performing a windowing operation such that the errored symbols located within the window in the interleaved stream are designated as burst errored symbols. A corresponding digital receiver and a digital transmission system are also disclosed.

Abstract: An error correction code includes a separate error code portion for each of two or more separate burst erasure durations (or burst error durations). For each burst erasure duration, the code can be employed to recover from the burst erasure with a different delay time. Each error code portion has a particular parameter for burst duration (B) and delay (T), meaning that the code can be used to recover from a burst erasure of duration B with delay T. Each error code portion is based on separating the source symbols into sub-symbols and diagonally interleaving the sub-symbols based on the (B,T) parameters for the error code portion. Accordingly, different burst erasures are recovered from with different delays.

Abstract: A method for low-density parity-check hard decision decoding includes computing, for every decoding iteration, a discrepancy of extrinsic messages responsive to channel inputs of a receiver, performing a flipping of the channel inputs responsive to a comparison of the discrepancy of extrinsic messages to a flipping threshold, the flipping threshold for each decoding iteration being determined based on a threshold computation responsive to a channel error probability estimation in a first iteration of a decoding of the channel inputs, and check node decoding responsive to the flipping of channel inputs.

Abstract: Provided is an error correction code decoding apparatus capable of performing a decoding process efficiently for various interleaver sizes while suppressing an increase in apparatus size.

Abstract: Disclosed is a decoding method and device for low density parity check codes using dynamic scheduling. The low density parity check codes are sequentially decoded, and the messages are scheduled in the descending order of the difference between values before and after updating the message transmitted from the variable node to the check node.

Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.

Abstract: A system and method are provided for creating codewords using common partial parity products. The method initially accepts an algorithm for creating p indexed parity bit positions, where the parity bit for each position is calculated from mathematical operations performed on bits from n indexed user word positions. A first group of parity bit positions is found, where the parity bit for each position in the first group is calculated using at least a first number of common mathematical operations. A second group of parity bit positions is found, where the parity bit for each position in the second group is calculated using at least a second number of common mathematical operations. The common mathematical operations are subtracted from the first and second group of parity bit position calculations, so that unique mathematical operations can be found, associated with each parity bit position calculation in the first and second group.

Abstract: Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (?) values and check edge message (?) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.

Abstract: Permuted accelerated LDPC (Low Density Parity Check) decoder. This decoding approach operates by processing, in parallel, selected rows for multiple individual LDPC matrix rows from various sub-matrix rows (e.g., first group of rows from a first sub-matrix row, second group of rows from a second sub-matrix row, etc.). A memory structure of daisy chains is employed for memory management of APP (a posteriori probability) values and also for check edge messages/intrinsic information (?) values. A first group of daisy chains may be employed for memory management of the APP values, and a second group of daisy chains may be employed for memory management of the check edge messages. These daisy chains operate to effectuate the proper alignment of APP (or gamma(?)) values and check edge message/intrinsic information (?) values for their respective updating in successive decoding iterations.

Abstract: An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements connected in a series configuration. An input of a first one of the delay elements is adapted to receive a sum of first and second signals, the first signal generated as a sum of the input data sample and at least one of the delayed samples, and the second signal generated as an output of a single one of the delay elements. A third delay line in the encoder is operative to generate an output data sample as a function of the sum of the first and second signals and a delayed version of the sum of the first and second signals.

Abstract: An error correction coding device includes a time divider for dividing field data of L packets into N data packets and (L-N) parity packets, a first RS (Reed-Solomon) encoder adding parities of a predetermined number of bytes to the data packets, respectively, a storage unit for storing the data packets, and a second RS encoder generating parity packets corresponding to the stored data packets. An error correction decoding device includes a first RS decoder correcting errors in a horizontal direction of the field data using parities of the predetermined number of bytes included in the L packets, a storage unit storing the error-corrected data packets, and a second RS decoder correcting errors in a vertical direction of the field data using the parity packets. Thus, the error correction can be strongly performed using parities existing in the horizontal and vertical directions with respect to the field data.

Abstract: An error correction coding device includes a time divider for dividing field data of L packets into N data packets and (L-N) parity packets, a first RS (Reed-Solomon) encoder adding parities of a predetermined number of bytes to the data packets, respectively, a storage unit for storing the data packets, and a second RS encoder generating parity packets corresponding to the stored data packets. An error correction decoding device includes a first RS decoder correcting errors in a horizontal direction of the field data using parities of the predetermined number of bytes included in the L packets, a storage unit storing the error-corrected data packets, and a second RS decoder correcting errors in a vertical direction of the field data using the parity packets. Thus, the error correction can be strongly performed using parities existing in the horizontal and vertical directions with respect to the field data.