Abstract: A method is provided for quantizing an input signal. The number of equal quantized values during a period of time is counted thereby obtaining said number of counts. The counts exceeding a count threshold being defined as reliable counts, the counts lower than or equal to the count threshold being defined as unreliable counts. Two unreliable counts are calculated using a lower and a higher value for a first parameter in an extrapolating function. The first parameter is considered equivalent to the lower value if the two unreliable counts differ less than or equal to a count difference. The invention further discloses a corresponding tail extrapolator.

Abstract: A soft decision device and method for obtaining a soft decision value as a value expressing a probability as near the actual probability as possible by simple processing. The soft decision device and method are used to output a soft decision value for each bit of each symbol used for decoding the each symbol as a value corresponding to the function value obtained by applying a predetermined function for each bit to the sampled value of the each symbol according to the demodulated signal such that the probability distribution of the sampled value in each symbol point is the Gauss distribution. The function for each bit is approximated to a curve expressing the probability that each bit is 1 or 0 for the sampled value of each symbol of the demodulated signal and defined by using a quadratic function.

Abstract: A digital broadcasting system for transmitting/receiving a digital broadcasting signal and a data processing method are disclosed. First program table information and second program table information, which has an identifier different from an identifier of the first program information, are multiplexed and transmitted. The first program table information describes main service data through fixed reception channel, while the second program information described mobile service data through mobile reception channel. Thus, a broadcast receiving system can receive and output the mobile service data by parsing the second program table information.

Abstract: A communication system that performs encoding and decoding for communication includes a transmitting apparatus and a receiving apparatus. The transmitting apparatus includes a turbo encoding unit including a first encoding unit that encodes an input signal and generates a first parity bit by bit-based encoding and n (n=1, 2, 3, . . . ) second encoding units that encode the input signal and generate second parity bits by bit-based encoding, and a symbol mapping unit that maps an output from the turbo encoding unit to a symbol by bit-based mapping operation and modulates the output. And the receiving apparatus includes a demodulating unit that demodulates a transmission signal, and a turbo decoding unit that performs turbo decoding on the demodulated signal by bit-based decoding.

Abstract: A device and method for rate matching channel-encoded symbols in a data communication system. The rate matching device and method can be applied to a data communication system which uses one or both of a non-systematic code (such as a convolutional code or a linear block code) and a systematic code (such as a turbo code). In one aspect, the rate matching device includes a plurality of rate matching blocks, the number of the rate matching blocks being equal to a reciprocal of a coding rate of a channel encoder. The rate matching device can rate match the symbols encoded with a non-systematic code or the symbols encoded with a systematic code, by changing initial parameters including the number of input symbols, the number of output symbols, and the puncturing or repetition pattern determining parameters.

Abstract: A method for decoding an encoded message is described. The method includes obtaining a set of metrics which includes first and second state metrics, and first and second branch metrics. First and second offset values for the iteration are obtained. The first state and branch metrics are added together to obtain a first partial result. The second state and branch metrics are added together to obtain a second partial result. The second partial result is subtracted from the first partial result to obtain a difference. The first partial result and the first offset value are added together to obtain a first result. The second partial result and the second offset value are added together to obtain a second result. Either the first result or the second result is selected for output responsive to the difference. A log correction term is selected responsive to the difference.

Abstract: A digital broadcasting transmission system processes dual transport stream (TS) including multi turbo streams. The digital broadcasting transmission system includes a turbo processor to detect a turbo stream from a dual transport stream (TS) which includes a multiplexed normal stream and a turbo stream, encoding the detected turbo stream and stuffing the encoded turbo stream into the dual TS; and a transmitter to trellis-encode the processed dual TS, and to output the resultant stream, wherein the turbo processor encodes the turbo stream using a plurality of turbo processors. Accordingly, a plurality of turbo streams may be processed in parallel.

Abstract: A storage device and data processing method thereof is described. The invention provides different ECC for different memory pages. The storage device uses the long-bit ECC for easy interference page, and uses the short-bit ECC for hard interference page. Therefore, the accuracy of the data is maintained and the reading/writing speed is increased.

Abstract: A communication device configured to perform packet reception processing, with the header of a packet including a header sequence and a Reed-Solomon code, includes: a header check sequence inspecting unit configured to detect, based on the header check sequence included in a received packet header, an error of the header; a Reed-Solomon encoding unit configured to encode the header of a received packet other than the Reed-Solomon code to generate a Reed-Solomon code; a Reed-Solomon code inspecting unit configured to detect whether or not the Reed-Solomon code generated by the Reed-Solomon encoding unit is completely identical to the Reed-Solomon code within the received packet header; and a processing control unit configured to control payload processing of a received packet in accordance with the inspection results of the header check sequence inspecting unit and the Reed-Solomon code inspecting unit.

Abstract: The present techniques provide systems and methods for decoding an optical data signal returned from an optical disc to retrieve source information. The decoding method is based on a 16 state trellis diagram, and may decode an optical data signal encoded through a modulation code where the input-to-output relationship is not convolutional, such as the 17 Parity Preserve/Prohibit (17pp) modulation code. A trellis diagram may enable non-convolutional trellis-modulated data to be more efficiently decoded. Further, the 16 state trellis diagram of the present techniques provides a unique path for each input-to-output bit pair, such that no information about input bits may be lost on parallel paths in a trellis diagram.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: A channel adaptive iterative turbo decoder for computing with MAP decoders a set of branch metrics for a window of received data, computing the forward and reverse recursive path state metrics and computing from the forward and reverse recursive path state metrics the log likelihood ratio for 1 and 0 and interleaving the decision bits; and identifying those MAP decoder decision bits which are non-convergent, computing a set of branch metrics for the received data, computing from the forward and reverse recursive path state metrics the log likelihood ratio (LLR) for 1 and 0 for each non-converged decision bit and interleaving the non-convergent decision bits.

Abstract: The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.

Abstract: Methods and apparatus for performing error correction of data bits are disclosed. A forward metric calculation may be performed during a first window to generate a first group of calculated data. The first group of calculated data from the forward calculation may be stored in a memory location. A forward metric calculation may be performed during a second window to generate a second group of calculated data. The first group of calculated data may be read from the memory location and the second group of calculated data may be stored in the same memory location. The first group of calculated data may be used to calculate reverse metrics.

Abstract: Systems and methods of digital interface translation are described. One embodiment of the invention includes multiple receiver lanes, where at least one of the receiver lanes is configured to receive a data channel at a first data rate and encoded in accordance with an input digital interface standard, an auxiliary channel input configured to receive an auxiliary data channel, and a single transmitter lane configured to output a single data channel at a second data rate and encoded in accordance with an output digital interface standard.

Abstract: A method, system and article of manufacture for the storing convolution-encoded data on a redundant array of independent storage devices (RAID) is described. The convolution-encoded data comprises error correction coded data to eliminate the need for parity as used in conventional RAID data storage. The number of storage devices may vary to accommodate expansion of storage capacity and provide on demand storage.

Abstract: In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). The CNUs generate check-node messages using a scaled min-sum algorithm, an offset min-sum algorithm, or a scaled and offset min-sum algorithm. Initially, the controller selects a scaling factor and an offset value. The scaling factor may be set to one for no scaling, and the offset value may be set to zero for no offsetting. If the decoder is unable to correctly decode a codeword, then (i) the controller selects a new scaling and/or offset value and (ii) the decoder attempts to correctly decode the codeword using the new scaling and/or offset value. By changing the scaling factor and/or offset value, LDPC decoders of the present invention may be capable of improving error-floor characteristics over LDPC decoders that use only fixed or no scaling factors or fixed or no offsetting factors.

Abstract: There are provided a turbo decoding system of a CDMA mobile communication terminal, a transmission power control method, and a CDMA mobile communication terminal in which interference in the other users is suppressed by not increasing the transmission power of a base station to a value over the necessary value and excessive repetitive processing is prevented in the turbo decoding section to reduce consumption power. There are disposed a BLER measuring section 10 to measure BLER as reception quality for each number of decoding bits on the basis of a CRC judge result after an error correction by the turbo decoding section 4 and an outer loop power control and iteration control section 11 to control transmission power of a base station and to control the iteration count of turbo decoding on the basis of the reception quality of each number of decoding bits.

Abstract: Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices.

Abstract: A base station creates a dummy pattern added with an error correction code, during occurring of a control channel not allocated for transmission of control information, transmits the dummy pattern instead of control information at a power level lower than a normal power level. A mobile station decodes control information transmitted through the control channel, examines whether or not a value specified by the decoded control information is within a suitable range, and performs error detection of the decoded control information. The mobile station stops decoding of data transmitted through a data channel, upon judging that the value is not within the suitable range or detecting an error in the error detection.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.

Abstract: A method for communication includes receiving at a receiver a signal from a transmitter embodying data encoded with an error correction code. The signal is processed in order to extract a sequence of samples in a complex signal space. Scalar values are extracted from the samples and the scalar values are processed so as to define one or more clusters of scalar data points. Gain and noise of the signal are estimated responsively to the defined clusters. Bit value metrics for the signal are computed based on the samples and the estimated gain and noise of the signal. The error correction code is decoded using the bit value metrics.

Abstract: A cascade encoding method and apparatus are applied to a handheld television system or other fields. The method includes the following: A. Reed-Solomon (RS) encoding is performed on inputted Medium Access Control (MAC) packets, and coded MAC packets are outputted; and B. Low density parity check code (LDPC) encoding is performed on the coded MAC packets, and LDPC encoding blocks are outputted. The apparatus includes an RS coder and an LDPC coder. The RS encoding and LDPC encoding are cascaded to encode an inputted code flow, so as to reduce an error rate. Meanwhile, bytes in one RS encoding data block are dispersed into different LDPC blocks to be encoded through byte interleaving, thereby sufficiently utilizing error code characteristics of the RS encoding and the LDPC encoding for decoding, and improving error correction capability of a system.

Abstract: The present invention provides a method for decoding a low density generator matrix code (LDGC), applied for decoding transmitted original information bits encoded in LDGC code. The method comprises the following steps: A: deleting a part erased by a channel in a received code word sequence R filled by a known bit sequence to obtain an erased code word sequence Re, and deleting the rows corresponding to the erased part from a transposed matrix GIdgct of a generator matrix of the LDGC to obtain the erased generator matrix Ge; B: permuting columns of Ge such that an M-order square matrix with an element in the 0th row and 0th column being a vertex is a triangular matrix to obtain the permuted generator matrix Gf; and C: calculating the original information bits using Gf and Re.

Abstract: A stopping method for an iterative signal processing includes a first step of receiving the state signatures generated by the iterative signal processing. A next step includes accumulating the state signatures into a stopping index variable. A next step includes stopping iterative decoding when the stopping index variable is less than a predetermined threshold.

Abstract: An integrated circuit comprises forward error correction (FEC) decoder logic being coupled to memory and arranged to receive data, comprising application data, from a host application process. The FEC decoder logic performs error detection upon the received data. Logic is further arranged to transmit error free application data back to the host application process prior to performing error correction; and store in memory only application data in which errors are detected.

Abstract: A Low Density Parity Check (LDPC) encoding apparatus and method are provided. The LDPC encoding apparatus includes a controller for determining a number of zeros b to be inserted in an input information vector when a length of the input information vector is less than a length of a use information vector of a parity-check matrix, for selecting b stopping sets Sd using the parity-check matrix, for selecting one variable node from each of the b stopping sets Sd using a selection scheme, and for determining positions corresponding to the selected variable node from each of the b stopping sets Sd as positions where zeros are to be inserted.

Abstract: This disclosure relates generally to data decoding, and more particularly to iterative decoders for data encoded with a low-density parity check (LDPC) encoder. LDPC decoders are disclosed that use reduced-complexity circular shifters that may be used to decode predefined or designed QC-LDPC codes. In addition, methods to design codes which may have particular LDPC code performance capabilities and which may operate with such decoders using reduced-complexity circular shifters are provided. The generation of quasi-cyclic low density parity check codes and the use of circular shifters by LDPC decoders, may be done in such a way as to provide increased computational efficiency, decreased routing congestion, easier timing closure, and improved application performance.

Abstract: Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder-input LLR values (Lch) are adjusted based on the number b of unsatisfied check nodes in the decoded codeword produced by global iteration i?1. The improved turbo-equalization methods can be used as the sole turbo-equalization method for a given global decoding session, or interleaved with other turbo-equalization methods.

Abstract: Methods and devices are provided for intersymbol interference encoding in a solid state drive. In an illustrative embodiment, an nth data signal is received as input to a processing component. An intersymbol interference signal applicable to the nth data signal is provided, based on a set of prior-written data in a data storage array and a set of intersymbol interference behavior of the set of prior-written data in the data storage array, the data storage array being communicatively connected to the processing component. The nth data signal and the intersymbol interference signal applicable to the nth data signal are combined into an intersymbol-interference-corrected encoding of the nth data signal. The intersymbol-interference-corrected encoding of the nth data signal is provided as output from the processing component.

Abstract: Transmission techniques are provided that improve service continuity and reduce interruptions in delivery of content that can be caused by transitions that occur when the User Equipment (UE) moves from one cell to the other, or when the delivery of content changes from a Point-to-Point (PTP) connection to a Point-to-Multipoint (PTM) connection in the same serving cell, and vice-versa. Such transmission techniques enable seamless delivery of content across cell borders and/or between different transmission schemes such as Point-to-Multipoint (PTM) and Point-to-Point (PIP). Mechanisms for adjusting different streams and for recovering content from each data block during such transitions are also provided so that data is not lost during a transition. In addition, mechanisms for realigning data during decoding at a receiving terminal are also provided.

Abstract: A digital communication device is provided for decoding a data stream to generate a receiver output. In the digital communication device, a burst error detector determines burst noise locations corresponding to the data stream according to an error-check equation and accordingly generates a burst error indicator. Thereafter, an inner decoder decodes the data stream to generate an inner decoded stream, comprising an erasure marker for performing an erasure marking process on the inner decoded stream based on the burst error indicator to generate an erasure indicator corresponding to the inner decoded stream. An outer decoder then decodes the inner decoded stream with reference to the erasure indicator to generate the receiver output.

Abstract: The present invention relates to a receiver device and method of detecting a block length of a data block in a data network, wherein a respective theoretical maximum value for a metric of a decoding operation is calculated for each of a plurality of candidate block lengths, and the calculated respective theoretical maximum value is compared to a respective actual value of the metric obtained for each of the plurality of candidate block lengths by the decoding operation. The candidate block length with the highest ratio between the respective actual value and the respective theoretical maximum value is then selected from the plurality of candidate block lengths to determine the block length of the data block.

Abstract: Provided is a transmission device which improves the error rate characteristic upon decoding when performing error correction encoding by using a self-orthogonal code or an LDPC-CC in a communication system using a communication path having a fading fluctuation, multi-value modulation, or MIMO transmission. In the transmission device, the self-orthogonal encoding unit (110) encodes a self-orthogonal code having a constriction length K and an interleave unit (130) rearranges a code word sequence so that the same modulation symbol includes an information bit of a moment i and a non-correlated bit of the information bit of the moment i in a multi-value modulation unit (150).

Abstract: A decoding device allowing a high-speed decoding operation. In a decoding section (215), if a degree of a check equation by a check matrix is D and the relationship between the check equation of the j+first row of the check matrix and the check equation of the jth row is shifted by n-bit, row processing operation sections (405#1 to 405#3) and column processing operation sections (410#1 to 410#3) perform the operation of a protograph in which the columns of the check matrix are delimited for each “(D+1)×N (N: natural number),” and the rows of the check matrix are delimited for each “(D+1)×N/n,” and formed as the processing unit of the row processing operation and column processing operation.

Abstract: The present invention relates to channel decoding and provides ways and means for improved channel decoding of data frames. The frame has been channel encoded and transmitted to a receiver. The frame includes a part with information that is unknown to the receiver and another part with information for which the receiver generates at least one data hypothesis predicting its information content. The receiver performs a hypothesis-based decoding of the received encoded frame, wherein the at least one data hypothesis is used to improve a probability of successful decoding. The invention may advantageously be used to improve decoding of frames containing short control messages with fill bits, e.g. acknowledgement messages.

Abstract: A receiver with capability of correcting error is disclosed. A soft slicer generates quantized data and associated soft data. A decoder with error recovery generates decoded quantized data and a soft sequence, and is capable of correcting one bit of the quantized data. A serial-to-parallel (S/P) converter with code corrector generates parallel data, and is capable of correcting two bits of de-scrambled data bits.

Abstract: Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword.

Abstract: A multiple-input multiple-output (MIMO) transmitter including a scrambler and a forward error correction encoder. The scrambler is configured to receive user data and generate scrambled data in response to the user data. The forward error correction encoder is configured to generate encoded data, in response to the scrambled data, using a low density parity check (LDPC) matrix, wherein the LDPC matrix is derived from a specified base matrix.

Abstract: A decoding device which performs error correction decoding of encoded data formed from a combination of an outer code for first error correction and an inner code for second error correction is disclosed. The decoding device has: a demodulator for creating a data series of likelihood information values; a second error correction decoder for creating a hard decision value series by executing repetitive decoding for the second error correction based on the likelihood information values; and a first error correction decoder for detecting a lost bit in the hard decision value series and creating an erasure flag indicating the position of the detected lost bit.

Abstract: Techniques for generating soft values for parity bits in a convolutional decoding process are disclosed. An exemplary method comprises, for each of at least one iteration in at least one soft-input soft-output decoder, calculating intermediate probability values for each possible transition between a first plurality of candidate decoder states at a first time and a second plurality of candidate decoder states at a second time. Two or more partial sums are then computed from the intermediate probability values, wherein the partial sums correspond to possible combinations of two or more systematic bits, two or more parity bits, or at least one systematic bit and at least one parity bit. Soft values, such as log-likelihood values, are then estimated for each of at least one systematic bit and at least one parity bit of the received communications data corresponding to the interval between the first and second times, based on the partial sums.

Abstract: A technique for decoding low-density parity check codes includes performing a combined check node and variable node calculation. Decoding is initialized using channel likelihood values estimated from a received physical signal. The decoding iteratively updates the variable nodes. Performing a combined check node and variable node calculation can enable reduced memory usage and faster convergence for the decoder.

Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.

Abstract: A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.

Abstract: A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255,239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.

Abstract: Systems, devices and techniques for soft-in, soft-out (SISO) decoding can include accessing initial soft information on a series of data units received over a communication channel, using a cyclic graphical model to represent a coding scheme associated with the received data units, obtaining cycle-free graphical models for a plurality of second conditions allowable by the coding scheme, and generating soft-out decision information by using information that includes the obtained cycle-free graphical models and the initial soft information. The number of obtained cycle-free graphical models can be less than a total number of conditions associated with the cyclic graphical model. Soft decision information can include confidence levels for each data unit.

Abstract: A decoding system for use with different degree parity constraint nodes and highly parallel processing operates by passing messages to variable nodes based on updated states of first and second check nodes, processing messages from the variable nodes and updating states of first and second check nodes in a decoder with Z processors that operate in parallel, further processing the updated state information for the second check nodes to coordinate the states of N=Z/z sets of second check nodes, where z is the number of bits associated with the second check nodes, and repeating the process utilizing the coordinated states of the second check nodes as the updated states of the second check nodes.

Abstract: A method for decoding of multiple wireless signals by a chase combining hybrid-automatic-repeat-request CC-HARQ receiver includes demodulating wireless signals received from respective mobile sources using an effective channel matrix and decision statistics; updating log-likelihood-ratios LLRs and decoding the received codewords using the corresponding updated LLRs; determining set of correctly decoded codewords using a cyclic redundancy check; updating the effective channel matrix and decision statistics responsive to the step of determining; and resetting the effective channel matrix and decision statistics in the event that the number of decoding errors for a codeword exceeds its maximum limit after storing the updated LLRs of all remaining erroneously decoded codewords for which the number of decoding errors is below the respective maximum limit.