Abstract: A method and apparatus for selecting interleaver sizes for turbo codes is provided herein. During operation information block of size K is received. An interleaver size K? is determined that is related to K?, where K? from a set of sizes; wherein the set of sizes comprise K?=ap×f, pmin?p?pmax; fmin?f?fmax, wherein a is an integer and f is a continuous integer between fmin and fmax, p takes integer values between pmin and pmax, a>1, pmax>pmin, pmin>1. The information block of size K is padded into an input block of size K? using filler bits, if needed. Encoding is performed using the original input block and the interleaved input block to obtain a codeword block using a turbo encoder. The codeword block is transmitted through the channel.

Abstract: Disclosed are a wireless transmission device, wireless receiving device, and method for transmitting encoded data with which power consumption can be reduced at the receiving end in accordance with reception conditions, while resource-saving is maintained by employing an erasure correcting code (ECC).

Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract: The present general inventive concept relates to a solid state drive and a method of controlling an error thereof. A flash translation layer includes a parity managing module to correct errors. A block address of a storage medium including error data that can be recovered is managed through the parity managing module. Parity data of a block including error data is generated through the parity managing module. The generated parity data is managed through the parity managing module. The generated parity data can be stored in an assigned area of the storage medium. When data of a block managed by the parity managing module is not recovered by an error correction code unit, error data is recovered with reference to the generated parity data.

Abstract: A system and method for providing fault detection capability is provided which comprises a first node (2). The first node (2) comprises a first processing subsystem (5) generating data (14) to be transmitted. The first node (2) has a fault supervisor unit (13) adapted to gather and process fault indications arising in the first node (2). The first processing subsystem (5) and the fault supervisor unit are both integrated in the first node (2). The first node (2) is structured such that, when no fault indications are detected by the fault supervisor unit (13), the fault supervisor unit (13) provides a first key (15) as a validity key, and, when at least one fault indication is detected by the fault supervisor unit (13), the fault supervisor unit (13) provides a second key (16) as the validity key, and the data (14) to be transmitted are encrypted by overlaying the respective validity key (15; 16) on the data.

Abstract: An apparatus, system, and method are disclosed for determining the location of intermediate CRC in a data stream sent from a channel subsystem to a control unit of an I/O processing system. A CRC locating module determines the location of at least one intermediate CRC in a transport data information unit. A CRC offset module determines a CRC offset of the at least one intermediate CRC. The CRC offset is a value identifying the difference between the location of the at least one intermediate CRC and the location of the first byte of user data in the transport data information unit. An offset block creation module creates a CRC offset block which includes a CRC offset value for each of the at least one intermediate CRC within the transport data information unit and a transmission module transmits the COB to a control unit in the I/O processing system.

Abstract: In order to correct errors of a first page on one plane in a two-plane NAND flash memory, use data of a second page on another plane to mix the encoding and leverage the error correction code of the first page. Each of the error correction codes of the first page and the second page is divided into an inner correction code and a cross correction code. The inner correction codes are used to correct errors of their own pages and the cross correction codes are used to correct errors of two distinct groups, grouped from the even and odd bytes of the two pages respectively. The second page, with fewer errors, is therefore used to enhance the correcting ability of the first page, without lengthening the error correction code of the first page.

Abstract: A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data.

Abstract: A transmitting-side device and a receiving-side device are connected to each other with a parallel bus that carries transmit data and an error-correcting code based on this transmit data in parallel. The transmitting-side device includes a signal inversion unit for inverting a signal to be sent to the parallel bus. The receiving-side device includes a signal inversion unit for inverting a received signal from the parallel bus, and an error detection unit for performing error detection and error correction based on a signal output from the signal inversion unit. The signal inversion unit of the transmitting-side device inverts a signal to be sent to all bus lines of the parallel bus and the signal inversion unit of the receiving-side device inverts the signal received from the all bus lines, which enables the error detection unit to perform error check on the parallel bus.

Abstract: It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed using the decoder and the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed using the decoder and the data associated with the decoder.

Abstract: In a Redundant Array of Independent Discs (RAID) type memory, dual parities P and Q are generated by a dual XOR engine that performs a plain XOR operation for parity P and a weighted XOR operation for parity Q. The plain and weighted XOR operations may be performed in a single pass.

Abstract: Optimizations for data transmission may be provided. A portion of a data block may be read into a batch by a read thread on a first server. The batch may be passed to a transmission thread. The transmission thread may then transmit the first batch to a second server while the read thread asynchronously reads a second portion of the data block into another batch.

Abstract: A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.

Abstract: In one embodiment, upstream transmission throughput in a cable network is markedly increased by moving up the US/DS frequency split by approximately an order of magnitude to a few hundred MHz. Additional transceivers (carriers) may be implemented to take advantage of the broader spectrum. A block of multiple upstream carriers (FIG. 2A) are associated to form a single logical upstream providing a high-bandwidth, in-order packet stream. The carriers have a common start time (704), pursuant to a single MAP message, and operation synchronously to transmit an upstream transmission frame (250). They may use OFDM or discrete carriers. A convergence layer (350) assembles the data from all of the upstream channels (320,322,324) for presentation to the MAC layer logic (308,310) as a single, serial, high-speed transmission from the CM.

Abstract: In a particular embodiment, at a controller coupled to a memory array, a method includes receiving an indication that a first group of data bits read from the memory array includes errors that are uncorrectable by an error correction coding (ECC) engine. A count of the first group of data bits having a particular bit value may be compared to a prior count of data bits having the particular bit value. In response to determining that the count exceeds the prior count, a bit of the first group of data bits that has the particular bit value and that corresponds to a same memory cell as a corrected data bit of a second group of data bits is identified. A value of the identified bit of the first group may be changed to generate an adjusted group of data bits. The adjusted group of data bits may be provided to the ECC engine.

Abstract: A method of decoding a coding pattern disposed on or in a substrate. The method comprises the steps of: (a) operatively positioning an optical reader relative to a surface of the substrate; (b) capturing an image of a portion of the coding pattern, the coding pattern comprising a plurality of square tags of length/identifying two-dimensional location coordinates; and (c) sampling and decoding x-coordinate data symbols within the imaged portion and y-coordinate data symbols within the imaged portion. The imaged portion has a predetermined diameter and is guaranteed to contain sufficient data symbols from each of the Reed-Solomon codes so that symbol errors are correctable in each of the codes during the decoding.

Abstract: A substrate having a coding pattern disposed thereon or therein. The coding pattern comprises a plurality of macrodots encoding first and second Reed-Solomon data symbols. Each first Reed-Solomon data symbol is represented by d macrodots, each of the d macrodots occupying a respective position from a plurality of predetermined possible positions p within a first symbol layout, the respective positions of the d macrodots representing one of a plurality of possible data values. Each second Reed-Solomon data symbol is represented by d macrodots, each of the d macrodots occupying a respective position from a plurality of predetermined possible positions p within a second symbol layout which is different than the first symbol layout, the respective positions of the d macrodots representing one of a plurality of possible data values.

Abstract: An electronic device is described which receives data from a transmitting device via a communications channel. The electronic device comprises digital processing circuitry arranged to process the data received via the communications channel to generate output data, error detection circuitry arranged to detect errors in the output data, and monitoring circuitry arranged to monitor the quality of digital processing conducted by the digital processing circuitry and generate digital performance data indicative of the monitored quality of digital processing. The electronic device also comprises control circuitry responsive to error information comprising errors detected by the error detection circuitry and the performance data generated by the monitoring circuitry to modify the operation of one or both of the transmitting device and the electronic device.

Abstract: A wireless communication terminal having a plurality of antennas with a variable relative distance includes a decoder for iterative decoding of reception signals including an error-correcting code received by the plurality of antennas) and a control unit for controlling an iteration count of decoding by the decoder in accordance with a distance between the antennas detected by an antenna distance detection unit for detecting the distance between the plurality of antennas.

Abstract: Low density parity check (LDPC) decoders are described utilizing a sequential schedule called Zigzag LBP (Z-LBP), for a layered belief propagation (LBP) architecture. Z-LBP has a lower computational complexity per iteration than variable-node-centric LBP (V-LBP), while being simpler than flooding and check-node-centric LBP (C-LBP). For QC-LDPC codes where the sub-matrices can have at most one “1” per column and one “1” per row, Z-LBP can perform partially-parallel decoding with the same performance as C-LBP. The decoder comprises a control circuit and memory coupled to a parity check matrix. Message passage is performed within Z-LBP in a first direction on odd iterations, and in a second direction on even iterations. As a result, a smaller parity check matrix can be utilized, while convergence can be more readily attained. The inventive method and apparatus can also be implemented for partially-parallel architectures.

Abstract: Disclosed is communication error monitoring system and method thereof. In the present disclosure, a master lower-level device, at least one or more slave lower-level devices, and an upper-level monitoring unit are inter-connected via Ethernet, wherein the upper-level monitoring unit receives information of lower-level devices determined as with communication error from the master lower-level device to request and collect necessary data with the slave lower-level devices except for the lower-level devices with the communication error through Ethernet. And thus, a communication delay unnecessary of an entire power system is eliminated and a real time response and stability of a system is enhanced.

Abstract: A digital television (DTV) transmitter and a method of processing data in the DTV transmitter are disclosed. A pre-processor pre-processes the enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded enhanced data. A data formatter generates enhanced data packets including the pre-processed enhanced data and for inserting known data to at least one of the enhanced data packets. A first multiplexer multiplexes the enhanced data packets with main data packets including the main data. An RS encoder RS-codes the multiplexed main and enhanced data packets, the RS encoder adding systematic parity data to each main data packet and adding RS parity place holders to each enhanced data packet. And, a data interleaver interleaves the RS-coded main and enhanced data packets, wherein a known data sequence is included in every Nth enhanced data segment outputted from the data interleaver.

Abstract: Methods and apparatus for compressing data for network transport in support of continuous availability of applications are described. One computer-implemented method of compressing data includes receiving a current instance of data in an input buffer. A candidate chunk of data is selected from the input buffer. A signature hash is computed from a signature length range of data within the candidate chunk. A matching dictionary entry having a matching signature hash from a multi-tiered dictionary is identified. The matching dictionary entry prospectively identifies a location of a prior occurrence of a selected range of consecutive symbols including the signature length range of data within at least one of the current instance of data and a prior instance of data in the input buffer. A dedupe processed representation of the instance of data is formed wherein a dedupe item is substituted for the selected range of consecutive symbols if the selected range is verified as recurring.

Abstract: According to one aspect of the teachings presented in this document, a wireless communication receiver implements a form of joint detection that is referred to as “fast joint detection” (FJD). A receiver that is specially adapted to carry out FJD processing provides an advantageous approach to joint detection processing wherein the number of computations needed to produce reliable soft bits, for subsequent turbo decoding and/or other processing, is significantly reduced. Further, the algorithms used in the implementation of FJD processing are particularly well suited for parallelization in dedicated signal processing hardware. Thus, while FJD processing is well implemented via programmable digital processors, it also suits applications where high-speed, dedicated signal processing hardware is needed or desired.

Abstract: Provided are a method of configuring a protocol header in a wireless communication system, and a communication apparatus and method using the protocol header configuration method. The protocol header configuration method may include: configuring a variable length physical layer (PHY) header and a fixed length PHY header; encoding the fixed length PHY header according to a first coding scheme; generating a Header Check Sequence (HCS) to check an error regarding a combination of the fixed length PHY header, the variable length PHY header, and a Media Access Control (MAC) header; scrambling the MAC header and an HCS to generate a scrambled MAC header and HCS; and encoding the variable length PHY header and the scrambled MAC header and HCS according to a second coding scheme.

Abstract: An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.

Abstract: A system detects an error in a network device that receives data via a group of data streams. The system receives a data unit, where the data unit is associated with at least one of the streams and a sequence number for each of the associated streams. The system determines whether each sequence number associated with the data unit is a next sequence number for the corresponding stream, and detects an error for a particular stream when the sequence number for that stream is not a next sequence number.

Abstract: Disclosed is a novel cooperative communication strategy jointly using symbol-level random network coding and hierarchical modulation in order to effectively minimize packet error rate in error prone wireless networks. The source (or sender) broadcasts random network coded symbols with hierarchical modulation to the relays and the destination (or receiver). In following time slots, the relays, which have successfully decoded the original packet, transmit additional random network coded symbols to the destination. By applying the present disclosure into a multi-hop relay consumer device network, which comprises a set of consumer devices, error free transmission with high efficiency can be achieved.

Abstract: A method and apparatus for determining the reliability of decoded data in a communication system. The method includes calculating a total sum of absolute values corresponding to Log Likelihood Ratio (LLR) values of received data, generating a first value obtained by multiplying the total sum of the absolute values by a predetermined threshold value, performing iterative decoding with respect to the LLR values of the received data, generating a survived path metric value having a maximum value among all path metric values as a decoded result and generating decoded data, comparing the first value with the survived path metric value, and determining whether the decoded data has suitable reliability according to the compared result.

Abstract: A method of reading and correcting data within a memory device that includes reading each data bit of a data word using a plurality of reference cells corresponding to each data bit, performing error detection on the read data bits, and correcting a read data bit when an error is detected using error correction code (ECC) and writing each corresponding reference cells to an original memory state thereof.

Abstract: A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting are preformed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization is effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization.

Abstract: A digital communication system, having a transmitter to transmit a digital signal; and a receiver to receive the digital signal; wherein the digital signal utilizes a 16APSK system, and the signal is bit-mapped using gray mapping, and bits of the digital signal are ordered based on the values of a log likelihood ratio from a communications channel.

Abstract: A digital broadcasting system and a data processing method are disclosed. A receiver receives a broadcast signal including mobile service data and main service data. A known data detector detects known data from the broadcast signal. An equalizer performs channel equalization on the mobile service data received by means of the detected known data. An RS frame decoder acquires an RS frame from the channel-equalized mobile service data. A management processor extracts a Generic Stream Encapsulation (GSE) packet from a GSE Base Band (BB) constructing one row of the RS frame, and calculates an IP datagram from the extracted GSE packet. A presentation processor displays broadcast data using data contained in the calculated IP datagram.

Abstract: A system and method for processing a block Low Density Parity Check (LDPC) code are provided. The system includes, a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part including a first section (B) including a plurality of first permutation matrices, a second section (D) including a second permutation matrix, a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, and a fourth section (E) including a fourth permutation matrix.

Abstract: In one embodiment, systems and methods of operating a SOVA system is disclosed that comprises determining the start and stop values for a trellis tree and using the start and stop values to determine the initial states of a plurality of branches within the trellis tree.

Abstract: A data transmitter and receiver for improving a data rate, and more particularly, to an apparatus and method of transmitting and receiving an orthogonal frequency division multiplexing (OFDM) symbol in which a pilot signal is added to a data signal is provided.

Abstract: Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed.

Abstract: A method for dividing a total number of decoders among decoder queues of codewords of different sizes, the codewords transmitted on return communication links from data terminals to a gateway of a satellite communications system, includes for each of K groups, allocating a respective number of decoders dedicated to decoding codewords of a particular size, where K is a number of different sizes of codewords, and the respective number of decoders is allocated from the total number of decoders and allocated in proportion to current offered load of codewords of the particular size.

Abstract: A method and system for setting a variable forward error correction overhead in an optical transport network frame for an optical link at a node are disclosed. In one embodiment, a method includes selecting a forward error correction overhead, signaling an optical node the selected forward error correction overhead, and setting the forward error correction overhead in the optical network transport frame for use in transmission of data over the optical link. In one embodiment, the forward error correction overhead is complementary to the data payload to maintain total transmission rate.

Abstract: The invention discloses an error-correcting apparatus for decoding an input signal by using a Viterbi algorithm to generate a Viterbi-decoded signal, including an erasure unit and a decoder. The erasure unit is configured to generate at least one logic signal according to at least one path metric difference of path metrics in the Viterbi algorithm, and generate erasure information, wherein the erasure information indicates data reliability of at least one location of the Viterbi-decoded signal. The decoder is configured to decode the Viterbi-decoded signal according to the erasure information.

Abstract: A relay station and a wireless communication system wherein novel retransmission control is achieved in cases when a TTI-bundling technique and a relay technique are used in communication between a terminal and a base station. A relay station (300) relays wireless communication between a terminal that transmits a wireless signal in which code words obtained by encoding a single set of transmission data have been mapped to a TTI bundle consisting of a plurality of TTIs, and a base station that receives the wireless signal and transmits error detection information related to the code word transmitted in the tail TTI of the TTI bundle. At the relay station (300), a control information generating unit (309) transmits error detection information related to the code word transmitted in the front TTI of the TTI bundle.

Abstract: Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying sizes when enacting block decoding of concatenated convolutional codes. The memory device efficiently minimizes space while enabling a higher throughput of the turbo decoder by enabling a plurality of memory banks of equal size. The number of memory banks may be limited by the amount of unused space in the memory banks, which may be a waste of area on an IC chip. Using the address associated with the maximum value of the data block, the memory may be split into a plurality of memory blocks according to the most-significant bits of the maximum address, with a number of parallel SISO decoders matching the number of memory banks. This may enable higher throughput while minimizing area on the IC chip.

Abstract: A device and a method for optimally adjusting transmitter parameters are provided to optimize transmission performance of a digital signal system. The device comprises an error signal analyzing unit and a step length adjustment unit which are connected in signal with each other; the error signal analyzing unit analyzes an error signal and makes a determination to carry out a transmitter parameter adjustment operation; the step length adjustment unit calculates and determines an adjustment direction and an adjustment step length of the transmitter parameter; and a transmitter parameter adjusting unit carries out operations of direction adjustment and step length adjustment of the transmitter parameter according to the result of the determination.

Abstract: Methods and apparatus relating to retry based protocol with source/receiver FIFO (First-In, First-Out) buffer recovery and anti-starvation mechanism to support dynamic pipeline lengthening for ECC error correction are described. In an embodiment, upon detection of an error, a portion of transmitted data is stored in one or more storage devices before retransmission. Other embodiments are also described and claimed.

Abstract: A method of implementing and manufacturing a cyclic redundancy check circuit for a multi-channel communication system. The method includes creating a generation expression that generates cyclic redundancy check (CRC) bits that satisfies a cyclic redundancy check polynomial of a mono-channel serial communication system with respect to a first point in time, creating a generation expression with respect to points in time that are sequentially delayed as much as the number of multi-channels from the first point in time by applying each point in time to the generation expression, and embodying a circuit corresponding to the generation expression with respect to the most delayed point in time among the created generation expressions. The CRC circuit corresponding to the generation expression will have more modulo-2 adders (e.g., XOR gates) than the number of non-zero coefficients in the selected CRC polynomial.

Abstract: Systems and methods that implement compress-forward (CF) coding with N-PSK modulation for the relay channel are disclosed, where N is greater than or equal to two. In the CF scheme, Wyner-Ziv coding is applied at the relay to exploit the joint statistics between signals at the relay and the destination. Quantizer design and selection of channel code parameters are discussed. Low-density parity check (LDPC) codes are used for error protection at the source, and nested scalar quantization (NSQ) and irregular repeat accumulate (IRA) codes for Wyner Ziv coding (or more precisely, distributed joint source-channel coding) at the relay. The destination system decodes original message information using (a) a first signal received from the source in a first interval and (b) a second signal that represents a mixture of transmissions from the source and relay in the second interval.

Abstract: A system, method and computer readable medium for performing a first read attempt of multiple codeword portions while using a first read threshold candidate to provide multiple first read results, wherein the multiple codeword portions are stored in multiple flash memory cells; calculating a first read threshold candidate error correction decoding based score; wherein the calculating comprises error correction decoding of the multiple first read results; performing a second read attempt of the multiple codeword portions while using a second read threshold candidate to provide multiple second read results; calculating a second read threshold candidate error correction decoding based score; wherein the calculating comprises error correction decoding of the multiple second read results; and selecting a first read threshold out of the first and second read threshold candidates based on a relationship between the first and second read threshold candidate error correction decoding based scores.

Abstract: Disclosed is a wireless communication device capable of always obtaining the optimum error rate characteristic and of keeping the number of retransmissions to a minimum for IR-based HARQ which uses LDPC encoding in the error correction encoding. With the device, an RV control unit (102) controls the system check bit transmission sequence such that all of the system check bits included in an LDPC code word are transmitted with the first transmission in sequence from the smallest column weight of a check matrix, and controls the transmission sequence of multiple RVs such that multiple RVs comprising only system check bits are transmitted in sequence from the smallest column weight when an RV is transmitted additionally after all of the parity bits included in an LDPC code word have been transmitted.

Abstract: According to one embodiment, a server apparatus includes a judgment module and a controller. The judgment module judges a communication connection state of the terminal that made the notification, when a message indicating that error reception of an unnecessary packet is detected by the terminal. The controller executes a process of preventing packet error distribution according to the communication connection state judged by the judgment module.

Abstract: Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.