Abstract: A data transmission apparatus in a wireless communication system includes: a data field generation unit configured to generate a data field for transmitting data; a signal field generation unit configured to generate a signal field for transmitting information on the data field; and a transmission unit configured to transmit a data packet containing the data field and the signal field. The signal field includes a rate bit, a reservation bit, a length bit, a parity check bit, and a tail bit, and the data transmission apparatus transmits a check bit for checking whether the signal field is normal or not through two or more bits of the bits of the signal field.

Abstract: An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p-k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of turbo decoding. For example, a device may include a turbo decoder to decode a turbo-encoded input according to a turbo code, the turbo-encoded input including a plurality of soft-decision information-bit values and a plurality of soft-decision parity-bit values corresponding to the soft-decision information bit values, wherein the turbo decoder is to output a plurality of extrinsic soft-decision parity-bit values corresponding to the plurality soft-decision parity-bit values. Other embodiments are described and claimed.

Abstract: A channel coding method in a communication system using a Low-Density Parity-Check (LDPC) code. The channel coding method includes determining a degree distribution for a plurality of column groups of an information part and a plurality of column groups of a parity part; determining degrees for the plurality of column groups of the information part based on the degree distribution; determining a shortening order based on the degrees for the plurality of column groups of the information part; generating a parity check matrix based on the shortening order; and performing coding using the generated parity check matrix.

Abstract: It is possible to provide a terminal device, a terminal device control method, and a recording medium which enables an error correction without modifying hardware. The terminal device receives a data stream formed in the NAL Unit by a hard decoder based on the H.264 standard. The terminal device includes error correction means which analyzes data encoded in the data stream by software and performs an error correction before inputting the data to the hard decoder.

Abstract: A method involves receiving an LDPC coded bitstream and demultiplexing the received LDPC coded bitstream using an optimized demultiplexer, the optimized demultiplexer being designed by: substituting Q levels of a constellation mapper by Q parallel binary erasure channels; optimizing a density evolution of erasure probability over said binary erasure channels for a plurality of demultiplexer offsets; and identifying from the plurality of demultiplexer offsets those with a minimum number of check node decoder collisions.

Abstract: Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.

Abstract: A method and apparatus for generating a Cyclic Redundancy Check (CRC) encoded message in a communication system are provided. The method includes generating the message, generating a first CRC for the message, generating a second CRC for the message, scrambling the first CRC by a first bit sequence of the message, and scrambling the second CRC by a second bit sequence of the message. The apparatus includes a message generator, a first CRC encoder, and a second CRC encoder. The message generator generates a message. The first CRC encoder generates a first CRC for the message, and scrambles the first CRC by a first bit sequence of the message. The second CRC encoder generates a second CRC for the message, and scrambles the second CRC by a second bit sequence of the message.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: Provided is a memory controller that generates Error Correction Code (ECC) information for data based on a required reliability level predetermined based on a type of the data, that computes an ECC code for the data based on the ECC information, and that records the ECC code in a memory based on the ECC information.

Abstract: In a communication system, a transmitter device transmits data to a receiver device for performing error-correcting decoding processing by combining received data and retransmitted data. The transmitter device selects one of a first set of schemes of an M number of modulation and coding schemes as a modulation and coding scheme (MCS) of first data according to communication quality information obtained from the receiver device when the first data is initially transmitted, and selects one of a second set of schemes of an N number of MCSs (N<M) according to the communication quality information when the first data is retransmitted. The transmitter device generates a control signal including information indicating the selected MCS so that an amount of information of the MCS selected from the second set of schemes is less than an amount of information of the MCS selected from the first set of schemes.

Abstract: A trellis encoding device includes a plurality of trellis encoders to perform trellis-encoding of a transport stream into which a supplementary reference signal (SRS) has been inserted, and performs a memory reset in a region that precedes an SRS; and a parity compensation unit to compensate for parities of the transport stream in accordance with values stored in memories included in the trellis encoders. The plurality of trellis encoders may be implemented in diverse types. The trellis encoding device can perform a memory reset selectively using the stored value of the memory and the inverted value thereof, or selectively using the stored value of the memory and a fixed value. By properly resetting the memory in processing the transport stream into which the SRS has been inserted, DC offset can be reduced.

Abstract: A method for adapting error protection in a communication network includes: a step of determining periods of time that are homogeneous as regards the distribution law of losses over the network, a step of classifying the homogeneous periods of time into at least two classes, on the basis of information representing losses over the network and/or representing a corresponding level of protection, during these periods of time, a step of determining a probability of alternation between two of said classes, and a step of selecting a protection strategy on the basis of said probability of alternation. A method of detecting transition between two states of a communication network corresponding to different loss rates of sent data includes: a step of determining a probability of transition, and a step of determining the existence of a transition on the basis of said probability.

Abstract: A parallel CAM that can perform a parity check fast at the search time. The CAM searches all addresses at the same time and determines whether or not the same data as input data is stored. The CAM includes a write search parity generator for generating parities of n-bit write and search data, a plurality of memory locations corresponding to a plurality of addresses, and a NAND circuit for activating a parity error signal if at least one of valid parity match signals outputted from the memory locations is inactive. Each memory location includes n data memory cells, a parity memory cell, an exclusive OR circuit for judging whether or not the parities match, and activating a parity match signal, if they are matched, and a NAND circuit for validating the parity match signal using a data match signal.

Abstract: An apparatus and a method for transmitting and receiving control information in a Multiple Input Multiple Output (MIMO) system are provided. A method of a base station for transmitting control information to a terminal in the MIMO system includes transmitting first control information for every transmission mode except for a Multiple-User (MU)-MIMO mode, to the terminal over a control channel of a subframe, and transmitting second control information for the MU-MIMO mode to the terminal over a data channel of the subframe.

Abstract: Various embodiments of the present invention provide systems and methods for decoding data. As an example, a data processing circuit is disclosed that includes a multi-tier decoding circuit having a first tier decoding circuit operable to decode portions of an encoded data set exhibiting low row weight, and a second tier decoding circuit operable to decode portions of an encoded data set exhibiting high row weight.

Abstract: In a communication system, a transmitter receives an input bit, and in response thereto, generates at least an n-bit codeword, each bit of which is generated by a respective one of n generators of which m are exactly the same, m being greater than n/2. A receiver comprises: m detectors, each adapted to receive the bit generated by a respective one of the m generators, and provide a respective one of m partial detection signals if a strength of the received bit exceeds a predetermined minimum threshold; and a majority logic element adapted to receive each of the m partial detection signals, and provide an output bit indicative of the input bit only if more than m/2 of the received m partial detection signals exceeds the minimum threshold.

Abstract: Various embodiments of the present invention provide systems and methods for encoding data. As an example, a data encoding circuit is disclosed that includes a first stage data encoder circuit and a second stage data encoder circuit. The first stage data encoder circuit is operable to provide a first stage output. The first stage data encoder circuit includes a first vector multiplier circuit operable to receive a data input and to multiply the data input by a first sparse matrix to yield a first interim value. The second stage encoder circuit includes a second vector multiplier circuit operable to multiply the first stage output by a second sparse matrix to yield a second interim value.

Abstract: According to one embodiment, a signal processing device comprises a first waveform equalizer, a second waveform equalizer, a first Viterbi decoder, a second Viterbi decoder. The first and the second waveform equalizers equalize a waveform of the input signal according to first and second partial response characteristics and output first and second partial response signals. The first and second Viterbi decoders decode the first and the second partial response signals by means of Viterbi decoding process. The input signal is reproduced based on an output of the first Viterbi decoder and an output of the second Viterbi decoder.

Abstract: In one embodiment, an LDPC decoder has a controller and an extrinsic log-likelihood (LLR) value generator. The extrinsic LLR value generator is selectively configurable to operate in either (i) a non-averaging mode that updates extrinsic LLR values without averaging or (ii) an averaging mode that updates extrinsic LLR values using averaging. Initially, the extrinsic LLR value generator is configured to generate non-averaged extrinsic LLR values, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged extrinsic LLR values. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) the extrinsic LLR value generator is configured to generate average extrinsic LLR values, and (iii) the decoder attempts to recover the correct codeword using the average extrinsic LLR values. Averaging the extrinsic LLR values may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets.

Abstract: Disclosed is an encoding method to change an encoding rate of an erasure correcting code, while decreasing a circuit scale of an encoder and a decoder. 12k bit (wherein k represents a natural number) which is an encoding output using LDPC-CC with an encoding rate of ½, and comprises information and parity, is defined as one cycle. From the one cycle, only the information is arranged in the output order of the encoding output to obtain 6k bit information X6i, X6i+1, X6i+2, X6i+3, X6i+4, X6i+5, . . . , X6(i+k?1) X6(i+k?1)+1, X6(i+k?1)+2, X6(i+k?1)+3, X6(i+k?1)+4, and X6(i+k?1)+5. Known information is inserted, in 3k pieces of information (Xj) among the 6k bit information, so that when 3k pieces of mutually different j is divided by 3, there is a remainder of 0 regarding k pieces, there is a remainder of 1 regarding k pieces, and there is a remainder of 2 regarding k pieces, to thereby obtain the parity from the information containing the known information.

Abstract: A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably, applying the first decoder consumes less power and is faster than applying the second decoder. Data are ported by encoding the data as a codeword, exporting the codeword to a corrupting medium, importing a representation of the codeword, and applying a first decoder to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword.

Abstract: Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values.

Abstract: In one embodiment, the invention is a method of transferring data. The method includes receiving a first video data stream at a first machine. The method also includes multicasting the first video data stream in uncompressed and raw form through a network. The method further includes receiving the first video data stream at a second machine. The method also includes playing the first video data stream on the second machine.

Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in QPSK/8PSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.

Abstract: Apparatus having corresponding methods and tangible computer-readable medium embodying instructions executable by a computer to perform the methods comprise: a receiver adapted to receive a signal representing an input code block, wherein the input code block represents information encoded with a (N, K) difference-set cyclic code, wherein the input code block includes N symbols, and wherein the N symbols represent K bits of the information; an estimator adapted to estimate a signal-to-noise ratio of the signal; a raised-threshold majority-logic decoder adapted to decode the input code block according to a raised-threshold majority-logic decoding algorithm when the signal-to-noise ratio does not exceed a first predetermined threshold; and a variable-threshold majority-logic decoder adapted to decode the input code block according to a variable-threshold majority-logic decoding algorithm when the signal-to-noise ratio exceeds the first predetermined threshold.

Abstract: A communication system enabling wireless transmission of messages via packets; and a method of operating the system provides for improved accuracy in the transmission of a message, particularly for overcoming signal distortion associated with the phase changes and varying multipath found in transmissions from the locomotive of a moving train. The maximum benefit of forward-error correction (FEC) with Reed-Solomon (RS) coding is applied for a message payload that is significantly shorter than the fixed length of a packet, with lesser coding being performed with longer payloads.

Abstract: A method of encoding data for transmissions from a source to a destination over a communications channel is provided. The method operates on an ordered set of source symbols and may generate zero or more redundant symbols from the source symbols, wherein data is encoded in a first step according to a simple FEC code and in a second step, data is encoded according to a second FEC code, more complex than the first FEC code. The first FEC code and/or the second FEC code might comprise coding known in the art. These steps result in two groups of encoded data in such a way that a low-complexity receiver may make use of one of the groups of encoded data while higher complexity receivers may make use of both groups of encoded data.

Abstract: Disclosed is a method and system of determining a data block of a RAID level 6 stripe that has corrupted or incorrect data. For each data block of the stripe, a reconstructed data block is created using the other data blocks and the P syndrome data block. The reconstructed data block and the other data blocks are used to create a new Q syndrome data block. The new Q syndrome data block and the stored Q syndrome data block are compared. If the new Q syndrome data block and the stored Q syndrome data block match, the data block is marked as being suspected as having corrupted or incorrect data. This process is repeated for every data block in the stripe. If there is only a single suspected data block, the reconstructed data block is stored as a replacement of the suspect data block in the stripe.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a decoder circuit and a scalar circuit. The decoder circuit is operable to perform a data decoding algorithm by processing at least one decoder message, and the scalar circuit is operable to multiply the decoder message by a variable scalar value.

Abstract: An encoding apparatus derives a bit order based on a puncturing table that specifies different puncturing patterns for different transmission rates. The encoding apparatus then generates an error correcting code from an input information bit string and rearranges the error correcting code in the derived bit order. The error correcting code is punctured by taking a number of consecutive bits from the rearranged error correcting code. The number of bits taken varies depending on the transmission rate. The punctured error correcting code is output to a decoding apparatus, which realigns the code bits according to the transmission rate and the puncturing table, then uses the realigned error correcting code to correct errors in erroneous data. Rearrangement of the error correcting code makes the puncturing process more efficient by avoiding the need to decide whether to take or discard each bit individually.

Abstract: Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. A novel approach is presented for variable modulation encoding of LDPC coded symbols. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis.

Abstract: A receiving apparatus that can prevent beforehand that a portable recording medium is erroneously ejected during examination, and can prevent body cavity image data from being lost and the portable recording medium from being damaged is provided. When an ejection operation of the portable recording medium is detected (step S103: Yes) during a recording operation (step S101: Yes), a warning unit is operated before the portable recording medium is ejected to give a warning to a user so as not to perform the ejection operation (step S105). Accordingly, the portable recording medium can be prevented beforehand from being ejected during the recording operation, thereby preventing body cavity image data from being lost and the portable recording medium from being damaged.

Abstract: A low density parity check (LDPC) encoding method and an LDPC encoder are provided. The LDPC encoding method includes generating a H matrix and a He matrix. The H matrix includes a first section (H1) matrix and a second section (H2) matrix. The He is based on a ratio of the H matrix and a zero matrix to a C matrix and a D matrix. The method further includes generating a H1row matrix columnwise for each of a plurality of input vectors based on the H1 matrix and generating parity vectors for each of the plurality of input vectors based on the H1row matrix.

Abstract: An example method of verifying avionic data includes establishing a first cyclical redundancy check value associated with a data file. The first cyclical redundancy value is established on an aircraft. The method transmits the data file from the aircraft to a ground system. The method receives a second cyclical redundancy check value associated with the data file. The second cyclical redundancy check value is established by the ground system. The method determines the transmitted data file integrity by comparing the first cyclical redundancy check value to the second cyclical redundancy check value. An example aircraft avionic data verification arrangement includes a collector device that assembles avionic data into a data file that is transmittable to a ground system.

Abstract: Embodiments provide a method for determining the number of parity bytes that are added by a Reed-Solomon encoder. The number of parity bytes are equivalent to the error correcting capability of the Reed-Solomon code. The number of parity bytes is based on the payload length or the information block size used in the Reed-Solomon encoder. Other factors may also be used to make this choice.

Abstract: An apparatus and a method for packet error correction in packet-switched networks is provided. Message packets to be transmitted on a network are subdivided into k symbols over GF(q), and the symbols are then encoded by a symbol-level encoder into a codeword of n>k symbols over GF(q). The codeword is transmitted on the network in a plurality of network packets to a symbol-level decoder, which recovers any symbols lost or corrupted in transmission. Encoding at the symbol level increases the amount of data that can be recovered in any single correction operation. The efficiency of the decoding is also enhanced because the location of symbol errors can be determined prior to decoding.

Abstract: A transmitter device (110T) for secure communication includes: an encoder (170) configured to apply a non-systematic error correcting code (NS ECC) to a message, thus producing encoded bits with no clear message bits; and a transceiver (720) configured to transmit the encoded bits over a main channel to a receiver. A method for secure communication includes: encoding a message with an NS ECC to produce an encoded message carrying no message bits in the clear; and transmitting the encoded message over a main channel (120). The NS ECC characteristics result in an eavesdropper channel error probability under a security threshold (320) and a main channel error probability over a reliability threshold (310), whenever an eavesdropper (140) listening on an eavesdropper channel (150) is more than distance Z (220) from the transmitter. Unreliable bits in the encoded bits render the eavesdropper unable to reliably decode messages on the main channel.

Abstract: A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include performing iterative decoding on a demodulated signal to provide a decoded signal, determining whether the iterative decoding is suffering an impairment, and terminating the iterative decoding responsive to the determination of the impairment, otherwise continuing the iterative decoding to provide the decoded signal.

Abstract: Methods and apparatus are provided for computing soft data or log likelihood ratios for received values in communication or storage systems. Soft data values or log likelihood ratios are computed for received values in a communication system or a memory device by obtaining at least one received value; identifying a segment of a function corresponding to the received value, wherein the function is defined over a plurality of segments, wherein each of the segments has an associated set of parameters; and calculating the soft data value or log likelihood ratio using the set of parameters associated with the identified segment. The computed soft data values or log likelihood ratios are optionally provided to a decoder.

Abstract: A transmission device includes a first conversion unit converting first transmission target data into first transmission data formed by N symbol values, with predetermined units of data, based on a first conversion table, a second conversion unit converting first error correction data into first symbol data formed by the a symbol values, based on a second conversion table, a third conversion unit converting second transmission target data into second symbol data formed by the (N-a) symbol values, based on a third conversion table, an addition and generation unit adding the second symbol data to the first symbol data and generating second transmission data formed by the N symbol values, and a transmission unit transmitting a transmission signal formed by the first and second transmission data.

Abstract: A method of managing forward error correction (FEC) initialization and auto-negotiation in ethernet passive optical networks includes receiving FEC data from an optical network unit (ONU), and the optical line terminal (OLT) responds to the ONU with FEC data. Upon receiving data not forward error corrected from an ONU, the OLT responds with data not coded for FEC. Similarly, upon receiving forward error corrected data from the OLT, the ONU responds with forward error corrected data; and upon receiving data not forward error corrected from the OLT, the ONU responds with data not forward error corrected. The communications quality from the ONU is monitored, if the communications quality is not sufficient, the OLT transmits forward error corrected data to the ONU; otherwise, the OLT transmits non-FEC data to the ONU.

Abstract: Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data.

Abstract: Methods and systems for doped rateless retransmission include receiving ratelessly coded symbols. An attempt is made to decode the coded symbols using a processor by creating an associated code graph that represents the structure of the rateless code used by the symbols. If the decoding attempt fails, an input node is selected from the code graph using a metric that gauges the number and degree of connections to the input node based on the code graph structure. The selected input node is then requested for retransmission of the selected input node by a feedback channel.

Abstract: A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include performing iterative decoding on a demodulated signal to provide a decoded signal, receiving information regarding the iterative decoding, and based on the information controlling a number of nodes of the iterative decoder to enable during a next iteration of the iterative decoding.

Abstract: A hard input low density parity check decoder is provided that shares logic between a bit-flipping decoder and a syndrome calculator. The hard-decision decoder decodes one or more error-correcting (EC) codewords and comprises a bit-flipping decoder that flips one or more bit nodes connected to one or more unsatisfied parity checks; and a syndrome calculator that performs a parity check to determine whether the bit-flipping decoder has converged on a valid codeword, wherein the bit-flipping decoder and the syndrome calculator share one or more logic elements. The decoder optionally includes means for updating a parity check equation of each flipped bit. Error-correcting (EC) codewords are decoded by flipping one or more bit nodes connected to one or more unsatisfied parity checks; and updating one or more parity check equations associated with the one or more bit nodes each time the one or more bit nodes are flipped. The parity check equations are updated whenever a bit is updated.

Abstract: In the field of mobile telecommunications, a method for checking a false alarm is provided. In the method, after a user in a Long Term Evolution (LTE) system receives control signaling for scheduling physical resources, Cyclic Redundancy Check (CRC) is performed on the control signaling; and if the CRC is passed, false alarm check is performed on the control signaling according to false alarm check bit(s) and padding bit(s) in the control signaling. An apparatus and a user equipment (UE) for checking a false alarm are also provided. According to the method, the apparatus, and the UE for checking a false alarm, the number of bits participating in the false alarm check is increased, thereby reducing the probability of false alarm occurrence, and improving receiving performance of the control signaling.

Abstract: A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables.

Abstract: To provide a receiving device and a receiving method which achieve iterative decoding regarding concatenated codes containing a convolutional code while suppressing increase in circuit scale, a decoder and an error correcting part iteratively perform decoding and error correction corresponding to a convolutional code on soft-decision inputs corresponding to the received signal sequence. Depending on whether a decoding result matches error corrected decoded data obtained in previous processing or not, penalties are calculated corresponding to branches transiting with the respective decoded results, and a branch metric is calculated by reflecting the calculated penalties as to decrease likelihood ratio of each of the branches to which the penalties are to be added. The obtained branch metric is input to a decoder, thereby reflecting the penalty corresponding to the decoding result.

Abstract: An approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to generate the LDPC coded signal are retrieved from memory. The edge values specify the relationship of bit nodes and check nodes, and are stored within memory according to a predetermined scheme that permits concurrent retrieval of a set of the edge values. A decoded signal corresponding to the LDPC coded signal is output based on the retrieved edge values.