Abstract: The present invention relates to a method for constructing LPDC code check matrix and encoding and decoding devices using the same. The encoding device encodes the inputted binary information and outputs the encoded system code sequence of position transformation. The encoding device comprises: a matrix multiplication module outputting a check sequence p which is obtained through the binary information sequence m multiplied with a matrix; a sorting index module having N memory units storing index values of a sorting table IDX in turn; and a sorting output module for sorting the m and p and outputting a code word c based on the index value stored in the sorting index table. The present invention constructs the LDPC code check matrix using an algebraic structure, obtaining the LDPC code with stable performance. In addition, the encoding and decoding devices of the present invention occupy less memory, which is preferable for optimization of the devices.

Abstract: A method for activating a semi-persistent scheduled (SPS) resource using a user agent (UA) is presented. A downlink (DL) communication may be received by a UA using a physical downlink control channel (PDCCH). The DL communication may include a control message. When the control message is associated with an SPS Cell-Radio Network Terminal Identifier (C-RNTI) of the UA, the method may include retrieving a value of a New Data Indicator (NDI) field. When the value of the NDI field is equal to 0, the method may include inspecting the control message to determine whether the control message indicates an SPS activation. When the control message indicates an SPS activation, the method may include activating an SPS resource identified by the control message.

Abstract: Direct injection of a data to be transferred in a hybrid computing environment that includes a host computer and a plurality of accelerators, the host computer and the accelerators adapted to one another for data communications by a system level message passing module. Each accelerator includes a Power Processing Element (‘PPE’) and a plurality of Synergistic Processing Elements (‘SPEs’). Direct injection includes reserving, by each SPE, a slot in a shared memory region accessible by the host computer; loading, by each SPE into local memory of the SPE, a portion of data to be transferred to the host computer; executing, by each SPE in parallel, a data processing operation on the portion of the data loaded in local memory of each SPE; and writing, by each SPE, the processed data to the SPE's reserved slot in the shared memory region accessible by the host computer.

Abstract: A system and method for transmitting and receiving acknowledgement information are provided. A method for communications device operations includes determining a hybrid automatic repeat request (HARQ) response for each CC in a set of configured CCs, thereby producing a set of HARQ responses, generating an information vector from the set of HARQ responses, encoding the information vector, and transmitting the encoded information vector. A sub-vector of one or more bits selected from the information vector is assigned a fixed vector value independent of HARQ responses for CCs not in a set of CCs when the set of CCs is not empty, where the set of CCs comprises at least one CC whose HARQ response is equal to DTX.

Abstract: Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. Moreover, an error-detection circuit, which is coupled to the encoder circuit, generates and stores error-detection information associated with the set of M symbols, where the error-detection information facilitates subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. Additionally, a receiver circuit receives feedback information from the other circuit. This feedback information includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space.

Abstract: A block-request streaming system provides for improvements in the user experience and bandwidth efficiency of such systems, typically using an ingestion system that generates data in a form to be served by a conventional file server (HTTP, FTP, or the like), wherein the ingestion system intakes content and prepares it as files or data elements to be served by the file server, which might or might not include a cache. A client device can be adapted to take advantage of the ingestion process as well as including improvements that make for a better presentation independent of the ingestion process. In the block-request streaming system, the an ingestion system generates data according to erasure codes and the client device, through various selection and timing of requests for media data and redundant data, can efficiently decode media to provide for presentations.

Abstract: Various embodiments for differentiating between data and stubs pointing to a parent copy of deduplicated data are provided. Undeduplicated data is stored with a first cyclic redundancy check (CRC) seed. A stub pointing to the parent copy of the deduplicated data is stored with a second CRC seed. Subsequent to reading the deduplicated data, the first CRC seed is associated with the undeduplicated data, and the second CRC seed is associated with the stub. A CRC check is performed using one of the first and second CRC seeds. If the CRC check is positive, an I/O operation is allowed to proceed. If the CRC check is negative, an additional CRC check is performed using another one of the first and second CRC seeds.

Abstract: An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability ? in association with each first address, a check node storage section that stores TMEM variables to calculate an external value ? in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units.

Abstract: This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of the NVM can include one or more parity pages that may be distributed at random through the NVM. To identify the page as a parity page, a parity page marker can be included in the metadata of that page. During power-up of the NVM, an address table including the logical-to-physical address mapping of the pages can be created. Pages including a parity page marker, however, can be skipped during the creation of this address table. Additionally, by having two or more parity pages associated with a codeword, an additional layer of protection can be provided for repairing errors in that codeword.

Abstract: A method includes segmenting a first portion of a data block into a plurality of segments that includes a first segment. The data block includes a second portion, different from the first portion, which stores cyclic redundancy check data calculated from data stored in the first portion of the data block. The method also includes calculating cyclic redundancy check data from the first segment, and, translating the calculated cyclic redundancy check data to a location associated with the data block. The method also includes combining the cyclic redundancy check data associated with the first segment and cyclic redundancy check data associated with at least one other segment included in the plurality of segments. The method also includes using the combined cyclic redundancy check data for error detection.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: A receiver and method for HARQ combining of a received codeword in a receiver with a FEC decoder, the method including computing Log Likelihood Ratios (LLRs) of demodulated soft symbols of the received codeword and outputting the LLRs as a-priori soft bits; performing iterative decoding of the a-priori soft bits in a Forward Error Correction (FEC) decoder; outputting a posteriori soft bits of the a priori soft bits of the received codeword from the FEC decoder; and HARQ combining the a posteriori soft bits with a retransmission of the received codeword.

Abstract: Embodiments of the invention provide a packet encoding scheme to ensure unequal error protection to different bits in a packet or in multiple packets. In one embodiment, a method to process bits in a bit stream comprises scrambling the bit stream; separating the scrambled bit stream into a high priority bit stream with an order of high priority bits from left to right and a low priority bit stream with an order of low priority bits from left to right; rearranging the bits by embedding the high priority bits in the low priority bit stream while preserving the two orders, the rearranged bit stream including blocks of bits, each block including one or more high priority bits disposed left of corresponding one or more low priority bits to provide protection for the high priority bits against noise which is at least equal to protection for the low priority bits; and modulating the rearranged bit stream using Gray encoding method to produce an encoded bit stream.

Abstract: A system and method for Viterbi decoding utilizes a general purpose processor with application specific extensions to perform Viterbi decoding operations specified in a Viterbi decoding algorithm stored in memory.

Abstract: A transmitting apparatus generates a first bit stream from a second bit stream by encoding at least a portion of the bits from the second bit stream, generates a code for the second bit stream, and attaches the code to the first bit stream for transmission to a receiving apparatus. A receiving apparatus receive from a transmitting apparatus a first bit stream with a code, generates a second bit stream from the first bit stream by decoding at least a portion of the bits from the first bit stream, computes the code for the second bit stream, and compares the computed code with the code from the first bit stream.

Abstract: Consistent the present disclosure, errored bits are inserted into a data stream, which is carried by an optical signal. The optical signal is transmitted over an optical link that may induce additional errors, i.e., add additional errored bits to the data stream. At the receive end, the optical signal is converted into a corresponding electrical signal that carries the data stream. The data stream is subject to forward error correction (FEC) decoding with an iterative decoder, for example. The iterative decoder decodes the data stream over a number of iterations until both the inserted errored bits and the additional errored bits are corrected. Since the number of inserted bits is known, the number of iterations required to correct the inserted bits is also known (“first iterations”).

Abstract: Techniques relating to a processor including instruction support for implementing a cyclic redundancy check (CRC) operation. The processor may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit configured to receive instructions that include a first instance of a cyclic redundancy check (CRC) instruction defined within the ISA, where the first instance of the CRC instruction is executable by the cryptographic unit to perform a first CRC operation on a set of data that produces a checksum value. In one embodiment, the cryptographic unit is configured to generate the checksum value using a generator polynomial of 0x11EDC6F41.

Abstract: A packet transmission apparatus is provided. The packet transmission apparatus transmits a packet having a limited arrival deadline through a best-effort network. The packet transmission apparatus includes an automatic packet retransmission section to control retransmission of an undelivered packet, a forward error correction coding section to add a redundant packet to a data packet block, and a redundancy determining section to dynamically determine redundancy of the redundant packet based on observed network state information, so that a loss rate after error correction at a receiver achieved by only the retransmission of the undelivered packet satisfies an allowable loss rate after error correction.

Abstract: The error correction capability of block codes can be doubled if error locations are known. Prior art approaches for error location detection always involve adding dedicated redundant data which then are evaluated to yield error location information. The present invention proposes and describes how error location information in the form of clues is derived from given DC control bits that are anyway present in a data stream.

Abstract: The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.

Abstract: The present invention relates to a system and method for enabling a buffer-less or substantially buffer-less core network using a packet-level forward error correction (FEC) coding scheme. The system includes an ingress edge router configured to receive data packets destined to at least one egress edge router via an access link from an end-host. The ingress edge router is connected to the at least one egress edge router via a core network, where the core network is buffer-less or substantially buffer-less. Also, the ingress edge router is configured to apply a forward error correction (FEC) encoding scheme to the data packets at a packet level and transmit the encoded data packets to the core network.

Abstract: A communication system that provides fast and reliable communications. The system is suitable for use in connection with wireless computing devices in which transmission errors may occur because of channel conditions, such as interference. Channel conditions causing transmission errors may be bursty and transient such that the errors temporarily overwhelm an error control code. By combining data received for multiple transmission attempts of a packet that fail error checking or that pass error checking with low reliability, a reliable representation of the packet may be quickly constructed. Though, combining may be omitted when a transmission attempt is received that passes error checking with high reliability.

Abstract: A decoder includes a first decoder configured to iteratively decode input data, accumulate iteratively decoded data in bit units, compare an accumulated value obtained for each bit of the iteratively decoded data with a plurality of reference values, and output decision data and indicator data according to a comparison result. The decoder includes a second decoder configured to perform error correction on a symbol including the decision data according to the indicator data.

Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

Abstract: A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.

Abstract: A method and apparatus perform forward error correction in a wireless communication device in a wireless communication network. Application layer forward error correction (AL-FEC) capability information is transmitted during a capabilities exchange. A set of source packets are reshaped to k equal-sized source symbols. Systematic packets for the source symbols and at least one parity packet is encoded using a single parity check (SPC) AL-FEC code on the k source symbols. A header of each encoded packet includes a parity packet indicator. The encoded packets are processed in a media access control (MAC) layer and a physical (PHY) layer for transmission.

Abstract: Positions holding different bit values between a first code word, which is obtained by coding an information bit sequence based on a coding method utilizing quasi-cyclic codes, and a second code word, which has the close Hamming distance from the first code word and satisfies a parity check of the coding method, are identified. Thereafter, a code word is generated by inserting bit values known to the transmitter and receiver into the identified positions of the information bit sequence and coding the information bit sequence. Upon reception of a signal based on the generated code word, the receiver judges whether known bit values held by corresponding positions in a code word obtained by decoding the received signal are the same as preset bit values. If the judgment result is negative, the code word based on the received signal is judges as erroneous even when it satisfies the parity check.

Abstract: The present disclosure describes a method, performed by a data processor comprising a cyclic redundancy check (CRC) module configured for calculating CRC remainders for encoded data and a comparator comprising a shift register, for making a cyclic redundancy check of an encoded data record of bit length L, in which at least A bits of the record represent content data and at least B bits represent check data. A system for performing a cyclic redundancy check is also described.

Abstract: A receiver including a switch for switching output of a memory to one of paths according to content of the output. The memory stores information bits, first check bits and second check bits. The first check bits and second check bits are switched to one of the paths via a rate dematch apparatus to a decoder. The information bits are switched directly to the decoder.

Abstract: A data transmission method according to the present invention includes the steps of: (A) adding a first CRC code to transmission data; (B) dividing the transmission data to which the first CRC code has been added into a plurality of encoded bit sequences; (C) adding a second CRC code to at least one of the divided encoded bit sequences; (D) performing error correction encoding processing on the encoded bit sequences; and (E) transmitting the encoded bit sequences on which the error correction encoding processing has been performed.

Abstract: A “Wi-Fi Multicaster” provides a practical and efficient Wi-Fi multicast system for environments having potentially large numbers of Wi-Fi clients. Significantly, the Wi-Fi Multicaster does not require any changes to the 802.11 protocol, or to the underlying Wi-Fi infrastructure. In various embodiments, the Wi-Fi Multicaster uses pseudo-broadcast, and augments it with destination control, association control and optional proactive FEC (forward error correction) to improve multicast performance. More specifically, the Wi-Fi Multicaster system converts multicast packets to targeted unicast transmissions. To minimize the amount of airtime consumed, the Wi-Fi Multicaster uses destination control in combination with various algorithms for association control. Further, in various embodiments, the Wi-Fi Multicaster includes an adaptive, proactive FEC scheme to reduce overall packet losses. Finally, to overcome the challenges posed by encryption protocols such as 802.

Abstract: A method is disclosed for transferring a number of medical image data records from a first computation facility to a second computation facility, with the second computation facility sending a transmission confirmation to the first computation facility after transmission is completed. In at least one embodiment, before the image data records are transmitted, a first checksum is determined for all the image data records and sent with the image data records; the first checksum is extracted at the second computation facility and is compared with a second checksum determined from the transmitted image data records in the same manner as the first checksum; and the transmission confirmation indicates a failure if the checksums do not correspond.

Abstract: A system and method for soft decoding data. A plurality of candidate error corrections may be generated to correct one or more data bits having soft bit information. Each candidate error correction may define suggested changes to the data bits and is associated with a soft bit value. The soft bit values associated the plurality of candidate error corrections may be mapped to a uniform scale, for example, a uniform finite or integer grid. The plurality of candidate error corrections may be ordered to have combined associated mapped values in a monotonically non-decreasing order. One or more of the plurality of candidate error corrections may be soft decoded in the order of the associated mapped values by a decoding operation for each candidate error correction therein with the associated non-mapped soft bit values.

Abstract: A system and method for decoding data. Multi-dimensional encoded data may be received that potentially has errors. The multi-dimensional encoded data may encode each input bit in a set of input bits multiple times in multiple different dimensions to generate encoded bits. The encoded bits may be decoded in at least one of the multiple dimensions. If one or more errors are detected in a plurality of encoded bits in the at least one of the multiple dimensions, an intersection sub-set of the encoded data may be decoded that includes data encoding the same input bits encoded by the plurality of encoded bits in at least a second dimension of the multiple dimensions. The values of the input bits by decoding the intersection sub-set may be changed.

Abstract: An error correction decoder includes a syndrome generator and an error correction value generator. The syndrome generator is operable to generate a plurality of syndromes based upon a received signal generated according to a generator polynomial. The error correction value generator is operable to generate a plurality of product values. Each of the product values is generated for one of the syndromes based upon a respective power of the roots of the generator polynomial. The respective power is determined based upon a respective index corresponding to one of the syndromes to be considered and unit positions of the received signal. The error correction value generator is further operable to generate an error correction value according to the product values, and to provide an error correcting device coupled thereto with the error correction value for correcting an error of the received signal.

Abstract: A method is provided for improving the acquisition of a data set transmitted repeatedly in a difficult environment, which is particularly appropriate to satellite radionavigation systems. The main characteristic of the method is to provide “contextual” aid relating to the transmitted data by indicating the nature and the possible updating of these data so that the receiver can accumulate the energy when the data are repeated in an identical manner. These aid data being short, it is possible to obtain good quality of reception and protection of this aid by virtue of its longer coding than that of the data.

Abstract: An apparatus, system and method for detecting errors in a physical interface during the transmission or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, a physical interface formed as a first IC on a first substrate portion to detect transmission errors in data exchanged with a second IC formed on a second substrate portion, the physical interface including multiple input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and one or more error recovery modules coupled between the plurality of input ports and output ports, where a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports.

Abstract: Low complexity error correction using cyclic redundancy check (CRC). Communications between at communication devices, sometimes including at least one redundant transmission from a transmitter to a receiver, undergo low complexity error correction. CRC may be employed in conjunction with using any desired type of ECC or using uncoded modulation. Based on CRC determined bit-errors, as few as a singular syndrome associated with a singular bit-error or a linear combination of syndromes associated with two or more singular bit-errors within two or more received signal sequences are employed to perform error correction of the received signal. Real time combinations of multiple syndromes associated with respective single bit-errors (that may themselves be calculated off-line) are employed in accordance with error correction. In addition to CRC, any ECC may be employed including convolutional code, RS code, turbo code, TCM code, TTCM code, LDPC code, or BCH code.

Abstract: Embodiments are disclosed herein that relate to multicast subscription based on forward error correction. One disclosed embodiment comprises a network-accessible server having a data-holding subsystem holding instructions executable by a logic subsystem to receive a content item, and form a first version of the content item having a first level of forward error correction and a second version of the content item having a second level of forward error correction. The instructions are further executable to stream the first version of the content item to a first multicast address, and while streaming the first version of the content item, stream the second version of the content item to a second multicast address.

Abstract: A Golay-code generator configured for generating Golay complementary code pairs comprises a sequence of delay elements configured for providing a predetermined set of fixed delays to at least a first input signal and a sequence of adaptable seed vector insertion elements configured for multiplying at least a second input signal by a variable seed vector, wherein each of a plurality of seed vectors corresponds to at least one predetermined piconet. The Golay-code generator may further comprise multiplexers configured for switching inputs and outputs of at least two delay elements in the sequence of delay elements to produce a plurality of compatible delay vectors. The Golay-code generator may further comprise a code-truncation module configured to shorten the Golay complementary code pairs for producing a plurality of daughter codes.

Abstract: Various embodiments of the present invention provide systems and methods for identifying a reproducible location on a storage medium. As an example, a circuit is discussed that includes a data storage circuit, a pattern comparison circuit, and a threshold comparison circuit. The data storage circuit is operable to store a first set of data samples corresponding to a region of interest. The pattern comparison circuit is operable to compare a subset of the first set of data samples with a subset of a second set of data samples corresponding to the region of interest. The pattern comparison circuit is operable to yield a match value corresponding to a degree of similarity between the first set of data samples with the subset of a second set of data samples. The threshold comparison circuit is operable to indicate an anchor point based at least in part on the magnitude of the match value relative to a threshold value.

Abstract: A circuit and technique for reducing parity bit-widths for check bit and syndrome generation is implemented through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The circuit and technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.

Abstract: A system and method are disclosed performing error correction on data by a processor. Received data is demultiplexed into a first demultiplexer output and a second demultiplexer output. Stored instructions are executed by a processor to decode the first demultiplexer output and a deinterleaver output to produce a decoded output. Stored instructions are executed by a processor to interleave the decoded output to produce an interleaved output. Stored instructions are executed by a processor to decode the interleaved output and the second demultiplexer output to produce decoded data. Stored instructions are executed by a processor to deinterleave the decoded data. The deinterleaved data is output.

Abstract: An approach is provided for processing structure Low Density Parity Check (LDPC) codes. Memory storing edge information and a posteriori probability information associated with a structured parity check matrix used to generate Low Density Parity Check (LDPC) coded signal are accessed. The edge information represent relationship between bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge information.

Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in 32APSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.

Abstract: The present invention discloses a method and apparatus for processing and error correction of a GFP-T superblock, where the 64 bytes of payload data of a first superblock are buffered in the first page of a two-page buffer. The flag byte is buffered in a separate buffer, and a CRC operation is performed in a separate logic element. The result of the CRC operation is checked against a single syndrome table which may indicate single- or multi-bit errors. As the payload data of the first superblock is processed and read out of the first page of the two-page buffer, the payload data of a second superblock is written into the second page of the two-page buffer to be processed and corrected.

Abstract: Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit (620) searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) (630) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.

Abstract: A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

Abstract: A method and apparatus for selecting interleaver sizes for turbo codes is provided herein. During operation information block of size K is received. An interleaver size K? is determined that is related to K?, where K? from a set of sizes; wherein the set of sizes comprise K?=ap×f, pmin?p?pmax; fmin?f?fmax, wherein a is an integer and f is a continuous integer between fmin and fmax, p takes integer values between pmin and pmax, a>1, pmax>pmin, pmin>1. The information block of size K is padded into an input block of size K? using filler bits, if needed. Encoding is performed using the original input block and the interleaved input block to obtain a codeword block using a turbo encoder. The codeword block is transmitted through the channel.

Abstract: Disclosed are a wireless transmission device, wireless receiving device, and method for transmitting encoded data with which power consumption can be reduced at the receiving end in accordance with reception conditions, while resource-saving is maintained by employing an erasure correcting code (ECC).