Abstract: To enable an instrument panel to appropriately check whether or not data display is normal. A display control apparatus includes a display output control unit and a CPU. The display output control unit includes a comparison control unit which performs a cyclic redundancy check over an arbitrary region of image data. The comparison control unit includes a region control unit which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image displayed on the display unit as a cyclic redundancy check target region, an arithmetic processing unit which performs arithmetic processing for the cyclic redundancy check over a region selected by the region control unit, and a comparison circuit which performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with its expected value.

Abstract: An embodiment of a data write path includes encoder and write circuits. The encoder circuit is operable to code data so as to render detectable a write error that occurs during a writing of the coded data to a storage medium, and the write circuit is operable to write the coded data to the storage medium. For example, such an embodiment may allow rendering detectable a write error that occurs while writing data to a bit-patterned storage medium.

Abstract: For detecting an error of an A/D converter, which is designed to generate at least one digital output signal, which includes a quantity of output data bits, based on at least one analog input signal, and during a conversion, to generate a thermometer code which includes a quantity T of output data values, the detection method includes: ascertaining a first parity directly for the output data bits of the output signal; making a prediction for the output data bits on the basis of the T output data values of the thermometer code; ascertaining a second parity, which is a reverse of the first parity, for the predicted output data bits; and detecting an error for the A/D converter when both the first and second parities are identical.

Abstract: A semiconductor memory device includes: a first bank and a second bank; one or more first data input/output pads disposed at one side of the first bank and used in access to data of the first bank; one or more second data input/output pads disposed at one side of the second bank and used in access to data of the second bank; a first cyclic redundancy code (CRC) generation circuit for generating a first CRC using a plurality of data output from the first bank and outputting the generated first CRC through the first data input/output pads; and a second CRC generation circuit for generating a second CRC using a plurality of data output from the second bank and outputting the generated second CRC through the second data input/output pads.

Abstract: A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include progressively enabling and disabling nodes of the iterative decoder to perform iterative decoding on a demodulated signal to provide a decoded signal with minimal variation of a supply voltage.

Abstract: A low complexity List Viterbi algorithm (LVA) for decoding tail biting convolutional codes (TBCCs) has lower complexity than a solution of running the LVA algorithm for all states. In one aspect, a low complexity LVA-TBCC process includes finding a list of states from a single Viterbi algorithm and finding a list of potential codewords for each state in the state list using the LVA. A cyclic redundancy check may prune out false solutions. The disclosed method may be applied to many communication systems to improve error performance similar to LTE downlink PBCH decoding enhancements.

Abstract: In accordance with the teachings described herein, systems and methods are provided for performing forward error correction. A decoder for performing forward error correction for a frame in a data stream includes a state machine configured to determine if a code block within the frame received by the decoder is a complete code block or a partial code block, the frame including a plurality of code blocks. A decoding unit is configured to receive the code block, and, when the code block is a partial code block, to generate an output based on decoding the partial code block and an additional partial decoding result that is input to the decoding unit.

Abstract: Wired and wireless communication networks can be subject to burst interference resulting in loss of throughput and data corruption. In a communication system comprising a transmitting network device and a receiving network device, the transmitting network device can be configured to implement balanced bit loading for retransmitting packets of a failed packet transmission. On receiving a request for retransmission from the receiving network device, the transmitting network device can identify and eliminate sub-carriers that are associated with a bit load that is less than a predefined bit load threshold. The transmitting network device can attempt to reallocate bit loads of the eliminated sub-carriers to remaining sub-carriers across two or more constituent symbols per original symbol.

Abstract: A digital broadcasting system and method of processing data are disclosed. Herein, a method of processing data in a transmitting system includes creating a data group including a plurality of mobile service data packets, re-adjusting a relative position of at least one main service data packet of a main service data section, the main service data section including a plurality of main service data packets, and multiplexing the mobile service data of the data group and the main service data of the main service data section in burst units. Herein, a position of an audio data packet among the main service data packets of the main service data section may be re-adjusted. Also, a position of an audio data packet included in the main service data section may be re-adjusted based upon a multiplexing position of the main service data section.

Abstract: The present invention relates to an error control technology in the communication system and discloses a method and an apparatus for implementing Cyclic Redundancy Check (CRC) codes to improve the operation performance of the system significantly and satisfy operation requirements when processing high-rate CRC data. The method includes: performing at least one XOR operation for information bits input in parallel to obtain a first result, where at least one pipeline is added during the XOR operation; performing an XOR operation for a previously obtained CRC code to obtain a second result; and performing an XOR operation for the second result and the first result to obtain a current CRC code. The present invention is applicable to any field that needs to implement CRC codes by means of hardware.

Abstract: A text watermarking method embeds an auxiliary message in an original electronic text document to form a watermarked text document. The method applies a spreading function to message symbols to spread the symbols over a carrier, which forms a modulated carrier. It maps elements of the modulated carrier to corresponding inter-word spaces in the electronic text document, and applies an embedding function to modify the corresponding inter-word spaces according to elements of the modulated carrier signal such that the modified inter-word spaces hide the modulated carrier signal in the watermarked text document. The message symbols are automatically decodable from the watermarked document without the original electronic text document. A compatible decoder extracts the auxiliary message from a printed or electronic watermarked text document. The decoder automatically measures inter-word spaces in the watermarked text document.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: A vital-signs device in a patient monitoring system is disclosed. The patch includes a housing configured to be attached to the skin of a patient. The housing contain monitoring circuitry configured to acquire and store measurements of vital signs of the patient, a wireless transmitter configured to transmit signals to another device, a wireless receiver configured to receive signals from the other device; and a processor operably connected to the monitoring circuitry, transmitter, and receiver. Upon receipt of an upload signal from the other device, the processor is configured to send a message to the other device via the transmitter. The message packet structure includes a data payload of variable size, a header containing transmit and route information and data payload length, and a data integrity check value.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: In a transmission device, a determining unit determines, for use in transmission, an LDPC encoding method corresponding to occurrence conditions of external noise from a plurality of LDPC encoding methods each having the same code length and the same code rate and being defined by a different parity check matrix, and an encoding unit generates a codeword bit sequence by encoding transmission data using the LDPC encoding method determined by the determining unit.

Abstract: A method includes, during a first iteration of a first decoder for decoding convolutionally encoded data elements, determining a first value of a first path metric. The method also includes, during a second iteration of the first decoder, determining a second value of the first path metric by using the first value of the first path metric as an initial value of the first path metric.

Abstract: An Parallel and Long Adaptive Instruction Set Architecture (PALADIN) is provided to optimize packet processing. The Instruction Set Architecture (ISA) includes instructions such as aggregate comparison, comparison OR, comparison AND and bitwise instructions. The ISA also includes dedicated packet processing instructions such as hash, predicate, select, checksum and time to live adjust, move header left, post, move header left/right and load/store header/status.

Abstract: Provided is a radio communication device which can obtain an error ratio characteristic equivalent to the one obtained by using a tail bit, without using a tail bit in the error correction and encoding. The device includes: a blocking unit (106) which adds a bit indicating an error detection result in a CRC unit (105) to control data (a bit string) so as to constitute an encoded block and outputs the encoded block to an encoding unit (107); and the encoding unit (107) which corrects and encodes the encoded block. The blocking unit (106) forms an encoded block by a bit string of control data and a probability deviation existence bit added to the tail of the bit string.

Abstract: A system may be used to predict when a decoding process will fail to correct an error burst within a transmission. A decoder may receive an input bit stream and process it to produce an output bit stream, which may be convolutionally encoded. K-bits of the convolutionally encoded output bit stream may be compared with a corresponding k-bits of a delayed version of the input bit stream, with the k-bits starting at a first bit and ending at first bit+k. For each bit of the k-bits in the convolutionally encoded output bit stream and in the corresponding k-bits of the delayed version of the input bit stream, a number of conflicting bits and whether the number of conflicting bits exceeds a threshold number of conflicting bits may be determined. The output bit stream may be sent to a block decoding component for decoding with the bits marked for erasure.

Abstract: A data transmission detecting device including a detecting module and a detection value calculating module is provided. The detecting module has a plurality of receiving terminals and receives a first data and a second data during a first period. The detecting module calculates a total detection value according to the first data and the second data, and performs an error check comparison by comparing the total detection value with an error check code. When the detecting module again receives the first data during a second period, the detection value calculating module transmits an auxiliary detection value to the detecting module, so that the detecting module calculates a corresponding total detection value according to the auxiliary detection value, and performs the error check comparison by comparing the total detection value with the error check code. The first period and the second period are two successive periods adjacent to each other.

Abstract: The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.

Abstract: A decoder 5 applies decode processing to N input data in parallel to generate K decode data. An S/P converter 6 outputs N input data applied in series to decoder 5 through first lines L1-L64 dividedly over several times. A P/S converter 7 receives through second lines R1-R60 the K decode data from decoder 5 dividedly over several times to output in series the K decoded data to an external source.

Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented.

Abstract: Schemes for creating a surplus of decoding iterations in a decoder are described. The surplus can be used to augment the decoding of signal blocks. The option of using an idle decoder to decode blocks marked as unproductive for decoding is also described.

Abstract: Erasure-encoded data is stored across a plurality of storage devices in a data storage system. The erasure-encoded data includes k data elements to store on k data storage devices and m parity elements to store on m parity storage devices, wherein for a given minimum Hamming distance d of the data storage system and m?(d?1), data elements are assigned only to corresponding unique combinations of parity elements of size (d?1).

Abstract: In one embodiment, a de-interleaver receives soft-output values corresponding to bits of an LDPC-encoded codeword. The de-interleaver has scratch pad memory that provides sets of the soft-output values to a local de-interleaver. The number of values in each set equals the number of columns in a block column of the LDPC H-matrix. Each set has at least two subsets of soft-output values corresponding to at least two different block columns of the LDPC H-matrix, where the individual soft-output values of the at least two subsets are interleaved with one another. Local de-interleaving is performed on each set such that the soft-output values of each subset are grouped together. Global de-interleaving is then performed on the subsets such that the subsets corresponding to the same block columns of the H-matrix are arranged together. In another embodiment, an interleaver performs global then local interleaving to perform the inverse of the de-interleaver processing.

Abstract: A television transmitting system includes an encoder, a data randomizing and expanding unit, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizing and expanding unit randomizes the error-detection-coded data and expands the randomized data. The group formatter forms a group of enhanced data having one or more data regions and inserts the expanded enhanced data into at least one of the regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter generates enhanced data packets.

Abstract: A channel equalizer includes a channel estimator, a coefficient calculator, a multiplier, and an error remover. The channel estimator estimates a channel impulse response (CIR) of input data in which a known data sequence is periodically inserted. The coefficient calculator calculates equalization coefficients using estimated CIR, and the multiplier multiplies the input data with the equalization coefficients for channel equalization. The error removes estimates a residual carrier phase error of the channel-equalized input data and removes the estimated phase error from the input data.

Abstract: The invention includes a method and apparatus for providing media content. The method includes duplicating each packet of an original packet stream for which an associated importance level satisfies an importance condition, inserting each duplicate packet within the original packet stream to form thereby a modified packet stream, and transmitting the modified packet stream toward a wireless terminal adapted for processing the modified packet stream for presenting the media content conveyed by the original packet stream. The duplicate packets may be inserted within respective windows associated with the duplicate packets, wherein each window is determined according to an original packet position associated with the original packet from which the duplicate packet is formed.

Abstract: A transmitting apparatus generates and transmits 3t+1 or more number of codewords for a message and multiple faulty encoded message identifying data, wherein the information regarding the message may not be obtained from t or less number of encoded messages and the message can be decoded from 2t+1 or more codewords. The faulty encoded message identifying data are able to detect t or less number of faulty codewords of the message, even if there are t or less number of faulty codewords. A receiving apparatus checks whether there is no fault in each codeword for the message, using the codewords of the message and faulty encoded message identifying data for the codewords of the message received and the corresponding faulty encoded message identifying data and also checks whether the codewords decided to be non-faulty are all of the same message.

Abstract: A PLI n-bit correction circuit extracts a core header (PLI) from a GFP frame with a fixed payload length; compares it with a predetermined expectation value for each bit; calculates the number of inconsistent bits therebetween; and outputs the predetermined expectation value, instead of the core header, when the number of inconsistent bits is equal to or less than n (n is a natural number); or directly outputs the core header when the number of inconsistent bits is greater than n. A decision on establishment of GFP Layer 2 synchronization is made based on the output of the PLI n-bit correction circuit, wherein predetermined processing is executed on a payload of a GFP frame dropping its core header when GFP Layer 2 synchronization is established, whilst the payload is not subjected to predetermined processing and discarded in the event of GFP Layer 2 desynchronization.

Abstract: Methods and systems for detecting errors in a field programmable gate array are disclosed. One method includes applying a cyclic redundancy check value to a transaction, the transaction including an address and data associated with the address. The method also includes applying a cyclic redundancy check value prior to routing the transaction through a field programmable gate array, and checking the cyclic redundancy check value after routing the transaction through the field programmable gate array to detect errors in the field programmable gate array.

Abstract: Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured to detect and report a parity error on the command signal, the address signal, or combinations thereof In some embodiments, a memory device may include a temperature sensor operably coupled to a mode register. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.

Abstract: A system and method is provided for decoding a set of bits using a plurality of hypotheses, for example, each independently tested on-the-fly. Initial bit states and associated reliability metrics may be received for the set of bits. A current hypothesis may be decoded for correcting the set of bits, wherein the current hypothesis defines different bit states and associated reliability metrics for the set of bits. If decoding the current hypothesis is not successful, a subsequently ordered hypothesis may be decoded, wherein the hypotheses are ordered such that their associated reliability metric is a monotonically non-decreasing sequence. Decoding may proceed iteratively until the current hypothesis is successful.

Abstract: In one embodiment, an LDPC decoder performs a targeted bit adjustment method to recover a valid codeword after the decoder has failed. In a first stage, a post processor initializes the decoder by saturating LLR values output by the decoder during the last (i.e., failed) iteration to a relatively small value. Then, two-bit trials are performed, wherein LLR values corresponding to two bits of the codeword are adjusted in each trial. Decoding is performed with the adjusted values, and if the number of unsatisfied check nodes exceeds a specified threshold, then a second stage is performed. The post processor initializes the decoder by saturating the LLR values output by the decoder during the last (i.e., failed) iteration of the first stage to a relatively small value. The second stage then performs single-bit adjustment trials, wherein one LLR value corresponding to one bit of the codeword is adjusted in each trial.

Abstract: In a passive optical network, an upstream transmission rate from an ONT to an OLT can be optimized by matching a transmission scheme for a channel to the upstream transmission characteristics of the channel. An FEC coding can be made channel dependent so that channels with low error rates can use minimal protection, and therefore minimal overhead, while channels with high input bit error rates can use the level of FEC coding required to produce a desired output bit error rate.

Abstract: An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(28) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.

Abstract: A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.

Abstract: A transmitting apparatus for transmitting user data, includes: an establishing section that establishes three or more transmission paths for a receiving apparatus; a first generation section that generates a user data unit which includes user data to be transmitted to the receiving apparatus; and a second generation section that generates an error correction data unit which includes error correction data to be used for error correction of the user data to be transmitted to the receiving apparatus. At least one of the three or more transmission paths transmits the error correction data unit, and at least two of the three or more transmission paths transmits the user data unit.

Abstract: A communication system (e.g., a hard drive) having a random-access memory (RAM) for storing trapping-set (TS) information that the communication system generates on-line during a special operating mode, in which low-density parity-check (LDPC)-encoded test codewords are written to a storage medium and then read and decoded to discover trapping sets that appear in candidate codewords produced by an LDPC decoder during decoding iterations. The discovered trapping sets are filtered to select a subset of trapping sets that satisfy specified criteria. The discovery and filtering of trapping sets is performed based on error vectors that are calculated using the a priori knowledge of original test codewords. The TS information corresponding to the selected subset is stored in the RAM and accessed as may be necessary to break the trapping sets that appear in candidate codewords produced by the LDPC decoder during normal operation of the communication system.

Abstract: A transfer apparatus includes: a receiver to receive one of an error correction packet and a data packet, the error correction packet for recovering the data packet through error correction, and the data packet having protective coverage information written thereon, the protective coverage information identifying a protective coverage on the data packet recoverable through an error correction of the error correction packet; an updater to update the protective coverage information in accordance with an order of reception of the data packets received by the receiver unit; a generator to generate an error correction packet of the data packet identified by new protective coverage information updated by the updater unit; and a transmitter to transmit the data packet having the protective coverage information updated by the updater unit, and the error correction packet generated by the generator unit.

Abstract: A method and apparatus for encoding and decoding high speed shared control channel (HS-SCCH) data are disclosed. For part 1 data encoding, a mask may be generated using a wireless transmit/receive unit (WTRU) identity (ID) and a generator matrix with a maximum minimum Hamming distance. For part 2 data encoding, cyclic redundancy check (CRC) bits are generated based on part 1 data and part 2 data. The number of CRC bits is less than the WTRU ID. The CRC bits and/or the part 2 data are masked with a mask. The mask may be a WTRU ID or a punctured WTRU ID of length equal to the CRC bits. The mask may be generated using the WTRU ID and a generator matrix with a maximum minimum Hamming distance. The masking may be performed after encoding or rate matching.

Abstract: A method is for generating, for each check node related to a parity check equation of a LDPC code, signals representing a first output table of corrected values of symbols of a word received through a communication channel and transmitted according to the LDPC code, and signals representing a second output table of the logarithm of the ratio between the respective probability of correctness of the values of same coordinates in the first output table and their corresponding maximum probability of correctness. The method is implemented by processing the components of a first input table of values of a Galois Field of symbols that may have been transmitted and of a second input table of corresponding probability of correctness of each value.

Abstract: An encoder and decoder using LDPC-CC which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an encoding method of the same. A termination sequence length determining unit (631) determines the sequence length of a termination sequence transmitted added to the end of an information sequence, according to the information length (information size) and encoding rate of the information sequence. A parity calculation unit (632) carries out LDPC-CC coding on the information sequence and the known-information sequence necessary for generating a termination sequence of the determined termination sequence length, and calculates a parity sequence.

Abstract: A method for sending data from a transmitter to a receiver in a transmission network comprising receiving outgoing data that is eight-bits-ten-bits (8b10b) encoded at a Gigabit Ethernet (GE) line rate from a physical medium attachment (PMA) layer, 8b10b decoding the received outgoing data, 64-bits-to-66-bits (64b66b) encoding the 8b10b decoded outgoing data, forward error correction (FEC) encoding the 64b66b encoded outgoing data, and serializing and sending the 64b66b and FEC encoded outgoing data at the GE line rate to a physical medium dependent (PMD) layer.

Abstract: A method for producing processed media content includes receiving media content at a network computing device. The media content is obtained from a media source at a scheduled time via a public network based on a user recording request received from a user device associated with a user. The method includes processing the media content to generate processed media content at the network computing device based on user settings associated with the user recording request. The method also includes storing the processed media content at a memory device identified in the user recording request.

Abstract: By controlling to select encoding appropriately considering characteristics of equalization and decoding of a receiving apparatus employing a turbo equalization technology, it is possible to attain a high transmission characteristic. Information bits of two systems including a sequence which is input to a first RSC encoding unit 22 and a sequence which is input through an interleaving unit 21 to a second RSC encoding unit 23 are set for input information bits, and each of which is subjected to RSC encoding. Each encoded parity bit is input to a puncturing unit 24. Since a systematic bit obtained by the first RSC encoding unit 22 is the information bit itself, a systematic bit obtained by the second RSC encoding unit 23 is not transmitted. In the puncturing unit 24, while puncturing is applied according to a predetermined coding rate, selection of either an RSC code or a turbo code is carried out by a puncturing control unit 25.

Abstract: This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.

Abstract: Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.

Abstract: A computer-implemented method and computer program product comprising optimal, systematic q-ary codes for correcting all asymmetric and symmetric errors of limited magnitude are provided.