Abstract: Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.

Abstract: A computer-implemented method and computer program product comprising optimal, systematic q-ary codes for correcting all asymmetric and symmetric errors of limited magnitude are provided.

Abstract: An improved latch arrangement for an electronic digital system is disclosed. The latch arrangement comprises a certain number of standard latches configured as configuration-switch latches which are modified only by shift operation and/or during Error Checking and Correction (ECC) action, and a corresponding number of standard latches configured as Error Checking and Correction (ECC) latches storing Error Checking and Correction (ECC) bit data used to check latch data of said configuration-switch latches.

Abstract: In one embodiment, a turbo equalizer is selectively operable in either first or second modes. In the first mode, layered (low-density parity-check (LDPC)) decoding is performed on soft-output values generated by a channel detector, where, for each full local decoder iteration, the updates of one or more layers of the corresponding H-matrix are skipped. If decoding fails to converge on a valid LDPC-encoded codeword and a specified condition is met, then LDPC decoding is performed in a second mode, where the updates of all of the layers of the H-matrix are performed for each full local decoder iteration, including the one or more layers that were previously skipped in the first mode. Skipping one or more layers in the first mode increases throughput of the decoder, while updating all layers in the second mode increases error correction capabilities of the decoder.

Abstract: Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points.

Abstract: An encoding circuit comprising: a memory unit; an EDC generating circuit, a scrambler, a header generator, an EDC correcting circuit and an decoder. The EDC generating circuit is used for generating a first EDC according to at least one main data, and for storing the first EDC to the memory unit. The scrambler is used for generating a scrambled main data according to the main data, and for storing the scrambled main data to the memory unit. The header generator is used for generating a header according to header information. The EDC correcting circuit is used for reading the first EDC from the memory unit and for correcting the first EDC according to the header to generate a second EDC. The encoder is used for encoding optical data according to the second EDC and the scrambled main data.

Abstract: A digital receiving system, and a method of processing data are disclosed. The digital receiving system includes a receiving unit, a known sequence detector, and a channel equalizer. The receiving unit receives a broadcast signal including mobile service data and main service data. The known sequence detector detects known data linearly inserted in a data group. The channel equalizer performs channel-equalizing on the received mobile service data using the detected known data.

Abstract: Methods and systems for reduced-complexity decoding of low-density parity-check (LDPC) information. An encoded input stream is received. The received stream is decoded with one or more reduced-complexity min-sum or a posteriori probability LDPC decoders. A v-node update rule in the reduced complexity decoder is omitted.

Abstract: A phase synchronization apparatus includes: a sampling section; a phase-error detection section; a first computation section; a second computation section; and an interpolation section.

Abstract: A method of estimating signal-to-noise ratio in a Viterbi decoder comprising: setting a threshold SNR value; determining a dependence on SNR of the average decoding path length; filling branch metrics matrix, minimal path metrics matrix, path metrics matrix and paths matrix with initial values; receiving packets from a communication channel; calculating the matrices that contains paths stored during operation of Viterbi algorithm in its rows, and a minimal path metrics matrix, including calculating an estimate of a decoding path length, where all the paths converge, based on the paths matrix; calculating current SNR estimate using an estimate of a decoding path length, based on results of previous steps; setting a decoder control signal to an active state if the current estimated SNR does not exceed the threshold, and to an inactive state otherwise; if the decoder control signal is in active state, the branch metrics matrix, the minimal path metrics matrix, the paths metrics matrix and the paths matrix are fi

Abstract: An apparatus generally having a lookup table and a circuit is disclosed. The lookup table may be configured to store a plurality of results including remainders of divisions by a particular polynomial. The circuit may be configured to (i) parse a first polynomial into a plurality of data blocks and an end block, (ii) fetch a plurality of results from the lookup table by indexing the lookup table with each of the data blocks and (iii) generate a second polynomial by adding the results fetched from the lookup table to the end block. The second polynomial generally has a second degree that is lower that a first degree of the first polynomial.

Abstract: A family of quasi cyclic irregular low density parity check codes for video broadcasting applications. The parity check matrices of the constructed low density parity check codes have quasi-cyclic structures to facilitate hardware implementation and have proper check/bit degree distributions to offer frame error rate performance lower than 10?7.

Abstract: Digital communication coding methods resulting in rate-compatible low density parity-check (LDPC) codes built from protographs. Described digital coding methods start with a desired code rate and a selection of the numbers of variable nodes and check nodes to be used in the protograph. Constraints may be set to satisfy a linear minimum distance growth property for the protograph. All possible edges in the graph are searched for the minimum iterative decoding threshold and the protograph with the lowest iterative decoding threshold is selected. Protographs designed in this manner may be used in decode and forward relay channels.

Abstract: Provided are a communication apparatus and method using a matrix network coding scheme. The communication apparatus includes a reception unit to receive a corrupted packet including a plurality of corrupted words, and a controller to estimate a first decoded word corresponding to the corrupted words based on the corrupted words and a generator matrix. The controller generates a second decoded word corresponding to the corrupted words based on a codebook and the estimated first decoded word. The codebook is based on the generator matrix. The controller generates a message based on a plurality of second decoded words respectively corresponding to the plurality of corrupted words.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.

Abstract: A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM) includes providing comparand data to the CAM, comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry. In response to asserting the match signal, the method further includes providing output data, an output parity bit, and an output complement parity bit from the RAM, using the comparand data to generate a generated parity bit, and providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit. The error indicator may indicate an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.

Abstract: Systems, methods, and an article of manufacture for decoding a broadcast signal are shown and described. In particular, aspects of the Reed-Solomon decoding algorithm are improved to thereby reduce the amount of processing time required to execute the Reed-Solomon decoding.

Abstract: Coded video data may be transmitted between an encoder and a decoder using multiple FEC codes and/or packets for error detection and correction. Only a subset of the FEC packets need be transmitted between the encoder and decoder. The FEC packets of each FEC group may take, as inputs, data packets of a current FEC group and also an untransmitted FEC packet of a preceding FEC group. Due to relationships among the FEC packets, when transmission errors arise and data packets are lost, there remain opportunities for a decoder to recover lost data packets from earlier-received FEC groups when later-received FEC groups are decoded. This opportunity to recover data packets from earlier FEC groups may be useful in video coding and other systems, in which later-received data often cannot be decoded unless earlier-received data is decoded properly.

Abstract: Translating between a first communication protocol used by a first network component and a second communication protocol used by a second network, where translating includes: receiving, by a network engine adapter operating independently from the first and second network components, data packets from the first and second network components; and performing, by the network engine, a combined communication protocol based on the first communication protocol and the second communication protocol, including manipulating data packets of at least one of the first communication protocol or the second communication protocol, thereby offloading performance requirements for the combined communication protocol from the first and second network components.

Abstract: In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality of components and the bus uses at least as many signal lines as components of the vector that are used, mapping the codeword to a second set of physical signals, wherein components of the second set of physical signals can have values from a set of component values having at least three distinct values for at least one component, and providing the second set of physical signals for transmission over the data bus in a physical form.

Abstract: The present invention relates to a method and a system for transmitting and receiving control information of an Multi-Input Multi-Output (MIMO) system, wherein the control information consists of information bits and parity bits. A base station transmits the control information including the location information for where the control information of the other terminal is transmitted. A terminal receives the control information of the other terminal based on the location information for where the control information of the other terminal is received. Therefore, the precoding matrix of the other terminal can be obtained from the received control information. The invention enables the removal of interference through the obtained precoding matrix when receiving a data symbol in an environment where a channel is not in a good state.

Abstract: Disclosed is an encoding processing apparatus in which reception precision characteristics are improved by specially adapting puncture processing in respect of the code words for each encoding system. A puncture section (130) switches between a puncture pattern for a first code word partial sequence obtained on the basis of the head and tail in a fixed information block, and a puncture pattern for a second code word partial sequence obtained on the basis of the middle portion, excluding the head and tail. Also, the puncture section (130) receives the number of retransmissions of information from a retransmission control section (180) and switches the puncture pattern for the second code word partial sequence in accordance with the number of retransmissions. In addition, the puncture section (130) prioritising systematic bits over parity bits when puncturing the first code word partial sequence.

Abstract: An apparatus, system, and method are disclosed for a front-end, distributed redundant array of independent drives (“RAID”). A storage request receiver module receives a storage request to store object or file data in a set of autonomous storage devices forming a RAID group. The storage devices independently receive storage requests from a client over a network, and one or more of the storage devices are designated as parity-mirror storage devices for a stripe. The striping association module calculates a stripe pattern for the data. Each stripe includes N data segments, each associated with N storage devices. The parity-mirror association module associates a set of the N data segments with one or more parity-mirror storage devices. The storage request transmitter module transmits storage requests to each storage device. Each storage request is sufficient to store onto the storage device the associated data segments. The storage requests are substantially free of data.

Abstract: An apparatus and a method segment an allocated resource in data transmission in a wireless communication system. When a size of transmission data is large, the data information bit is distributed to one or more forward error correction (FEC) blocks with consideration of a size of the data information bit. A number of data tones is determined based on control information with respect to each of the one or more FEC blocks. The data information bit distributed to the one or more FEC blocks is mapped into a data tone with consideration of the number of data tones determined for each of the one or more FEC blocks.

Abstract: Techniques for performing erasure detection and power control for a transmission without error detection coding are described. For erasure detection, a transmitter transmits codewords via a wireless channel. A receiver computes a metric for each received codeword, compares the computed metric against an erasure threshold, and declares the received codeword to be “erased” or “non-erased”. The receiver dynamically adjusts the erasure threshold based on received known codewords to achieve a target level of performance. For power control, an inner loop adjusts the transmit power to maintain a received signal quality (SNR) at a target SNR. An outer loop adjusts the target SNR based on the status of received codewords (erased or non-erased) to achieve a target erasure rate. A third loop adjusts the erasure threshold based on the status of received known codewords (“good”, “bad”, or erased) to achieve a target conditional error rate.

Abstract: A receiver with capability of correcting error is disclosed. A soft slicer generates quantized data and associated soft data. A decoder with error recovery generates decoded quantized data and a soft sequence, and is capable of correcting one bit of the quantized data. A serial-to-parallel (S/P) converter with code corrector generates parallel data, and is capable of correcting two bits of de-scrambled data bits.

Abstract: In a transmission apparatus, a first parity calculation controller calculates parity by the frame and inserts a calculation result into a next frame to a first frame sequence. A second parity calculation controller calculates the parity by the frame and inserts a calculation result into a next frame to a second frame sequence. The second parity calculation controller receives from the first parity calculation controller first parity data which is a parity calculation result by the first parity calculation controller and which has the same value as that of a parity calculation result to be inserted into a target frame of a parity calculation in the second frame sequence. Then, the controller calculates the parity of the target frame including the first parity data and second parity data which is a parity calculation result of a previous frame in the second frame sequence before one frame of the target frame.

Abstract: According to one embodiment, an interface device including a decoding module configured to decode received data, a storage module configured to store data obtained after the decoding module performs decoding, a CRC module configured to detect a CRC error included in the data obtained after the decoding module performs the decoding, an error detection module configured to detect a decoding error included in the data obtained after the decoding module performs the decoding, and a data processing module configured to process, as valid data, the data that is obtained after the decoding module performs the decoding and stored in the storage module when the decoding error detected by the error detection module is non-user data and the CRC module does not detect any CRC error.

Abstract: A wireless reception apparatus (200) for a wireless communication system which transmits, between an MBS transmission apparatus and MBS reception apparatus, multiple transport blocks (TB) coded by error correction coding at the physical layer or at both the physical layer and the data link layer. In the wireless reception apparatus (200), a feedback condition judgment unit (208) transmits feedback information to the MBS transmission apparatus when a reception judgment unit (206) detects errors in L or more TBs out of an N-number of TBs (N is a natural number while L is a natural number less than N) that constitute the beginning portion of any MAC FEC blocks where the beginning TB has been identified. In the wireless communication apparatus (100), the link adaptation unit (114), based on the feedback information from the wireless communication apparatus (200), adjusts the physical layer transmission parameters used for the TBs in the physical layer processing unit.

Abstract: A method of communication comprising determining whether to use distributing coding between a source (S), relay (R) and destination (D), based on a predetermined transmission rate; if the determination is positive, determining a forward error correction scheme using distributed Alamouti space-time coding, wherein the scheme is determined based on the predetermined transmission rate, a channel signal-to-noise ratio (SNR) and a network topology; relaying coded data from the S to the D using the determined forward error correction.

Abstract: A method is provided for configuring an overall encoding scheme comprising a first encoding for generating first encoded packets from source packets and a second encoding for generating second encoded packets by combination of first encoded packets according to a combination scheme applied by predetermined nodes of the network. The method obtains a number N of defective paths among paths used to transmit the first and second encoded packets to at least one destination node, a path being defective if an associated quality of transmission is below a predetermined threshold. A combination scheme is selected from among at least two possible predetermined combination schemes for which a number of encoded second packets is greater than or equal to N.

Abstract: Disclosed are a method and apparatus for detecting frame boundary for a data stream received at an Ethernet FEC layer, as well as a decoding method and system for the same. The apparatus for detecting frame boundary may comprise: a buffer for buffering data in a data stream, a length of the data in the buffer being greater than one frame; a syndrome generator for calculating a current syndrome based on a first data item, a second data item, and an intermediate calculation result of a previous syndrome, wherein the first data item is the last bit in a current candidate frame, and the second data item is a bit preceding the current candidate frame; and a comparator for using the current syndrome to check whether the bit preceding the current candidate frame is a frame boundary of an Ethernet FEC layer. The apparatus for detecting frame boundary can improve the speed of frame boundary detection.

Abstract: Disclosed is a wireless communication apparatus in which reception precision characteristics are improved, by specially adapting the modulating processing in respect of the code words for each encoding system. A wireless communication apparatus (100) wherein an encoding processing section (120) includes a convolutional encoder that performs convolutional encoding of fixed information blocks made up of K bits. In code word partial sequences obtained on the basis of the head and tail in a fixed information block, a modulating section (130) maps bits, from bit groups constituting single symbols, to bits associated with groups having poor quality characteristics, prioritising systematic bits over parity bits. In this way, the reception quality characteristics in first code word partial sequences having good error characteristics is equalised.

Abstract: A method of iteratively decoding data transferred through a channel is provided. The method may include iteratively decoding each sector of 1 to N sectors of the data in continuous succession until all N sectors are decoded, wherein upon determination of successful completion of iterative decoding corresponding to a current sector of the N sectors, immediately initiating iterative decoding a next sector of the N sectors.

Abstract: A data scrubbing apparatus corrects disturb errors occurring in a memory cell array, such as SMT MRAM cells. The data scrubbing apparatus activates scrubbing of the data and associated error correction bits based on a number of errors corrected, at a power up of the memory cell array, or a programmed time interval. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data, the associated error correction bits, and reference bits. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.

Abstract: In a method for transmitting data of various traffic types an xDSL modem is utilized. Detectors are used to detect the traffic types of the data which are to be transmitted and the detected traffic types are taken as a basis for dynamically adjusting a data transmission rate for the xDSL modem.

Abstract: Disclosed are: a method for constructing a low-density parity-check (LDPC) code for use in next-generation mobile communication and deep-space communication by using a cyclic distribution; a transmitter; a receiver; and a system. The method includes a block cycle determination step in which the distribution of a block cycle constructed from non-zero cyclic shift element values is determined for the basic matrix of the LDPC code, a priority determination step in which the priorities of the non-zero cyclic shift element values included in each block cycle are determined on the basis of the determined block cycle distribution, and a calculation step in which the greatest common divisor is determined for the permutation elements of all magnitudes in the check matrix of the LDPC code, and the divisor is factored. According to this method, short cycles will not be included in any actual check matrix of an LDPC code constructed by using all different permutation elements.

Abstract: A device, method, machine-readable medium, and system are disclosed. In one embodiment the device is a memory controller capable of modifying a reference voltage to a persistent moving read reference (MRR) voltage level for use during one or more subsequent reads to a non-volatile memory array. This modification is in response to a change in a reference voltage supplying the non-volatile memory array from a previous reference voltage level to a temporary MRR voltage level.

Abstract: The inventive concept enables backward-compatible extension of existing interleaver-based transmission systems to the effect that in addition to an existing logical transport channel, which is interleaved using a standardized interleaver profile, further logical transport channels may be transmitted via the same physical transmission channel. In this context, the first transport channel obviously is reduced in terms of data rate, so that the additional transport channels may actually obtain a transmission capacity that is needed accordingly. Interleaver profiles of the further logical transport channels are derived, to this end, from the interleaver profile of the first transport channel.

Abstract: A control system includes an error calculation module that receives a data bit pattern having a predetermined quantity of data bits and that calculates a binary vector based on a predetermined binary matrix and the data bit pattern. The error calculation module further determines the data bit pattern contains a corrupted data bit when the binary vector is not a predetermined value. The control system further includes a bit position module that receives the binary vector, that locates the corrupted data bit based on the binary vector and that corrects the data bit pattern. The bit position module receives the data bit pattern when the binary number is the predetermined value. The data bits are pre-assigned a base-10 value that corresponds to a data bit position.

Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.

Abstract: An apparatus and method for rate dematching in a communication system are provided. The apparatus includes an input sequence generator, an error calculator, and a puncture/repetition determiner. The input sequence generator calculates if current input data among data, which are input in interleaved sequence, corresponds to any nth sequence among before-interleaved sequence. The error calculator calculates an error for the current input data using the calculated sequence. The puncture/repetition determiner determines type of the current input data using the error for the current input data.

Abstract: A channel decoding apparatus and method in a communication system using Low-Density Parity-Check (LDPC) codes are provided in which an encoded signal is received from a transmitter and decoded using a parity-check matrix. At least one of input orders and output orders of the parity-check matrix are determined so that same values are not overlapped in a column direction between the at least one of the input orders and the output orders.

Abstract: A method of handling packet loss uses errorcorrecting codes and block rearrangement. This method divides the original data stream into data blocks, then codes the blocks by errorcorrecting codes. After coding the blocks, rearranges the coding blocks for spreading original data into new blocks and then transmitting the new blocks. After receiving the transmitted blocks, reverserearrangs the received blocks and decode the blocks. Combine the decoded blocks into original data stream in the end.

Abstract: A method for encoding or decoding an LDPC code with variable code lengths is provided in an embodiment of the present invention. The method includes: obtaining a base exponential matrix of an LDPC code and grouping code lengths during construction of the base exponential matrix; correcting the base exponential matrix according to a grouping correction factor to obtain an exponential matrix of the group corresponding to the grouping correction factor; extending the exponential matrix by using an extension factor of a code length in the group to obtain an LDPC matrix corresponding to the code length; and implementing encoding or decoding by using the LDPC matrix.

Abstract: A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. An encoding part subjects transport data to a block encoding process to form block encoded data. A modulating part modulates the block encoded data to form data symbols; and an arranging (interleaving) part arranges (interleaves) the block encoded data in such a manner that the intra-block encoded data of the encoded blocks, which include their respective single different data symbol, get together, and then supplies the arranged (interleaved) block encoded data to the modulating part. In this way, there can be provided a transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Abstract: Method, relay node and computer program product for processing transport packets, the transport packets conveying: (i) data stream units forming a data stream, and (ii) correction data units relating to the data stream units, where each transport packet contains information identifying the content of units in that transport packet. Transport packets are received at the relay node, the data stream units in the transport packets received at the relay node being insufficient to constitute the data stream. At least some of the correction data units and the data stream units in the received transport packets are used to generate substitute data stream units thereby to substantially recover the data stream at the relay node. The relay node packetises the data stream units of the substantially recovered data stream with correction data units to form output transport packets for transmission from the relay node, and then the output transport packets are transmitted from the relay node.

Abstract: A method of encoding a bit sequence over a Physical Downlink Control Channel (PDCCH) having Downlink Control Information (DCI) including: determining DCI bits to provide a DCI bit sequence; performing a CRC calculation on the DCI bit sequence to provide a CRC parity bit sequence; scrambling the CRC parity bit sequence to provide a scrambled CRC bit sequence; if the DCI format is LTE-A, further scrambling the DCI together with the attached scrambled CRC bit sequence to provide a LTE-A scrambled bit sequence; channel coding either the DCI attached scrambled CRC bit sequence or LTE-A scrambled bit sequence to provide a channel coded bit sequence; modulating the channel coded bit sequence to provide a modulated symbol sequence; layer mapping the modulated symbol sequence to one or more antennas associated with a transmitter to provide one or more layers having a symbol sequence; and precoding the layered symbol sequences.