Error Detection Or Correction Of The Data By Redundancy In Hardware (epo) Patents (Class 714/E11.054)

  • Publication number: 20120239993
    Abstract: The present invention provides various circuits for injecting faults into a larger circuit, sometimes called circuit under test, or CUT. One type of fault injection circuit is a clock controlled fault injection circuit. This type of circuit uses internal scan chains as a way by which a fault injection operation is performed while a system clock is in the off state. Another type of fault injection circuit is a concurrent fault injection circuit. This type of fault injection circuit uses dedicated fault injection scan chains in parallel with or without internal scan chains. Yet another type of fault injection circuit is a hybrid fault injection circuit that uses both clock controlled and concurrent fault injection circuits. Other embodiments are disclosed and still other embodiments would be obvious to those of ordinary skill in the art upon understanding the full scope of the present disclosure.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 20, 2012
    Applicant: EIGENIX
    Inventor: Sung Soo Chung
  • Publication number: 20120240006
    Abstract: A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells.
    Type: Application
    Filed: May 27, 2011
    Publication date: September 20, 2012
    Applicant: STEC, Inc.
    Inventors: Xinde Hu, Anthony D. Weathers, Richard D. Barndt
  • Publication number: 20120233496
    Abstract: Embodiments are directed to establishing a fault tolerant parallel database system and to detecting the health of parallel database services. In an embodiment, a computer system establishes a control node cluster that includes at least one active control node and at least one spare control node. Each node of the control node cluster includes specific functions assumable only by other control nodes. The computer system also establishes a compute node cluster that includes at least one active computing node, at least one spare computing node, at least one active storage node and at least one spare storage node. Each of the computing and storage nodes includes specific functions assumable only by other computing and storage nodes. The computer system detects a failure of an active node and instantiates a corresponding spare node that is configured to perform the functions of the failed active node.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 13, 2012
    Applicant: MICROSOFT CORPORATION
    Inventors: German A. Gil, Yunsheng He, Dale S. Grinnell, Paul Herman Dyke, Subhankar Aich, Ruwen Henning Hess
  • Publication number: 20120226963
    Abstract: Bad block management for flash memory including a method for storing data. The method includes receiving a write request that includes write data. A block of memory is identified for storing the write data. The block of memory includes a plurality of pages. A bit error rate (BER) of the block of memory is determined and expanded write data is created from the write data in response to the BER exceeding a BER threshold. The expanded write data is characterized by an expected BER that is lower than the BER threshold. The expanded write data is encoded using an error correction code (ECC). The encoded expanded write data is written to the block of memory.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Bivens, Michele M. Franceschini, Ashish Jagmohan
  • Patent number: 8249728
    Abstract: Methods for operating a management system that manages a large number of first function modules and second function modules. An inhibitor module I sets first control statuses to designating blocking when associated events are detected by an event detecting device, and then the management system no longer makes associated first function modules available for execution. The inhibitor module I sets second control statuses to designating executable when associated events are detected by an event detecting device, and then the management system makes associated second function modules available for execution.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: August 21, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Bernd Kesch, Hans Hillner, Matthias Knirsch, Alexander Hinz
  • Publication number: 20120210176
    Abstract: A method for controlling an information processing apparatus including a processor and a plurality of hardware units, the method has detecting, with the processor, an abnormal state of a hardware unit among the plurality of hardware units in the information processing apparatus, obtaining identification information of the hardware unit having abnormality, generating abnormality identification information on the basis of the identification information, recording a log of an execution process executed by the processor, assigning the abnormality identification information to the log of the execution process recorded at a time when the abnormal state of the hardware unit is detected, and outputting the log of the execution process to which the abnormality identification information has been assigned.
    Type: Application
    Filed: April 24, 2012
    Publication date: August 16, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Yasuo SUZUKI
  • Publication number: 20120210180
    Abstract: A read value that is read from a multi-level storage device is received, as are a set of bins having bin ranges and (for each of the bins in the set) a corresponding portion of read values which fall into that particular bin. One or more of the bin ranges is adjusted such that the received portions of read values remain substantially the same after adjustment and after assignment of the read value to one of the set of bins after adjustment.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Applicant: LINK_A_MEDIA DEVICES CORPORATION
    Inventors: Marcus Marrow, Jason Bellorado, Rajiv Agarwal
  • Publication number: 20120198269
    Abstract: Embodiments of the invention relate to block layout and block allocation in a file system to support transparency of application processing. At least one copy of an application is replicated in a write affinity region of a secondary server, and at least one copy of the application is replicated in a wide striping region across a cluster file system. When the application is subject to failure, application processing is transferred from the failure location to the write affinity copy. At the same time, the failed application is rebuilt using the wide striping replication of the application. Once the application is rebuilt, processing may return to the failed location employing the rebuilt application.
    Type: Application
    Filed: January 27, 2011
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karan Gupta, Reshu Jain, Himabindu Pucha, Prasenjit Sarkar, Dinesh K. Subhraveti
  • Publication number: 20120192276
    Abstract: Provided are a computer program product, system, and method for selecting one of a plurality of scanner nodes to perform scan operations for an interface node receiving a file request. A list includes a plurality of scanner nodes in a network and for each scanner node a performance value. A file request is received with respect to a file. In response to the file request, one of the scanner nodes in the list is selected based on the performance values of the scanner nodes. The file is transmitted to the selected scanner node to perform a scan operation with respect to the file. Indication is received from the selected scanner node performing the scan operation whether a subset of code in the file matches code in a definition set. The file request is processed to result in execution of the file request based on the indication of whether the subset of code in the file matches a definition in the definition set.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin L. Andrews, David A. Brettell, Anthony J. Ciaravella, Bruce D. Lucas
  • Publication number: 20120166911
    Abstract: According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller configured to control data input and output to and from nonvolatile memories for channels. The encoding module configured to generate encoded data for an interchannel error correction process, using data stored in each of the nonvolatile memories. The data controller configure to manage the encoded data in units of logical blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to planes of the same channel in each logical block.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 28, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kyosuke Takahashi, Motohiro Matsuyama
  • Publication number: 20120166891
    Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Eric J. Dahlen, Glenn J. Hinton, Raj K. Ramanujan
  • Publication number: 20120159242
    Abstract: A method including requesting access to a resource governed by a spinlock; determining an allocation of the resource to a further requester; determining an expiration of a time limit for the spinlock, if the resource is allocated to the further requester; and initiating a fault recovery, if the time limit is expired.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 21, 2012
    Inventors: Raymond RICHARDSON, Gregory Stults
  • Publication number: 20120151249
    Abstract: A connection state system is described herein that allows a client to resume a connection with a server or a different replacement server by remotely storing client state information in association with a resume key. The system provides a resume key filter operating at the server that facilitates the storing of volatile server state information. The state information can include information such as oplocks, leases granted to a client, and in-flight operations on a file handle. The resume key filter driver sits above the file system, which allows multiple file access protocols to use the filter. Upon a failover event, such as a server going down or losing connectivity to a client, the system can bring up another server or the same server and reestablish state for file handles held by various clients using the resume key filter.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 14, 2012
    Applicant: Microsoft Corporation
    Inventors: Paul R. Swan, Mathew George, David M. Kruse, Roopesh C. Battepati, Michael C. Johnson
  • Publication number: 20120144233
    Abstract: Embodiments comprise a plurality of computing devices that dynamically intercept process application I/O errors. Various embodiments comprise two or more computing devices, such as two or more servers, each having access to a shared data storage system. An application may be executing on the first computing device and performing an I/O operation when an I/O error occurs. The first computing device may intercept the I/O error, rather than passing it back to the application, and prevent the error from affecting the application. The first computing device may complete the I/O operation, and any other pending I/O operations not written to disk, via an alternate path, perform a checkpoint operation to capture the state of the set of processes associated with the application, and transfer the checkpoint image to the second computing device. The second computing device may resume operation of the application from the checkpoint image.
    Type: Application
    Filed: December 1, 2010
    Publication date: June 7, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas J. Griffith, Angela A. Jaehde, Somasundaram Krishnasamy, Stephen A. Schlachter
  • Publication number: 20120144230
    Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: PATRICK A. BUCKLAND, JAY R. HERRING, GREGORY M. NORDSTROM, WILLIAM A. THOMPSON
  • Publication number: 20120131377
    Abstract: Techniques are provided for establishing a Virtual Desktop Interface (VDI) connection at a virtual desktop thin client (VDTC) device, between a VDI client in the VDTC device and a VDI server in a hosted virtual desktop server (HVDS). A unified communications (UC) control connection is established between a UC protocol stack on the VDTC device and a primary call agent, where the UC control connection is configured to allow the UC protocol stack to register with the primary call agent, and to send or receive commands from the primary call agent that are based on signals from a UC control application running on the HVDS. A UC control backup application is started on the virtual desktop thin client device in a standby mode that is configured to switch to an active mode in response to a failure to establish or maintain the UC control connection, or a failure to establish or maintain the VDI connection.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 24, 2012
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Randall Bernard Baird, J. Steven Mayer
  • Publication number: 20120124413
    Abstract: A method and system for network element recovery are provided. In one form, frontend servers intelligently proxy error or unavailability messages returned by backend servers and simulate frontend server failure. In at least one form, the frontend server also includes intelligence or logic to determine that directing the client to recover service to an alternate system or site would assure better service availability, reliability, and/or quality-of-experience for the client.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Inventors: Eric Bauer, Daniel W. Eustace, Randee Susan Adams
  • Publication number: 20120110400
    Abstract: A universal memory interface on an integrated circuit includes an external memory interface unit operable to perform data rate conversion for a data signal between a first rate associated with the integrated circuit and a second rate associated with a memory system. The universal memory interface also includes a sequencer unit operable to calibrate at least one of a delay for the data signal and a delay for a strobe for the data signal by executing a calibration procedure instruction.
    Type: Application
    Filed: December 3, 2010
    Publication date: May 3, 2012
    Applicant: Altera Corporation
    Inventors: Valavan Manohararajah, Ivan Bluno, Przemek Guzy, Kalen B. Brunham
  • Publication number: 20120096304
    Abstract: A mechanism is provided in a storage control unit in a data processing system for providing unsolicited global disconnect requests to users. The mechanism stores lock control data in the storage control unit. The storage control unit allocates its resources into a plurality of clusters. Responsive to a given user connecting to a given partition that is for a logical subsystem resident on a first cluster within the plurality of clusters, the mechanism sends reflected partition information from the first cluster to a second cluster within the plurality of clusters. Responsive to the first cluster experiencing a failure condition, the mechanism moves control data from one or more logical subsystems from the first cluster to the second cluster and for each logical subsystem that moved from the first logical subsystem to the second logical subsystem and that has reflected partition information, presents unsolicited status to one or more users.
    Type: Application
    Filed: October 13, 2010
    Publication date: April 19, 2012
    Applicant: International Business Machines Corporation
    Inventors: Brian D. Clark, Juan A. Coronado, Christopher D. Filachek, Beth A. Peterson
  • Publication number: 20120089877
    Abstract: When write request signal is input from a host device 10, an SSD 20 inputs data input from the host device 10 in an encoder 30 sequentially and controls a RRAM 24 to store data output from the encoder 30. When size of data stored in the RRAM 24 reaches predetermined size Sref, the SSD 20 controls the RRAM 24 to read out data of size of the predetermined size Sref, inputs read data from the RRAM 24 in the encoder 32, and controls a flash memory 22 to store data output from the encoder 32. This configuration accomplishes the increase of the data write speed and improvement of reliability of the data.
    Type: Application
    Filed: September 8, 2011
    Publication date: April 12, 2012
    Applicant: THE UNIVERSITY OF TOKYO
    Inventors: Ken TAKEUCHI, Mayumi FUKUDA, Kazuhide HIGUCHI
  • Publication number: 20120079333
    Abstract: A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits.
    Type: Application
    Filed: December 7, 2011
    Publication date: March 29, 2012
    Applicant: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Publication number: 20120066552
    Abstract: A trace circuit 8 is configured to generate a stream of trace data elements indicative of processing operations performed by a processing circuit 4. The trace circuit 8 has a plurality of reference address registers 30-1 configured to store corresponding reference addresses. When the processing circuit 4 performs a processing operation associated with an associated memory address, the trace circuit 8 selects one of the reference address registers 30-1 as a selected reference address register, and generates a trace data element indicating: (i) which of the reference address registers 30-1 is the selected reference address register, and (ii) a difference, if any, between the associated memory address and the reference address of the selected reference address register. A diagnostic apparatus 20 for analysing the trace stream has a similar set of reference address registers 30-2 which are used to reconstruct the associated memory address from the generated trace data element.
    Type: Application
    Filed: August 3, 2011
    Publication date: March 15, 2012
    Applicant: ARM LIMITED
    Inventors: Paul Anthony Gilkerson, John Michael Horley
  • Publication number: 20120060055
    Abstract: A method for responding to a failure of hardware locus of at a communication installation having a plurality of control apparatuses for controlling a plurality of processes distributed among a plurality of hardware loci, the hardware loci including at least one spare hardware locus, includes the steps of: (a) Shifting control of a failed process from an initial control apparatus to an alternate control apparatus located at an alternate hardware locus than the failed hardware locus. The failed process is a respective process controlled by the initial control apparatus located at the failed hardware locus. (b) Relocating the respective control apparatuses located at the failed hardware locus to a spare hardware locus. (c) Shifting control of the failed process from the alternate control apparatus to the initial control apparatus relocated at the spare hardware locus.
    Type: Application
    Filed: November 15, 2011
    Publication date: March 8, 2012
    Applicant: ROCKSTAR BIDCO, LP
    Inventor: Sandeep Mehta
  • Publication number: 20120030503
    Abstract: A system and method is provided for ensuring high availability for a distributed application. A management object manages multiple scenarios defined for protection units associated with a distributed application. The management object may coordinate various operations performed at the protection units based on management object configuration information.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 2, 2012
    Inventors: Guodong Li, Hailin Peng, Zhenghua Xu, Ran Shuai
  • Publication number: 20120030510
    Abstract: A hard disk drive that is coupled to a non-volatile memory. The non-volatile memory includes data that was designated to be stored in the hard disk drive in a previous time period. When a power loss event is detected the hard disk drive stores the track address of the last written track in non-volatile memory. When power is returned, the hard drive retrieves the last track address from the non-volatile memory. The data can then be rewritten onto the last track. Such an approach allows relatively large sectors of 4 Kbytes to be recaptured after a power loss event.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 2, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Ken Hong
  • Publication number: 20120017122
    Abstract: A process control system is provided having a plurality of I/O devices in communication using a bus. A primary redundant I/O device and a secondary redundant I/O device are coupled to the bus, where the secondary redundant I/O device is programmed to detect a primary redundant I/O device fault. The secondary redundant I/O device, upon detecting the primary redundant I/O device fault, publishes a primary redundant I/O device fault message on the bus. The controller may deactivate the primary redundant I/O device and activate the secondary redundant I/O device responsive to the primary redundant I/O device fault message.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Applicant: FISHER-ROSEMOUNT SYSTEMS, INC.
    Inventors: Michael D. Apel, Steven Dienstbier
  • Publication number: 20110296233
    Abstract: A computer which takes over a task managed by a server apparatus from another computer which occupies the task, the computer including, a processor to detect an error of the other computer, to transmit, when an error of the another computer is detected, a task relaying request for taking over the task to the server apparatus, and to allow when a permission of the takeover of the task is received from the server apparatus processes of application programs in standby states in the computer to occupy the task.
    Type: Application
    Filed: May 23, 2011
    Publication date: December 1, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Kazuki AKITA, Takeshi YAMAZAKI, Daisuke SHIMABAYASHI
  • Publication number: 20110264962
    Abstract: A method begins by a processing module generating a payload of a dispersed storage network frame by generating a transaction number field including a transaction number and generating one or more slice payload sections, wherein each slice payload section includes a slice name field to include a slice name corresponding to an encoded data slice, a last known slice revision numbering field including a last known revision number of the slice name, a new slice revision numbering field including a new revision number of the slice name, a slice length field including a length of the encoded data slice, and a slice payload field including the encoded data slice. The method continues with the processing module generating a protocol header including a payload length field and remaining fields of the protocol header.
    Type: Application
    Filed: April 5, 2011
    Publication date: October 27, 2011
    Applicant: CLEVERSAFE, INC.
    Inventors: Andrew Baptist, Wesley Leggette, Jason K. Resch
  • Publication number: 20110264950
    Abstract: A method begins by a processing module generating a payload section of a dispersed storage network (DSN) frame regarding a check request operation by generating one or more slice name fields of the payload section to include one or more slice names corresponding to one or more encoded data slices and generating a transaction number field of the payload section to include a transaction number corresponding to the check request operation. The method continues with the processing module generating a protocol header of the DSN frame by generating a payload length field of the protocol header to include a payload length that represents a length of the payload section and generating remaining fields of the protocol header.
    Type: Application
    Filed: April 5, 2011
    Publication date: October 27, 2011
    Applicant: CLEVERSAFE, INC.
    Inventors: Andrew Baptist, Wesley Leggette, Jason K. Resch, Zachary J. Mark, Ilya Volvovski, Greg Dhuse
  • Publication number: 20110264949
    Abstract: A disk array provided with a RAID group in a Redundant Array of Inexpensive Disks (RAID) configuration with redundancy of two, the disk array includes, a data recovery technique selecting unit to select a technique for recovering data from a first failed disk to be recovered first, the technique being selected from among a plurality of techniques based on the type of storage apparatus included in the RAID group, and I/O conditions with respect to the RAID group, when failures occur in two storage apparatus in the RAID group, a data recovering unit to split recovered data from the first failed storage apparatus and writing the recovered data to two recovery storage apparatus in accordance with the data recovery technique selected by the data recovery technique selecting unit, and an aggregating unit to aggregate the recovered data onto one of the two recovery storage apparatus.
    Type: Application
    Filed: October 18, 2010
    Publication date: October 27, 2011
    Applicant: Fujitsu Limited
    Inventors: Kazuhiko IKEUCHI, Mikio Ito, Hidejirou Daikokuya, Chikashi Maeda
  • Publication number: 20110258485
    Abstract: A central hub is coupled to a plurality of computational devices. The central hub stores a data structure that grants locks for accessing common data stored at the central hub, wherein the common data is shared by the plurality of computational devices. Each computational device maintains locally those locks that are held by the computational device in the data structure stored at the central hub. In response to a failure of the data structure stored at the central hub, a selected computational device of the plurality of computational devices is determined to be a manager system. Other computational devices besides the manager system communicate to the manager system all locks held by the other computational devices in the data structure stored at the central hub. The data structure and the common data are generated and stored at the manager system. Transactions are performed with respect to the data structure stored at the manager system, until the data structure stored at the central hub is operational.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas Lee Lehr, Franklin Emmert McCune, David Charles Reed, Max Douglas Smith
  • Publication number: 20110246820
    Abstract: The present invention is related to a microcomputer mutual monitoring system in which mutual monitoring is performed between a first microcomputer 11 and a second microcomputer 12, characterized in that if a reset of the second microcomputer is performed due to an occurrence of an abnormal event in the second microcomputer, the monitoring of the first microcomputer is performed by an alternative monitoring function 142 incorporated in the first microcomputer instead of the monitoring of the first microcomputer by a monitoring function of the second microcomputer during the reset. With this arrangement, the microcomputer mutual monitoring system, which can prevent reduced marketability while maintaining reliability as a system, can be obtained.
    Type: Application
    Filed: March 18, 2010
    Publication date: October 6, 2011
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaaki Murao
  • Publication number: 20110239053
    Abstract: A method for diagnosing a control system for a stacked battery is disclosed. The control system comprises a plurality of processors, a plurality of controllers, and a monitoring unit (control unit). The method comprises sending a diagnostic information from the central unit to a top processor of the plurality of processors, transmitting a return information from the top processor of the plurality of processors to the central unit, comparing the diagnostic information sent from the central unit with the return information received by the central unit, and indicating a communication problem if the diagnostic information sent from the central unit is different from the return information received by the central unit. The steps are repeated by eliminating the top processor from a previous cycle and assigning a new top processor if there is no problem with the reconfigurable communication system.
    Type: Application
    Filed: June 7, 2011
    Publication date: September 29, 2011
    Applicant: O2MICRO, INC.
    Inventors: Guoxing Li, Xiaojun Zeng, Anquan Xiao, Xiaohua Hou
  • Publication number: 20110239308
    Abstract: Systems and methods for vetting data include receiving a notification at a second processor that a first processor has written first output data to an output data buffer in an output device. A hardware-implemented buffer access flag controls a permission for the first processor to write data to the output data buffer. The second processor sets the hardware-implemented buffer access flag to a first setting that prevents the first processor from writing additional output data to the output data buffer while the first output data in the output data buffer is being inspected. The second processor has a read-write permission to the hardware-implemented buffer access flag. The first processor has a read-only permission to the hardware-implemented buffer access flag.
    Type: Application
    Filed: March 29, 2010
    Publication date: September 29, 2011
    Applicant: MOTOROLA, INC.
    Inventors: Kenneth C. Fuchs, Brian W. Pruss, Gary W. Schluckbier
  • Publication number: 20110231739
    Abstract: A composite semiconductor memory device, comprising: a plurality of nonvolatile memory devices; and an interface device connected to the plurality of nonvolatile memory devices and for connection to a memory controller, the interface device comprising an error correction coding (ECC) engine. Also, a memory system, comprising: a memory controller; and at least one composite semiconductor memory device configured for being written to and read from by the memory controller and comprising a built-in error correction coding (ECC) engine.
    Type: Application
    Filed: March 2, 2011
    Publication date: September 22, 2011
    Inventor: Jin-Ki KIM
  • Publication number: 20110231713
    Abstract: Logical/physical conversion information is configured from first conversion information and second conversion information. A controller of a flash memory module restores the first conversion information at boot up time, enables an access command to be received from a host after having restored the first conversion information, and restores the second conversion information after an access command is able to be received.
    Type: Application
    Filed: November 4, 2009
    Publication date: September 22, 2011
    Applicant: HITACHI, LTD.
    Inventors: Masanori Takada, Jun Kitahara
  • Publication number: 20110225450
    Abstract: A file directory system comprises a directory file, a directory address for the directory file, and a directory address failsafe mechanism. The directory file includes one or more directory entries and one or more corresponding addresses for the one or more directory entries. The directory address failsafe mechanism functions to dispersed storage error encode the directory address to produce a plurality of encoded components of the directory address and transmit the plurality of encoded components of the directory address to a plurality of agent modules.
    Type: Application
    Filed: February 4, 2011
    Publication date: September 15, 2011
    Applicant: CLEVERSAFE, INC.
    Inventors: S. Christopher Gladwin, Gary W. Grube, Jason K. Resch, Timothy W. Markison
  • Publication number: 20110197101
    Abstract: A semiconductor device includes a first management area storing a plurality of inspection results, the plurality of inspection results being obtained by executing inspections for each of a plurality of storage areas which store a plurality of data; and a second management area storing the plurality of inspection results. The first and second management areas are independent from each other.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 11, 2011
    Inventor: Shin ITO
  • Publication number: 20110191639
    Abstract: Provided are a storage system and its control method having superb functionality of being able to notify an administrator of the extent of impact of a pool fault in an easy and prompt manner. The foregoing storage system and its control method manage a storage area provided by a storage medium by dividing it into multiple pools, provide a virtual logical device to a host system, dynamically allocate a storage area to the logical device according to a data write request from the host system for writing data into the logical device, move data that was written into the logical device to another pool according to the access status from host system to such data, identify, when a fault occurs in any one of the pools, an extent of impact of the fault based on the correspondence relationship of the logical device and the pool, and notify the identified extent of impact of the fault to an administrator.
    Type: Application
    Filed: September 2, 2009
    Publication date: August 4, 2011
    Applicant: HITACHI, LTD.
    Inventors: Daisuke Shinohara, Yukinori Sakashita
  • Publication number: 20110191641
    Abstract: A RAID device has a plurality of HDDs for a RAID configuration and controls the RAID configuration. The RAID device has a host that performs various data processes on the HDDs and a control unit that controls communication with the HDDs. With this configuration, if an initialization process for assigning physical addresses unique to the HDDs is performed, the RAID device receives initialization frames from the HDDs. Then, the RAID device detects abnormality of the HDDs in accordance with information contained in the received initialization frames.
    Type: Application
    Filed: January 21, 2011
    Publication date: August 4, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Hiroki TASHIMA
  • Publication number: 20110154106
    Abstract: In accordance with various aspects of the disclosure, a method and apparatus are disclosed that includes aspects of monitoring a first processor of a computer by a monitoring module for a first processor instability; determining if the first processor is stable based on the monitored first processor instability; routing operational priority to a second processor of the computer through a multiplexer module if the first processor is determined not to be stable, wherein a first desktop management interface of the first processor and a second desktop management interface of the second processor are in communication with the multiplexer module and wherein the first processor and the second processor are in communication by a processor interconnect; and operating the computer using the second processor.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Inventors: Brian KELLY, Michael Kasper
  • Publication number: 20110154101
    Abstract: A controller is used to provide a sharable, programmable and composable infrastructure. The controller includes a user manager to take input of user application programming interface calls that correspond to actions accepted from users. A physical manager fulfills requests from the user manager by manipulating distributed physical resources and logical devices in a network controlled by the controller. A configuration effector implements configuration changes to the physical resources and logical devices. A device monitor determines a status of the physical resources and logical devices, propagates the status to the physical manager for detecting a failure of the physical resources and logical devices in real-time, and mitigates the failure.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Applicant: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Jacobus Van Der MERWE, Xu CHEN
  • Publication number: 20110145634
    Abstract: An apparatus and method for automatically recovering a hardware when the hardware is not accessible from the processing unit. The hardware is recovered via a path different from a path which the processing unit uses when the processing unit fails to access to the hardware via the path initially used.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 16, 2011
    Applicant: NEC CORPORATION
    Inventor: Yoji TABUCHI
  • Publication number: 20110125889
    Abstract: The distributed virtual SAN infrastructure provides a plurality of host systems with a scalable dynamically expandable distributed virtual storage pool, which includes a virtual storage automatic construct protocol. The distributed virtual SAN infrastructure includes one or more SAN units including IP SAN unit and Fiber Channel SAN unit, the management console, the distributing control management station and the network infrastructure, wherein the network infrastructure provides the communication links between all systems in this distributed virtual SAN.
    Type: Application
    Filed: November 12, 2010
    Publication date: May 26, 2011
    Inventor: Sheng Tai (Ted) Tsao
  • Publication number: 20110099419
    Abstract: A method for flash sparing on a solid state drive (SSD) includes detecting a failure from a primary memory device; determining if a failure threshold for the primary memory device has been reached; and, in the event the failure threshold for the primary memory device has been reached: quiescing the SSD; and updating an entry in a sparing map table to replace the primary memory device with a spare memory device.
    Type: Application
    Filed: October 23, 2009
    Publication date: April 28, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregg S. Lucas, Gary A. Tressler, Dustin J. Vanstee, Andrew D. Walls
  • Publication number: 20110099320
    Abstract: A method for adjusting a drive life and a capacity of a solid state drive (SSD), the SSD comprising a plurality of memory devices includes determining a desired drive life for the SSD; determining a utilization for the SSD; and allocating a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization. An SSD with an adjustable drive life and capacity includes a plurality of memory devices; and a memory allocation module configured to: determine a desired drive life for the SSD; determine a utilization for the SSD; and allocate a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization.
    Type: Application
    Filed: October 23, 2009
    Publication date: April 28, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregg S. Lucas, Gary A. Tressler, Dustin J. Vanstee
  • Publication number: 20110093742
    Abstract: A storage apparatus connected to a storage device includes a storage module, a memory for storing data to be copied to the storage device, buffers for temporarily saving the data, redundantly, the saved data stored in one of the buffers being recoverable by the data stored in the rest of the buffers, and a control module for executing, storing the data of write request to the storage module and the memory, copying the data to the storage device, saving the data to the buffer when an using rate of the memory is greater than a predetermined rate, writing the saved data stored in the buffer to the memory when an using rate of the memory is not greater than the predetermined rate, detecting a failure of the buffers, and rebuilding the saved data stored in the one of the buffers based on an using state of the buffers.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 21, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Yoshinari SHINOZAKI
  • Publication number: 20110087915
    Abstract: Peer-to-peer multicasting of streaming data in a node in a peer-to-peer computer environment. A transmission of packets is received at the node, wherein the packets are data packets pushed from a parent node and comprises data of a sub stream of the streaming data. A buffer map of the node is created at the node, wherein the buffer map lists the packets that have been received and an available bandwidth of the node. The node is connected with at least one neighboring node. The buffer map of the node is exchanged with a buffer map of the at least one neighboring node. Provided a determination is made that at least one packet in the sub stream of the streaming data was not received at the node, the at least one packet is pulled from the at least one neighboring.
    Type: Application
    Filed: October 9, 2009
    Publication date: April 14, 2011
    Inventors: Meng ZHANG, Pierpaolo Baccichet
  • Publication number: 20110083036
    Abstract: Methods of recovering data lost by a server, and/or facilitating a recovery of data lost by a server, as well as systems for recovering (and/or facilitating the recovery of) data lost by a server, are disclosed herein. In some embodiments, the method includes receiving a data map pertaining to the lost data from one or both of a second server (which can be, for example, a master server) and a mobile device, and obtaining application data from the data map. The method further includes, based upon the application data, accessing one or more of the first mobile device, a second mobile device and a content provider website to obtain at least some of the lost data. Instead, or in addition, the lost data can be obtained from one or more mobile devices or other devices. In some such embodiments, the process can be initiated or governed by the second (e.g., master) server or a mobile device.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 7, 2011
    Applicant: MOTOROLA, INC.
    Inventors: Kamil Pawlowski, William Warren Bjorge
  • Publication number: 20110078526
    Abstract: A method and a circuit configuration for simulating fault states in a control unit, as well as a computer program and a computer-program product, are provided. In this context, a multiplexer and a fault-generating circuit are used, the multiplexer being realized using a relay technology, and the fault-generating circuit being implemented using a semiconductor technology.
    Type: Application
    Filed: January 16, 2007
    Publication date: March 31, 2011
    Inventors: Paul Mohr, Henrik Jakoby, Mathias Koehrer, Robert Geiselmann