Forming From Vapor Or Gaseous State (e.g., Vpe, Sublimation) Patents (Class 117/84)
  • Patent number: 7482037
    Abstract: A method of forming a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition process including a plurality of deposition cycles.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: January 27, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Donald L. Westmoreland, Stefan Uhlenbrock
  • Patent number: 7481881
    Abstract: Affords a method of manufacturing GaN crystal substrate in which enlargement of pit size in the growing of GaN crystal is inhibited to enable GaN crystal substrate with a high substrate-acquisition rate to be produced. The method of manufacturing GaN crystal substrate includes a step of growing GaN crystal (4) by a vapor growth technique onto a growth substrate (1), the GaN-crystal-substrate manufacturing method being characterized in that in the step of growing the GaN crystal (4), pits (6) that define facet planes (5F) are formed in the crystal-growth surface, and being characterized by having the pit-size increase factor of the pits (6) be 20% or less.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: January 27, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takuji Okahisa
  • Patent number: 7476487
    Abstract: Semiconductor nanocrystals surface-coordinated with a compound containing a photosensitive functional group, a photosensitive composition comprising semiconductor nanocrystals, and a method for forming semiconductor nanocrystal pattern by producing a film using the photosensitive semiconductor nanocrystals or the photosensitive composition, exposing the film to light and developing the exposed film, are provided. The semiconductor nanocrystal pattern exhibits luminescence characteristics comparable to the semiconductor nanocrystals before patterning and can be usefully applied to organic-inorganic hybrid electroluminescent devices.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: January 13, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Jin Park, Eun Joo Jang, Shin Ae Jun, Tae Kyung Ahn, Sung Hun Lee
  • Publication number: 20090007841
    Abstract: A vapor-phase growing apparatus and a vapor-phase growing method which reduce sticking of a wafer to a holder during vapor-phase growth are provided. In the vapor-phase growing apparatus, a holder arranged in a chamber includes a disk-like member having a recessed portion at the center of a holder or a ring-like member having a recessed portion at a center of a holder and having an opening in a bottom center of the holder. A first projecting portion is arranged on an inner circumference wall surface of the holder, and a second projecting portion is formed on a bottom surface of the recessed portion of the holder. In this manner, the holder can support a wafer with a small contact area. In vapor-phase growth, the wafer can be prevented from sticking to the holder.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 8, 2009
    Inventors: Hironobu Hirata, Hideki Arai
  • Patent number: 7473315
    Abstract: A low dislocation density AlxInyGa1-x-yN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing an AlxInyGa1-x-yN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: January 6, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Koji Uematsu
  • Patent number: 7465353
    Abstract: It is to provide a method for growing an epitaxial crystal in which the doping conditions are set when an epitaxial crystal having a desired carrier concentration is grown. A method for growing an epitaxial crystal while a dopant is added to a compound semiconductor substrate, comprises: obtaining a relation between an off angle and a doping efficiency with regards to the same type of compound semiconductor substrate in advance; and setting a doping condition for carrying out an epitaxial growth on the compound semiconductor substrate based on the obtained relation and a value of the off angle of the subtrate.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: December 16, 2008
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Manabu Kawabe, Ryuichi Hirano
  • Patent number: 7465354
    Abstract: A process, for patterning a thin film that is highly resistant to conventional etching processes and that is to be deposited at a high substrate temperature, is disclosed. The process uses a liftoff method wherein a refractory material has been substituted for the conventional organic resin. The method is particularly useful for the fabrication of tunable microwave devices and ferroelectric memory elements.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: December 16, 2008
    Assignee: National University of Singapore
    Inventors: Chong Kim Ong, Chin Yaw Tan
  • Patent number: 7459024
    Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described, as well as a system for use in performing such a method, and articles incorporating such a composition.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: December 2, 2008
    Assignee: Apollo Diamond, Inc.
    Inventors: Robert C. Linares, Patrick J. Doering
  • Publication number: 20080289570
    Abstract: This invention reduces planar defects which occur within a silicon carbide single crystal when a silicon carbide single crystal is epitaxially grown on a single crystal substrate. The process for producing a silicon carbide single crystal in which a silicon carbide single crystal layer is epitaxially grown on the surface of a single crystal substrate is a process in which a plurality of undulations that extend in a single, substantially parallel direction on the substrate surface is formed on the single crystal substrate surface; undulation ridges on the single crystal substrate undulate in the thickness direction of the single crystal substrate; and the undulations are disposed so that planar defects composed of anti-phase boundaries and/or twin bands that propagate together with the epitaxial growth of the silicon carbide single crystal merge with each other.
    Type: Application
    Filed: May 23, 2006
    Publication date: November 27, 2008
    Applicant: Hoya Corporation
    Inventors: Takamitsu Kawahara, Kuniaki Yagi, Naoki Hatta, Hiroyuki Nagasawa
  • Publication number: 20080289575
    Abstract: An improved method and apparatus for depositing a Group III-V for a hydride vapor phase epitaxy (HVPE) process are provided. In one embodiment, an apparatus for a hydride vapor phase epitaxy process may include an elongated body having a trough defined between a first and a second wall, a channel formed in the first wall configured to provide a gas to the trough, and an inlet port formed in the body coupled to the channel. In another embodiment, a method for a hydride vapor phase epitaxy process may include providing Group III metal liquid precursor in a container disposed in a chamber, flowing a halogen containing gas across the container to form a Group III metal halide vapor to a reacting zone in the chamber, and mixing the Group III metal halide vapor with a Group V gas supplied in the chamber in the reacting zone.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 27, 2008
    Inventors: Brian H. Burrows, Nyi O. Myo, Ronald Stevens, Jacob Grayson, Lori D. Washington, Sandeep Nijhawan
  • Patent number: 7455730
    Abstract: A method for producing a single crystal includes supplying a vapor gas from silicon carbide as a raw material to a seed crystal formed of a silicon carbide single crystal to grow the seed crystal. The seed crystal is disposed in a part of crystal growth, with a crystal face of the seed crystal inclined relative to a (0001) plane or (000-1) plane, thereby making crystal growth.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: November 25, 2008
    Assignee: Showa Denko K.K.
    Inventor: Naoki Oyanagi
  • Patent number: 7455729
    Abstract: The invention concerns a method for preparing gallium nitride films by vapour-phase epitaxy with low defect densities. The invention concerns a method for producing a gallium nitride (GaN) film from a substrate by vapour-phase epitaxy deposition of gallium nitride. The invention is characterized in that the gallium nitride deposition comprises at least one step of vapour-phase epitaxial lateral overgrowth, in that at least one of said epitaxial lateral overgrowth steps is preceded by etching openings either in a dielectric mask previously deposited, or directly into the substrate, and in that it consists in introducing a dissymmetry in the environment of dislocations during one of the epitaxial lateral overgrowth steps so as to produce a maximum number of curves in the dislocations, the curved dislocations not emerging at the surface of the resulting gallium nitride layer. The invention also concerns the optoelectronic and electronic components produced from said gallium nitride films.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: November 25, 2008
    Assignee: Lumilog
    Inventors: Bernard Beaumont, Pierre Gibart, Jean-Pierre Faurie
  • Patent number: 7449065
    Abstract: A method and the benefits resulting from the product thereof are disclosed for the growth of large, low-defect single-crystals of tetrahedrally-bonded crystal materials. The process utilizes a uniquely designed crystal shape whereby the direction of rapid growth is parallel to a preferred crystal direction. By establishing several regions of growth, a large single crystal that is largely defect-free can be grown at high growth rates. This process is particularly suitable for producing products for wide-bandgap semiconductors, such as SiC, GaN, AlN, and diamond. Large low-defect single crystals of these semiconductors enable greatly enhanced performance and reliability for applications involving high power, high voltage, and/or high temperature operating conditions.
    Type: Grant
    Filed: December 2, 2006
    Date of Patent: November 11, 2008
    Assignee: Ohio Aerospace Institute
    Inventors: J. Anthony Powell, Philip G. Neudeck, Andrew J. Trunek, David J. Spry
  • Publication number: 20080271667
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Application
    Filed: July 1, 2008
    Publication date: November 6, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Patent number: 7445671
    Abstract: A method of producing networks of low melting metal oxides such as crystalline gallium oxide comprised of one-dimensional nanostructures. Because of the unique arrangement of wires, these crystalline networks defined as “nanowebs”, “nanowire networks”, and/or “two-dimensional nanowires”. Nanowebs contain wire densities on the order of 109/cm2. A possible mechanism for the fast self-assembly of crystalline metal oxide nanowires involves multiple nucleation and coalescence via oxidation-reduction reactions at the molecular level. The preferential growth of nanowires parallel to the substrate enables them to coalesce into regular polygonal networks. The individual segments of the polygonal network consist of both nanowires and nanotubules of ?-gallium oxide. The synthesis of highly crystalline noncatalytic low melting metals such as ?-gallium oxide tubes, nanowires, and nanopaintbrushes is accomplished using molten gallium and microwave plasma containing a mixture of monoatomic oxygen and hydrogen.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: November 4, 2008
    Assignees: University of Louisville, University of Kentucky
    Inventors: Mahendra Kumar Sunkara, Shashank Sharma, Burtron H. Davis, Uschi M. Graham
  • Patent number: 7445672
    Abstract: Heat treatment is conducted at a predetermined temperature of not less than 1250° C. on an underlying substrate obtained by epitaxially forming a first group-III nitride crystal on a predetermined base as an underlying layer. Three-dimensional fine irregularities resulting from crystalline islands are created on the surface of the underlying layer. A second group-III nitride crystal is epitaxially formed on the underlying substrate as a crystal layer. There are a great many fine voids interposed at the interface between the crystal layer and underlying substrate. The presence of such voids suppresses propagation of dislocations from the underlying substrate, which reduces the dislocation density in the crystal layer. As a result, the crystal layer of good crystal quality can be obtained.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: November 4, 2008
    Assignees: NGK Insulators, Ltd., Dowa Mining Co., Ltd.
    Inventor: Tomohiko Shibata
  • Patent number: 7442253
    Abstract: The present invention is directed to a process for producing a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of agglomerated intrinsic point defects. The process either comprises exposing the wafer's front and back surfaces to different atmospheres, or thermally annealing two wafers in a face-to-face arrangement.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: October 28, 2008
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Joseph C. Holzer, Marco Cornara, Daniela Gambaro, Massimiliano Olmo, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
  • Publication number: 20080257256
    Abstract: Bulk GaN and AlGaN single crystal boules, preferably fabricated using a modified HVPE process, are provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth, for example to achieve n-, i-, or p-type conductivity.
    Type: Application
    Filed: June 19, 2008
    Publication date: October 23, 2008
    Inventors: Yuri V. MELNIK, Vitali Soukhoveev, Vladimir Ivantsov, Katie Tsvetkov, Vladimir A. Dmitriev
  • Patent number: 7438761
    Abstract: A hydrogen chloride gas and an ammonia gas are introduced with a carrier gas into a reactor in which a substrate and at least an aluminum metallic material through conduits. Then, the hydrogen gas and the ammonia gas are heated by heaters, and thus, a III-V nitride film including at least Al element is epitaxially grown on the substrate by using a Hydride Vapor Phase Epitaxy method. The whole of the reactor is made of an aluminum nitride material which does not suffer from the corrosion of an aluminum chloride gas generated by the reaction of an aluminum metallic material with a hydrogen chloride gas.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: October 21, 2008
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomohiko Shibata, Keiichiro Asai, Mitsuhiro Tanaka
  • Patent number: 7435297
    Abstract: A method for growing Group III nitride materials using a molten halide salt as a solvent to solubilize the Group-III ions and nitride ions that react to form the Group III nitride material. The concentration of at least one of the nitride ion or Group III cation is determined by electrochemical generation of the ions.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: October 14, 2008
    Assignee: Sandia Corporation
    Inventors: Karen E. Waldrip, Jeffrey Y. Tsao, Thomas M. Kerley
  • Publication number: 20080213543
    Abstract: A semiconductor compound material, preferably a III-N-bulk crystal or a III-N-layer, is manufactured in a reactor by means of hydride vapour phase epitaxy (HVPE), wherein in a mixture of carrier gases a flow profile represented by local mass flow rates is formed in the reactor. The mixture can carry one or more reaction gases towards a substrate. Thereby, a concentration of hydrogen important for the reaction and deposition of reaction gases is adjusted at the substrate surface independently from the flow profile simultaneously formed in the reactor.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 4, 2008
    Inventors: Gunnar Leibiger, Frank Habel, Stefan Eichler
  • Patent number: 7419888
    Abstract: In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a silicon-rich insulation layer on the object. A third gas including a second silicon compound is provided onto the silicon-rich insulation layer to form a silicon nanocrystalline layer on the silicon-rich insulation layer. The first gas, the second gas and the third gas may be repeatedly provided to alternately form the silicon-rich nanocrystalline structure having a plurality of silicon-rich insulation layers and a plurality of silicon nanocrystalline layers on the object.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: September 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Ryol Yang, Kyong-Hee Joo, In-Seok Yeo, Ki-Hyun Hwang, Seung-Hyun Lim
  • Publication number: 20080202409
    Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Application
    Filed: February 13, 2008
    Publication date: August 28, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
  • Patent number: 7416604
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: August 26, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Patent number: 7410923
    Abstract: A highly corrosion-resistant SiC material is formed on a base body by a CVD process. The SiC material contains ?-SiC crystals so oriented that the ratio of the sum of peak intensities of x-ray diffraction for (220) and (311) planes of the ?-Sic csystals to the sum of peak intensities of x-ray diffraction for (111), (200), (220), (311) and (222) planes Of the ?-SiC crystals is 0.15 or above. The SiC material may contain both ?-SiC crystals and ?-SiC crystals of 6H structure. A base body with a SiC material by a CVD process is used as an internal component member of a semiconductor device fabricating system.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: August 12, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Hayashi Otsuki, Satoru Nogami
  • Patent number: 7410539
    Abstract: The template type substrate is used for opto-electric or electrical devices and comprises A) a layer of bulk mono-crystal nitride containing at least one element of alkali metals (Group I, IUPAC 1989) and B) a layer of nitride grown by means of vapor phase epitaxy growth wherein the layer A) and the layer B) are combined at non N-polar face of the layer A) and N-polar face of the layer B). Therefore, the template type substrate has a good dislocation density and a good value of FWHM of the X-ray rocking curve from (0002) plane less than 80, so that the resulting template type substrate is very useful for the epitaxy substrate from gaseous phase such as MOCVD, MBE and HVPE, resulting in possibility of making good opto-electric devices such as Laser Diode and large-output LED and good electric devices such as MOSFET.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: August 12, 2008
    Assignees: Ammono Sp. z o.o., Nichia Corporation
    Inventors: Robert Dwilinski, Roman Doradzinski, Jerzy Garczynski, Leszek Sierzputowski, Yasuo Kanbara
  • Publication number: 20080182092
    Abstract: Bulk single crystal of aluminum nitride (AlN) having an a real planar defect density?100 cm?2 Methods for growing single crystal aluminum nitride include melting an aluminum foil to uniformly wet a foundation with a layer of aluminum, the foundation forming a portion of an AlN seed holder, for an AlN seed to be used for the AlN growth. The holder may consist essentially of a substantially impervious backing plate.
    Type: Application
    Filed: January 17, 2008
    Publication date: July 31, 2008
    Applicant: Crystal IS, Inc.
    Inventors: Robert T. Bondokov, Kenneth E. Morgan, Leo J. Schowalter, Glen A. Slack
  • Patent number: 7404858
    Abstract: A method for epitaxial growth of silicon carbide using chemical vapor deposition (CVD) is provided. This method utilizes halogenated carbon precursors and control of the gas-phase interaction of halogen-containing intermediate chemical products involving silicon and carbon, which ensures quality and homogeneity across the silicon carbide crystals. It also ensures a possibility to achieve device-quality epitaxial layers at lower growth temperatures as well as on on-axis or low off-angle substrate surfaces. The growth method can be applied to forming SiC device regions of desirable shape and dimensions by restricting the growth into windows formed in non-silicon carbide region on the top of SiC substrate. Application of the methods described herein will greatly benefit the production of high quality silicon carbide materials and devices.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: July 29, 2008
    Assignee: Mississippi State University
    Inventor: Yaroslav Koshka
  • Publication number: 20080176386
    Abstract: A method of producing a separated GaN crystal body grown by vapor phase epitaxy on a substrate made of material different from GaN is provided. In this method, a nitride deposit is formed during the growth on a periphery of the substrate and GaN crystal body. The present method comprises the steps of: processing the periphery of the substrate to remove the nitride deposit; and, after the peripheral processing, separating the substrate from the GaN crystal body to make the substrate and the GaN crystal body independent of each other.
    Type: Application
    Filed: January 22, 2007
    Publication date: July 24, 2008
    Inventor: Masahiro Nakayama
  • Patent number: 7402206
    Abstract: A method of synthesizing or growing a compound having the general formula Mn+1AXn(16) where M is a transition metal, n is 1, 2, 3 or higher, A is an A-group element and X is carbon, nitrogen or both, which comprises the step of exposing a substrate to gaseous components and/or components vaporized from at least one solid source (13, 14, 15) whereby said components react with each other to produce the Mn+1AXn (16) compound.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: July 22, 2008
    Assignee: ABB AB
    Inventors: Peter Isberg, Jens-Petter Palmquist, Ulf Jansson, Lars Hultman, Jens Birch, Timo Seppänen
  • Publication number: 20080171133
    Abstract: The invention relates to a method for producing c-plane GaN substrates or AlxGa1-xN substrates using an original substrate. Said method is characterized by the following steps: a tetragonal (100)-oriented or (?100)-oriented original LiAlO2 substrate is used; said original substrate is nitrided in a nitrogen compound-containing atmosphere at temperatures lying below the decomposition temperature of LiAlO2; a nucleation layer is grown at temperatures ranging between 500° C. and 700° C. by adding GaCl or AlCl or a mixture of GaCl and AlCl in a nitrogen compound-containing atmosphere; single-crystalline c-plane-oriented GaN or AlxGa1-xN is grown on the nucleation layer at temperatures ranging between 900° C. and 1050° C. by means of hydride vapor phase epitaxy (HVPE) with GaCl or AlCl or a GaCl/AlCl mixture in a nitrogen compound-containing atmosphere; and the substrate is cooled.
    Type: Application
    Filed: January 18, 2006
    Publication date: July 17, 2008
    Applicant: Freiberger Compound Materials GMBH
    Inventors: Eberhard Richter, Gunther Trankle, Markus Weyers
  • Patent number: 7399357
    Abstract: A method for the controlled growth of thin films by atomic layer deposition by making use of multilayers and using energetic radicals to facilitate the process is described in this invention. In this method, a first reactant is admitted into the reaction chamber volume, where there is a substrate to be coated. This first reactant then adsorbs, in a self-limiting process, onto the substrate to be coated. After removing this first reactant from the reaction chamber volume, leaving a layer coating the substrate, a second reactant is then admitted into the reaction chamber volume, which adsorbs onto this initial layer in a self-limiting process. The second reactant is then also removed from the reaction chamber volume. Following this procedure a self-limited multilayer of unreacted species remains adsorbed on the substrate to be coated. If additional chemical species are desirable, these exposures and removals could be continued. Next this multilayer is exposed to a flux of radicals.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: July 15, 2008
    Inventor: Arthur Sherman
  • Publication number: 20080166522
    Abstract: An epitaxial growth process for producing a thick III-N layer, wherein III denotes at least one element of group III of the periodic table of elements, is disclosed, wherein a thick III-N layer is deposited above a foreign substrate. The epitaxial growth process preferably is carried out by HVPE. The substrate can also be a template comprising the foreign substrate and at least one thin III-N intermediate layer. The surface quality is improved by providing a slight intentional misorientation of the substrate, and/or a reduction of the N/III ratio and/or the reactor pressure towards the end of the epitaxial growth process. Substrates and semiconductor devices with such improved III-N layers are also disclosed.
    Type: Application
    Filed: May 5, 2006
    Publication date: July 10, 2008
    Applicants: FREIBERGER COMPOUND MATERIALS GMBH, OSRAM OPTO SEMICONDUCTORS GMBH, FRAUNHOFER GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Ferdinand Scholz, Peter Bruckner, Frank Habel, Matthias Peter, Klaus Kohler
  • Patent number: 7396409
    Abstract: By uniformly forming an indefinite number of microscopic acicular crystals on a surface of a silicon substrate so as to be perpendicular to the surface of the substrate by plasma CVD method using a catalyst, it is possible to reliably, homogeneously and massively form an ultramicroscopic acicular silicon crystal having a substantial cone shape tapered so as to have a radius of curvature of not less than 1 nm to no more than 20 nm at its tip end and having a diameter of bottom surface of not less than 10 nm, and a height equivalent to or more than the diameter of bottom surface, at a desired location.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: July 8, 2008
    Assignees: Covalent Materials Corporation, Techno Network Shikoku Co., Ltd.
    Inventors: Akitmitsu Hatta, Hiroaki Yoshimura, Keiichi Ishimoto, Hiroaki Kanakusa, Shinichi Kawagoe
  • Publication number: 20080156255
    Abstract: The present invention relates to an apparatus for vapour phase crystal growth to produce multiple single crystals in one growth cycle comprising one central source chamber, a plurality of growth chambers, a plurality of passage means adapted for transport of vapour from the source chamber to the growth chambers, wherein the source chamber is thermally decoupled from the growth chambers.
    Type: Application
    Filed: February 2, 2006
    Publication date: July 3, 2008
    Inventors: Arnab Basu, Max Robinson, Ben Cantwell, Andy Brinkman
  • Patent number: 7393410
    Abstract: There is provided a method of manufacturing a nano-wire using a crystal structure. In the method of manufacturing a nano-wire, a crystal grain having a plurality of crystal faces is used as a seed, and a crystal growing material having a lattice constant difference within a predetermined range is deposited on the crystal grain, thereby allowing the nano-wire to grow from at least one of the crystal faces. Therefore, it is possible to give the positional selectivity with a simple process using a principle of crystal growth and to generate a nano-structure such as a nano-wire, etc. having good crystallinity. Further, it is possible to generate a different-kind junction structure having various shapes by adjusting a feature of a crystal used as a seed.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: July 1, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Sang-Hyun Lee, Tae-Won Jeong, Jeong-Na Huh
  • Patent number: 7393562
    Abstract: A method of providing material into a deposition chamber is provided. A reservoir is in fluid communication with the deposition chamber. A metastable specie is provided and contained within the reservoir prior to flowing the metastable specie from the reservoir into the deposition chamber. For atomic layer deposition, the metastable specie can be purged from the containment reservoir and the metastable specie can be compressed into the reaction chamber from the reservoir. A portion of the metastable specie is deposited onto a substrate.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: July 1, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7390360
    Abstract: Compositions useful in the manufacture of compound semiconductors are provided. Methods of manufacturing compound semiconductors using these compositions are also provided.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: June 24, 2008
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Deodatta Vinayak Shenai-Khatkhate, Egbert Woelk
  • Patent number: 7387677
    Abstract: The substrate is used for opto-electric or electrical devices and comprises a layer of nitride grown by means of vapor phase epitaxy growth wherein both main surfaces of the nitride substrate are substantially consisting of non N-polar face and N-polar face respectively and the dislocation density of the substrate is 5×105/cm2 or less. Therefore, the template type substrate has a good dislocation density and a good value of FWHM of the X-ray rocking curve from (0002) plane less than 80, so that the resulting template type substrate is very useful for the epitaxy substrate from gaseous phase such as MOCVD, MBE and HVPE, resulting in possibility of making good opto-electric devices such as Laser Diode and large-output LED and good electric devices such as MOSFET.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: June 17, 2008
    Assignees: AMMONO Sp. z o.o., Nichia Corporation
    Inventors: Robert Dwilinski, Roman Doradzinski, Jerzy Garczynski, Leszek Sierzputowski, Yasuo Kanbara
  • Publication number: 20080134959
    Abstract: An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide.
    Type: Application
    Filed: January 31, 2008
    Publication date: June 12, 2008
    Applicant: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Publication number: 20080134960
    Abstract: An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide.
    Type: Application
    Filed: January 31, 2008
    Publication date: June 12, 2008
    Applicant: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Patent number: 7384867
    Abstract: Methods for the deposition of tungsten films are provided. The methods include depositing a nucleation layer by alternatively adsorbing a tungsten precursor and a reducing gas on a substrate, and depositing a bulk layer of tungsten over the nucleation layer.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: June 10, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Ken K. Lai, Jeong Soo Byun, Frederick C. Wu, Ramanujapuran A. Srinivas, Avgerinos Gelatos, Mei Chang, Moris Kori, Ashok K. Sinha, Hua Chung, Hongbin Fang, Alfred W. Mak, Michael X. Yang, Ming Xi
  • Patent number: 7384481
    Abstract: Methods for forming compositions comprising a single-phase rare-earth dielectric disposed on a substrate are disclosed. In some embodiments, the method forms a semiconductor-on-insulator structure. Compositions and structures that are formed via the method provide the basis for forming high-performance devices and circuits.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: June 10, 2008
    Assignee: Translucent Photonics, Inc.
    Inventor: Petar Atanackovic
  • Publication number: 20080115719
    Abstract: In a method of SiC single crystal growth, a SiC single crystal seed and polycrystalline SiC source material are provided in spaced relation inside of a graphite growth crucible along with at least one compound capable of forming SiO gas in the growth crucible. The growth crucible is heated whereupon the gaseous SiO forms and reacts with carbon in the growth crucible thereby avoiding the introduction of carbon into the SiC single crystal before and during the growth thereof and the SiC source material vaporizes and is transported via a temperature gradient in the growth crucible to the seed crystal where it precipitates and forms a SiC single crystal.
    Type: Application
    Filed: September 27, 2007
    Publication date: May 22, 2008
    Applicant: II-VI Incorporated
    Inventors: Avinash K. Gupta, Edward Semenas, Ilya Zwieback
  • Patent number: 7374617
    Abstract: The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave radiation is provided proximate a reaction chamber. At least a fragment of a precursor material is chemisorbed on a substrate within the reaction chamber while not exposing the precursor material to microwave radiation from the source. Excess precursor material is removed from the chamber, and the chemisorbed material is subsequently exposed to microwave radiation from the source within the reaction chamber.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: May 20, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Brian A. Vaartstra
  • Patent number: 7371282
    Abstract: A substrate and method for growing a semi-conductive crystal on an alloy film such as (AIN)x(SiC)(1-x) without any buffer layer is disclosed. The (AIN)x(SiC)(1-x) alloy film can be formed on a SiC substrate by a vapor deposition process using AlN and SiC powder as starting materials. The (AIN)x(SiC)(1-x) alloy film provides a better lattice match for GaN or SiC epitaxial growth and reduces defects in epitaxially grown GaN with better lattice match and chemistry.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: May 13, 2008
    Assignee: Northrop Grumman Corporation
    Inventors: Narsingh Bahadur Singh, Brian Wagner, Mike Aumer, Darren Thomson, David Kahler, Andre Berghmans, David J. Knuteson
  • Patent number: 7371281
    Abstract: A growth crucible (2) for depositing on a seed crystal substrate (5) a silicon carbide single crystal (6) using a sublimate gas of a silicon carbide raw material (11) is disposed inside of an outer crucible (1). During the course of silicon carbide single crystal, a silicon raw material (22) is continuously fed from outside into a space between the growth crucible and the outer crucible for the purpose of vaporizing the silicon raw material. An atmosphere gas surrounding the growth crucible is constituted of a silicon gas. The pressure of the atmosphere silicon gas is controlled to suppress a variation in the composition of the sublimate gas within the growth crucible to thereby grow a large-sized silicon carbide single crystal with few crystal defects on the seed crystal substrate reliably at a high growth rate.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: May 13, 2008
    Assignee: Showa Denko K.K.
    Inventors: Yasuyuki Sakaguchi, Atsushi Takagi, Naoki Oyanagi
  • Patent number: 7361220
    Abstract: The present invention provides a method of manufacturing a gallium nitride single crystal that can suppress the decomposition of gallium nitride and improve production efficiency in a sublimation method. According to the manufacturing method, a material (GaN powder) for the gallium nitride (GaN) single crystal is placed inside a crucible, sublimed or evaporated by heating, and cooled on a substrate surface to return to a solid again, so that the gallium nitride single crystal is grown on the substrate surface. The growth of the single crystal is performed under pressure. The pressure is preferably not less than 5 atm (5×1.013×105 Pa). The single crystal is grown preferably in a mixed gas atmosphere containing NH3 and N2.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: April 22, 2008
    Assignees: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takatomo Sasaki, Yusuke Mori, Fumio Kawamura, Masashi Yoshimura, Yasunori Kai, Mamoru Imade, Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi
  • Publication number: 20080090072
    Abstract: A semiconducting structure having a glass substrate. In one embodiment, the glass substrate has a softening temperature of at least about 750° C. The structure includes a nucleation layer formed on a surface of the substrate, a template layer deposited on the nucleation layer by one of ion assisted beam deposition and reactive ion beam deposition, at least on biaxially oriented buffer layer epitaxially deposited on the template layer, and a biaxially oriented semiconducting layer epitaxially deposited on the buffer layer. A method of making the semiconducting structure is also described.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 17, 2008
    Inventor: Alp T. Findikoglu
  • Patent number: 7357837
    Abstract: The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer 8 an epitaxial layer 12 made of GaN.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: April 15, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Takuji Okahisa, Naoki Matsumoto