Preformed Panel Circuit Arrangement (e.g., Printed Circuit) Patents (Class 174/250)
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Patent number: 10869382Abstract: An interposer includes an insulating element body, a wiring electrode inside the element body, a signal terminal electrode at the top surface of the element body and connected to a flat cable with a conductive bonding material interposed therebetween, and a ground terminal electrode. A through-hole penetrates through the element body to allow a bar-shaped metal fixing member to be inserted. A metal fixing member connecting electrode to be electrically connected to a metal fixing member is provided at at least one of the top surface of the element body and an inner wall of the through-hole. Predetermined signal terminal electrodes are electrically connected by the wiring electrode. The ground terminal electrode and the metal fixing member connecting electrode are electrically connected.Type: GrantFiled: February 18, 2020Date of Patent: December 15, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Hirokazu Yazaki, Keito Yonemori
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Patent number: 10863618Abstract: A composite substrate structure includes a circuit substrate, a first anisotropic conductive film, a first glass substrate, a dielectric layer, a patterned circuit layer and a conductive via. The first anisotropic conductive film is disposed on the circuit substrate. The first glass substrate is disposed on the first anisotropic conductive film and has a first surface and a second surface opposite to the first surface. The first glass substrate includes a first circuit layer, a second circuit layer and at least one first conductive via. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The first conductive via penetrates the first glass substrate and is electrically connected to the first circuit layer and the second circuit layer. The first glass substrate and the circuit substrate are respectively located on two opposite sides of the first anisotropic conductive film.Type: GrantFiled: February 22, 2019Date of Patent: December 8, 2020Assignee: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Pei-Wei Wang, Bo-Cheng Lin, Chun-Hsien Chien, Chien-Chou Chen
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Patent number: 10860044Abstract: Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input pin is configured to step-down a voltage from the external supply voltage level to the internal supply voltage level and to step-up a current from the external supply current level to the internal supply current level to provide an internal power source.Type: GrantFiled: December 13, 2016Date of Patent: December 8, 2020Assignee: XILINX, INC.Inventor: Stephen M. Trimberger
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Patent number: 10863616Abstract: A circuit board includes an insulating layer; and a wiring layer disposed on a surface of the insulating layer, wherein the wiring layer includes a noise canceling region including a first wiring having a linear shape; and a second wiring having a linear shape and disposed side by side with the first wiring, wherein the first wiring and the second wiring include a bent portion.Type: GrantFiled: July 2, 2020Date of Patent: December 8, 2020Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Jeong Hyun Park
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Patent number: 10861815Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BRIM substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.Type: GrantFiled: September 5, 2019Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Weng Hong Teh, Chia-Pin Chiu
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Patent number: 10863625Abstract: A flexible printed circuit board includes: a base material including a principal face; at least one first wiring pattern disposed on the principal face of the base material and extending along a first direction; and a first member and a second member disposed on the first wiring pattern so as to be spaced from each other in the first direction. In the first direction, the first member and the second member divide the flexible printed circuit board into: a first region located opposite to the second member with respect to the first member in the first direction, a second region located between the first member and the second member, a third region located opposite to the first member with respect to the second member, a fourth region in which the first member is disposed, and a fifth region in which the second member is disposed.Type: GrantFiled: April 19, 2018Date of Patent: December 8, 2020Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Takumi Nagamine, Yoichi Kitamura
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Patent number: 10852783Abstract: A system and method of operatively coupling a motherboard and a graphics board supported on a chassis, coating the motherboard and the graphics board with an anti-tarnish finish, plating a first interposer on at least a first side with a neutral metal material, soldering pass-through electrical contacts of the first interposer to a connector pad area of the motherboard, and clamping a first compression jumper pad to compress an array of compressible communication contacts to the pass-through electrical contacts on the first interposer, adjusting a flexible jumper trace array cable between the first compression jumper pad and a second compression jumper pad to adjacently align the motherboard and graphics board to minimize thickness of the information handling system, and coupling the second compression jumper pad to the graphics board to provide lanes of data communication.Type: GrantFiled: April 11, 2018Date of Patent: December 1, 2020Assignee: Dell Products, LPInventors: Arnold Thomas Schnell, Ivan Guerra, Gurpreet Sahota
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Patent number: 10852890Abstract: A touch panel includes a substrate, a touch sensing electrode, a peripheral conductive trace, a protective layer, and a conductive layer. The substrate has a display area and a peripheral area. The touch sensing electrode is disposed in the display area. The peripheral conductive trace is disposed in the peripheral area. The touch sensing electrode is electrically connected to the peripheral conductive trace. The touch sensing electrode and the peripheral conductive trace at least include metal nanowires. The protective layer is disposed on the touch sensing electrode, and the conductive layer is disposed on the peripheral conductive trace.Type: GrantFiled: August 23, 2018Date of Patent: December 1, 2020Assignee: TPK Touch Solutions Inc.Inventors: Chen-Yu Liu, Bo-Ren Jian, Cheng-Ping Liu
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Patent number: 10818624Abstract: A semiconductor device includes a first substrate including a first surface, at least one first bonding pad disposed on the first surface, and at least one second bonding pad disposed on the first surface. The first bonding pad includes a first width, and the second bonding pad includes a second width. The second width is substantially different from the first width.Type: GrantFiled: October 24, 2017Date of Patent: October 27, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Fa Chen, Hsien-Wei Chen
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Patent number: 10811471Abstract: A display apparatus includes a touch screen panel having an active area and a non-active area. The touch screen panel includes a first side and a second side. A display flexible printed circuit board is connected to the touch screen panel. The display flexible printed circuit board at least partially overlaps the first side of the touch screen panel. A touch flexible printed circuit board is connected to the touch screen panel. The touch flexible printed circuit board at least partially overlaps the second side of the touch screen panel. The touch flexible printed circuit board is bent toward a lower surface of the touch screen panel. A reinforcement member contacts a lower surface of the touch flexible printed circuit board. A portion of a side surface of the touch screen panel is connected to the second side of the touch screen panel.Type: GrantFiled: February 7, 2019Date of Patent: October 20, 2020Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Myoung-ha Jeon, Hyeonjeong Oh, Kichang Lee
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Patent number: 10813213Abstract: The present disclosure provides a high-frequency composite substrate which includes a metal layer and an insulating structure. The insulating structure includes at least one liquid crystal polymer (LCP) layer with dielectric constant ranged from about 2 to about 4. The liquid crystal polymer layer adheres to the metal layer. The high-frequency composite substrate may reduce the adverse effects caused by the Resistor-Capacitor delay (RC delay).Type: GrantFiled: October 31, 2017Date of Patent: October 20, 2020Assignee: AZOTEK CO., LTD.Inventor: Hung-Jung Lee
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Patent number: 10806024Abstract: In one or more embodiments, a circuit board may include a trace pair and a serpentine region of the trace pair, which may include: a first subregion in which the first trace includes a first portion that has a third width and a first length and in which the second trace includes a second portion, at least substantially parallel to the first portion, that has a fourth width, greater than the second width, and a second length; and a second subregion, adjacent to the first subregion, in which the first trace includes a third portion that has the third width and a third length and in which the second trace includes a third portion that has the fourth width and a third length, different from the second length.Type: GrantFiled: January 28, 2020Date of Patent: October 13, 2020Assignee: Dell Products L.P.Inventors: Bhyrav Murthy Mutnury, Chun-Lin Liao
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Patent number: 10804629Abstract: The present invention provides a method, structure, and system of beveling staggered card edges. In some embodiments, the method, computer program product, and system include receiving a card with a plug end and two or more metal contact leads running up to the plug end, removing material from the plug end such that one or more engagement points for one or more of the leads are set back from the plug end resulting in staggered steps, where an engagement point is where a metal contact lead will enter a receptacle, and removing material from an edge formed for each engagement point of the card such that beveled edges are created at the one or more engagement points for each lead.Type: GrantFiled: November 27, 2017Date of Patent: October 13, 2020Assignee: International Business Machines CorporationInventors: Sandra Shirk/Heath, Paul Schaefer, Mark Hoffmeyer
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Patent number: 10795474Abstract: There is provided a display apparatus and a production method thereof. The display apparatus has a touch control panel and a display panel, wherein at least one surface of the touch control panel has a plurality of concave-convex fine structures, and wherein the touch control panel is on a light-emitting side of the display panel. The touch control panel may have: a flexible substrate having a plurality of concave-convex fine structures on at least one surface; and a touch control electrode having at least one part formed on one or more concave-convex fine structures of the flexible substrate.Type: GrantFiled: October 19, 2018Date of Patent: October 6, 2020Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Dejun Bu, Pao Ming Tsai, Zhao Li
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Patent number: 10784128Abstract: Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.Type: GrantFiled: September 11, 2019Date of Patent: September 22, 2020Assignee: Cerebras Systems Inc.Inventors: Jean-Philippe Fricker, Frank Jun, Paul Kennedy
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Patent number: 10779410Abstract: The present disclosure provides a circuit board, an electrical component and a display apparatus. The circuit board includes a wiring pad which is divided into a plurality of sub-pads by bubble discharge paths, the bubble discharge paths intersect at a first point which is a geometric center of the wiring pad. By configuring bubble discharge paths with a shape of a straight line and as being intersected at the geometric center point of the wiring pad, the circuit board can discharge gas bubbles, generated when the wiring pad is soldered to a wiring terminal of other circuit board, from the geometric center point of the wiring pad to the edge thereof via the bubble discharge paths. Thus gas bubbles can be eliminated or reduced between the wiring pad and the wiring terminal when soldering, connection between the wiring pad and the wiring terminal can be more secure.Type: GrantFiled: January 19, 2018Date of Patent: September 15, 2020Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Lingguo Wang, Xin Wang, Ying Liu, Yaodong Wang, Bin Fan, Binbin Liu
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Patent number: 10770498Abstract: A method for manufacturing the image sensor includes providing a substrate structure; forming a mask layer on the substrate structure, the mask layer having openings; depositing a metal grid material covering a surface of the mask layer and a bottom of the openings; and stripping the mask layer for removing a portion of the metal grid material on the top surface of the mask layer. The substrate structure includes: a substrate having a first surface; a plurality of pixels in the substrate; isolation structures around each of the plurality of pixels; and an anti-reflective coating on the first surface of the substrate. The openings include first openings exposing a portion of the first surface of the substrate structure above the isolation structures. A remaining portion of the metal grid material at the bottom of the openings forms metal grids.Type: GrantFiled: August 22, 2018Date of Patent: September 8, 2020Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: De Kui Qi, Fu Cheng Chen, Jue Lu, Xuan Jie Liu
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Patent number: 10757800Abstract: A circuit board transmission line structures has microstrip or stripline transmission line geometries and cross-hatch patterned return planes. The cross-hatch design structure of the return planes and the relative position of the cross-hatch pattern to the transmission lines are configured to increase the usable bandwidth of the transmission lines. By properly adjusting the size and shape of the cross-hatch pattern, the performance of the microstrip and stripline transmission lines can be largely restored to the performance where continuous, solid return planes are used.Type: GrantFiled: June 22, 2018Date of Patent: August 25, 2020Assignee: Flex Ltd.Inventors: Mark Bergman, Franz Gisin
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Patent number: 10743403Abstract: A wiring board includes an insulating layer, and a metal layer. The insulating layer includes a first pattern and a second pattern. The first pattern includes first grooves extending parallel to each other, and a first projecting part separating adjacent first grooves. The second pattern includes a second projecting part, and a second groove surrounding the second projecting part. The metal layer includes a wiring formed within the first grooves, and a degassing hole formed within the second pattern and having an opening formed by the second projecting part.Type: GrantFiled: December 16, 2019Date of Patent: August 11, 2020Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Rie Mizutani
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Patent number: 10736214Abstract: A printed circuit board and a method for the production thereof. The printed circuit board can include a shaped part made of an electrically conducting material and can be used to manage the currents and heat volumes that occur in the field of power electronics.Type: GrantFiled: May 23, 2012Date of Patent: August 4, 2020Assignee: JUMATECH GMBHInventor: Markus Wölfel
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Patent number: 10705002Abstract: A sensor for detecting electrically conductive and/or polarizable particles, in particular for detecting soot particles, includes a substrate, a first electrode layer, and a second electrode layer, which is arranged between the substrate and the first electrode layer. An insulation layer is formed betweem the first electrode layer and the second electrode layer and at least one opening is formed in the first electrode layer and in the insulation layer, wherein the opening of the first electrode layer and the opening of the insulation layer are arranged one over the other at least in some segments in such a way that at least one passage to the second electrode layer is formed.Type: GrantFiled: December 7, 2015Date of Patent: July 7, 2020Assignee: HERAEUS NEXENSOS GMBHInventors: Tim Asmus, Karlheinz Wienand, Stefan Dietmann
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Patent number: 10701799Abstract: According to an example, a device may comprise a printed circuit board. The printed circuit board may further comprise a first layer and a second layer. The first layer may comprise a first material and the second layer may comprise a second material. In some examples, the first layer may further comprise at least one mounting hole surrounded by a third material at a thickness equal to a thickness of the first layer, and the first material may be electrically isolated from the third material. In some examples, the printed circuit board may be mated to a light guide assembly for a touchscreen system.Type: GrantFiled: March 31, 2015Date of Patent: June 30, 2020Assignee: Hewlett-Packard Development Company, L.P.Inventors: Stewart R. Wyatt, Don E. Saunders, Scott David Hahn, Cameron L. Hutchings
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Patent number: 10689248Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.Type: GrantFiled: March 14, 2018Date of Patent: June 23, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ming Yen Lee, Chia Hao Sung, Ching-Han Huang, Yu-Hsuan Tsai
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Patent number: 10681819Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.Type: GrantFiled: December 18, 2018Date of Patent: June 9, 2020Assignee: Infineon Technologies Austria AGInventors: Eung San Cho, Danny Clavette, Darryl Galipeau
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Patent number: 10679892Abstract: A method is presented for reducing a resistance-capacitance product and RIE lag in a semiconductor device. The method includes depositing a first ultra-low-k (ULK) material over a dielectric cap, the first ULK material defining a recess, filling the recess with a second ULK material, the second ULK material being different than the first ULK material, where the first and second ULK materials are formed in a common metal level of a back-end-of-the-line (BEOL) structure, forming first trenches within the first ULK material and second trenches within the second ULK material, and filling the first and second trenches with a conductive material.Type: GrantFiled: February 28, 2019Date of Patent: June 9, 2020Assignee: International Business Machines CorporationInventors: Yann Mignot, Chih-Chao Yang, Hosadurga Shobha
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Patent number: 10672718Abstract: Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing through package vias in a glass interposer comprising laminating a polymer on at least a portion of a top surface of a glass interposer, removing at least a portion of the polymer and the glass interposer to form a through via, filling at least a portion of the through via with a metal conductor to form a metallization layer, and selectively removing a portion of the metallization layer to form a metalized through package via. Other methods are also disclosed, along with through-package-via structures in glass interposers produced therefrom.Type: GrantFiled: January 25, 2016Date of Patent: June 2, 2020Assignee: Georgia Tech Research CorporationInventors: Venkatesh Sundaram, Fuhan Liu, Rao R. Tummala, Vijay Sukumaran, Vivek Sridharan, Qiao Chen
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Patent number: 10661300Abstract: A method for painting a work piece of plastic material. The method includes applying a first coating of an electrically conductive material to the work piece and electrically grounding the first coating. The method also includes electrostatically charging a paint to render the paint conductive for statically attracting the conductive paint toward the grounded first coating of the work piece. The method also includes overlying a mask of a non-conductive material over at least a portion of the first coating of the work piece and electrically insulating the mask. The work piece is then sprayed with the conductive paint to apply a layer of paint on the first coating with the mask preventing the conductive paint from being applied on the portions of the first coating of the work piece that are covered by the mask.Type: GrantFiled: November 17, 2016Date of Patent: May 26, 2020Assignee: Lacks Enterprises, Inc.Inventors: Lee Chase, Scott Stuart
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Patent number: 10663662Abstract: A hybrid spiral waveguide geometry is proposed that exhibits essentially zero curvature (i.e., infinite bend radius) at the center of the spiral (similar to a Fermat spiral), with the curvature then increasing in value as the spiral moves outward. Advantageously, as the spiral moves away from the center, the spacing between adjacent waveguides quickly approaches a constant value (similar to an Archimedean spiral). This hybrid spiral structure has been found to allow for a high density waveguide to be created with lower loss and requiring a smaller size than many conventional spiral configurations and finds use in optical delay lines, amplifiers and arrayed waveguide gratings.Type: GrantFiled: April 29, 2019Date of Patent: May 26, 2020Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Michael Gehl, Christopher DeRose
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Patent number: 10658329Abstract: A method of determining curing conditions is for determining the curing conditions of a thermosetting resin to seal a conductive part between a substrate and an electronic component. A curing degree curve is created. The curing degree curve indicates, with respect to each of heating temperatures, relationship between heating time and curing degree of the thermosetting resin. On the basis of the created curing degree curve, a void removal time of a void naturally moving upward in the thermosetting resin, at a first heating temperature, is calculated. The first heating temperature is one of the heating temperatures.Type: GrantFiled: May 8, 2019Date of Patent: May 19, 2020Assignee: SONY CORPORATIONInventor: Takeshi Ichimura
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Patent number: 10660200Abstract: The invention provides an electronic device that includes a first functional body, a second functional body, and at least one connection member connecting the first functional body to the second functional body. The at least one connection member has a spiral pattern, and is suspended in air to allow for stretching, flexing or compressing.Type: GrantFiled: June 16, 2017Date of Patent: May 19, 2020Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITYInventors: Hanqing Jiang, Cheng Lv, Hongyu Yu
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Patent number: 10660218Abstract: A multilayer circuit board comprises an inner circuit unit having at least one solder portion, and at least one outer circuit board coupled with the inner circuit unit. The inner circuit unit connects with the outer circuit board by an insulation colloid. At least one side of the inner circuit unit does not extend to edges of the multilayer circuit board. The at least one outer circuit board forms at least one through-hole and at least one conductive hole. The at least one conductive hole which is internally-plated with copper extends from the at least one outer circuit board to the inner circuit unit. A method of manufacturing the multilayer circuit board is also disclosed.Type: GrantFiled: April 19, 2018Date of Patent: May 19, 2020Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.Inventors: Xian-Qin Hu, Li-Kun Liu, Yan-Lu Li, Ming-Jaan Ho
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Patent number: 10660219Abstract: A resin multilayer substrate includes a stacked body including resin layers, a component, one or more first conductor patterns, and one or more second conductor patterns each disposed in a gap between the resin layers. At least a portion of an outline of each of the one or more first conductor patterns overlaps with the component. An outline of each of the one or more second conductor patterns does not overlap with the component. A resin portion is adjacent to each of the one or more first conductor patterns along a portion of the outline of each of the one or more first conductor patterns that overlaps with the component. The resin portion is made of a resin paste including thermoplastic resin powder as a main material. The resin portion is not disposed in a portion along the outline of each of the one or more second conductor patterns.Type: GrantFiled: February 8, 2019Date of Patent: May 19, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yoshihito Otsubo, Asato Fujimoto
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Patent number: 10653006Abstract: Electrical conductors are disclosed. More particularly, undulating electrical conductors are disclosed. Certain disclosed electrical conductors may be suitable to be disposed on flexible or stretchable substrates.Type: GrantFiled: December 14, 2015Date of Patent: May 12, 2020Assignee: 3M INNOVATIVE PROPERTIES COMPANYInventors: Nicholas T. Gabriel, Ronald D. Jesme, Andrew J. Ouderkirk, Ravi Palaniswamy, Andrew P. Bonifas, Alejandro Aldrin A. Narag, II, Robert M. Jennings, Robin E. Gorrell
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Patent number: 10643784Abstract: A filter inductor for high-current applications. The filter inductor includes a magnetic core and a winding. The winding includes a shaped section having opposing ends, a pair of arm sections laterally extending from the opposing ends of the shaped section, respectively, and a pair of inductor pins, each extending perpendicular from an end of a respective arm section. The magnetic core includes a first core portion and a second core portion. The first core portion includes a recessed channel configured to receive the shaped section of the winding. The second core portion includes a pair of recessed regions configured to receive the pair of arm sections of the winding, respectively. The first core portion and the second core portion are coupled in contact to one another to secure the shaped section of the winding within the magnetic core. The filter inductor can be edge-mounted to a printed circuit board.Type: GrantFiled: April 19, 2017Date of Patent: May 5, 2020Assignee: Bel Fuse (Macao Commercial Offshore) LimitedInventors: Jianbin Yao, Hai Huang
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Patent number: 10638599Abstract: A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including a signal layer; and via patterns formed in the plurality of layers, each of the via patterns comprising first and second signal vias extending from a first surface of the printed circuit board to the signal layer, the signal layer including first and second signal traces connected to the first and second signal vias, respectively, the signal layer further including a ground conductor located between the signal traces and adjacent signal-carrying elements.Type: GrantFiled: December 18, 2018Date of Patent: April 28, 2020Assignee: Amphenol CorporationInventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
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Patent number: 10638605Abstract: A circuit board design device judging whether a circuit board has a pair of via holes which are adjacent within a solder bridge formation distance within which a solder bridge can be formed; when the affirmative, the circuit board design device judging whether each of the pair of via holes is electrically connected in parallel to other via hole with a land not coated with solder resist; when the circuit board design device judges that at least one of the pair of via holes is electrically connected in parallel to the other via hole with a land not coated with solder resist, the circuit board design device determining the at least one of the pair of via holes which is electrically connected in parallel to the other via hole with a land not coated with solder resist as a coated via hole with a land coated with solder resist.Type: GrantFiled: July 23, 2018Date of Patent: April 28, 2020Assignee: DENSO TEN LimitedInventors: Tamaki Kawabata, Kenichi Osakabe
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Patent number: 10632680Abstract: Embodiments include an apparatus, generated at least partially using a 3D printer, the apparatus including an object, the object being at least partially fabricated from a 3D printer, the object including a first part of the object, the first part of the object defining a first void and a second part of the object, the second part of the object defining a second void. The apparatus can include a pin, the pin having a first end and a second end, where the first end of the pin engages the first void of the object and the second end of the pin engages the second end of the pin such that the first part is coupled with the second part to form the object.Type: GrantFiled: March 6, 2018Date of Patent: April 28, 2020Assignee: GHOST CAPITAL, INC.Inventor: Brian Quincy Robinson
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Patent number: 10627099Abstract: A lighting assembly (100), a light source, a lamp and a luminaire are provided. The lighting assembly comprises a heat transferring element (102) and an elongated structure (120) comprising light emitting elements (122, 122?) and power connections. The heat transferring element comprises at a first side (104) a heat sink interface or a heat sink element. At the second opposite side (106) one or more upstanding walls (108, 108?) are provided extending away from the second side. The upstanding walls are heat conductive and thermally coupled to the first side. The elongated structure is arranged on a wall surface of at least one of the upstanding walls. The wall surface is adjacent to the second side. A surface of the elongated structure through which no light is emitted is thermally coupled to the wall surface. A pattern formed by the elongated structure is a meandering or spiral pattern.Type: GrantFiled: June 20, 2017Date of Patent: April 21, 2020Assignee: SIGNIFY HOLDING B.V.Inventors: Ties Van Bommel, Rifat Ata Mustafa Hikmet
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Patent number: 10629850Abstract: A flexible OLED display panel is disclosed and includes an encapsulation structure. The encapsulation structure includes: a first inorganic thin film formed on a surface of an OLED display layer and a surrounding region of the surface; a first organic thin film formed on a surface of the first inorganic thin film; and a plurality of dams. Each of the dams has a first sub-dam close to the first inorganic thin film and a second sub-dam away from the first inorganic thin film. A gap is formed between the first sub-dam and the second sub-dam which are located at a same side. The gap is filled with desiccant.Type: GrantFiled: November 28, 2017Date of Patent: April 21, 2020Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventors: Simin Peng, Hsiang lun Hsu, Jun Cao
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Patent number: 10624208Abstract: A printed circuit board for a surface mount device (SMD) is provided. The printed circuit board includes adjacent, opposed first and second lands on a face of the printed circuit board, the first land comprising a first solder pad contacting or merged with a first annular pad of a first via, the second land comprising a second solder pad contacting or merged with a second annular pad of a second via, arranged for solder mounting a surface mount device to the first and second solder pads.Type: GrantFiled: October 18, 2018Date of Patent: April 14, 2020Assignee: Arista Networks, Inc.Inventor: Zev Gross
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Patent number: 10619248Abstract: The present invention provides a conductive laminate for a touch panel which includes a substrate, and a patterned metal layer which is visually recognized to have greater blackness when viewed from the substrate side; a touch panel; and a transparent conductive laminate. The conductive laminate includes a substrate which has two main surfaces; a patterned plated layer which is disposed on at least one main surface of the substrate and has a functional group that interacts with metal ions; and a patterned metal layer which is disposed on the patterned plated layer, in which the patterned plated layer includes a metal component constituting the patterned metal layer and the ratio of the average peak intensity resulting from the metal component contained in the patterned plated layer to the average peak intensity resulting from the metal component constituting the patterned metal layer is in a range of 0.5 to 0.95.Type: GrantFiled: November 17, 2016Date of Patent: April 14, 2020Assignee: FUJIFILM CorporationInventor: Naoki Tsukamoto
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Patent number: 10624215Abstract: A method for manufacturing connection structure, the method includes arranging a first composite on a first surface of a first member where a first electrode is located and arranging conductive particles on the first electrode, arranging a second composite on a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.Type: GrantFiled: June 8, 2018Date of Patent: April 14, 2020Assignee: MIKUNI ELECTRON CORPORATIONInventor: Sakae Tanaka
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Patent number: 10616990Abstract: Printed circuit board (PCB) apparatus comprising an apertured ground plane defining aperture pattern/s in the ground plane, each aperture pattern including apertures which, taken together, surround most but not all of SMT footprint/s and are interspersed with ground plane region/s which provide/s the SMT component with electrical connectivity to area/s of said ground plane other than said SMT footprint, thereby to maintain functionality of the SMT component including electrical connectivity between said SMT footprint and area/s of said ground plane other than said SMT footprint, while also slowing heat dissipation from the SMT footprint by restricting thermal conductivity between said area and said area's vicinity thereby to raise the temperature in the SMT footprint while a SMT component is being soldered thereto, thereby to at least partly prevent improper soldering of the SMT component which may cause the SMT component to subsequently detach from the board.Type: GrantFiled: December 18, 2018Date of Patent: April 7, 2020Assignee: ELTA SYSTEMS LTD.Inventor: Yaniv Boaron
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Patent number: 10616991Abstract: An interposer includes an insulating element body, a wiring electrode inside the element body, a signal terminal electrode at the top surface of the element body and connected to a flat cable with a conductive bonding material interposed therebetween, and a ground terminal electrode. A through-hole penetrates through the element body to allow a bar-shaped metal fixing member to be inserted. A metal fixing member connecting electrode to be electrically connected to a metal fixing member is provided at at least one of the top surface of the element body and an inner wall of the through-hole. Predetermined signal terminal electrodes are electrically connected by the wiring electrode. The ground terminal electrode and the metal fixing member connecting electrode are electrically connected.Type: GrantFiled: July 30, 2019Date of Patent: April 7, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Hirokazu Yazaki, Keito Yonemori
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Patent number: 10617009Abstract: Methods, systems, and apparatus, including printed circuit boards (PCBs) with trace routing topologies are disclosed. In one aspect, a PCB includes an external layer that includes multiple integrated circuit (IC) installation regions that are each configured to receive an IC, a first trace routing layer having a first conductive trace that is routed along a first path from a first IC installation region to a second IC installation region, a second trace routing layer having a second conductive trace that is routed along a second path from the first IC installation region to the second IC installation region, a first via region having one or more first vias that extend from the first trace routing layer to the second trace routing layer, and a second via region having one or more second vias that extend from the first trace routing layer to the second trace routing layer.Type: GrantFiled: July 31, 2019Date of Patent: April 7, 2020Assignee: Google LLCInventors: Andrew Gerard Noonan, Sara Zebian
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Patent number: 10608018Abstract: A display device includes first, second and third connection wiring. The second connection wiring is located in a same layer as the first connection wiring. The third connection wiring is located in a layer different from the first connection wiring. The first connection wiring includes at least one first region running in a first direction and at least one second region running in a second direction different from the first direction. The second connection wiring includes at least one third region running in the first direction and at least one fourth region running in the second direction. The third connection wiring includes at least one fifth region running in the first direction and at least one sixth region running in the second direction. The at least one first region, the at least one third region, and the at least one fifth region are adjacent to one another.Type: GrantFiled: March 19, 2018Date of Patent: March 31, 2020Assignee: Japan Display Inc.Inventor: Jun Hanari
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Patent number: 10606426Abstract: A touch panel electrode includes a transparent base, two or more first electrode patterns, and two or more second electrode patterns. The first electrode pattern and the second electrode pattern face each other being insulated, and overlap each other. Each of the first electrode pattern and the second electrode pattern is a combination of a plurality of cells formed by thin metal wires. The area of an overlapping portion between the first electrode pattern and the second electrode pattern is greater than 4 mm2 and less than 20 mm2.Type: GrantFiled: September 4, 2018Date of Patent: March 31, 2020Assignee: FUJIFILM CorporationInventor: Hiroshige Nakamura
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Patent number: 10602651Abstract: A system for tracking objects such as a printed circuit board (PCB) undergoing multiple manufacturing processes traceability system includes a coding unit, a scanning unit, and a reading unit and a database. The printed circuit board includes at least two inner copper foil substrates, subsequent substrates can be added. The coding unit marks identification and manufacturing stage codes on the inner copper foil substrate for through scanning by the scanning unit emitting X-rays. The reading unit can receive and parse the codes identified by the X-rays, and determine the previous or a next stage according to a predetermined encoding rule without risk of stage repetition or stage omission or product misplacement. The database stores standard identities and information as to manufacturing stages as a reference.Type: GrantFiled: July 31, 2018Date of Patent: March 24, 2020Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.Inventors: Fu-Sheng Luo, Pai-Hung Huang, Chien-Jui Lo, Yin-Zhen Zeng
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Patent number: 10595406Abstract: A module component includes a substrate; first, second, third and fourth main electrodes on or in a principal surface of the substrate; a sub-electrode located between two of the four main electrodes and connected to one of the four main electrodes by a solder; a first mount component mounted to the first and second main electrodes; and a second mount component mounted to the third and fourth main electrodes; wherein an area of the sub-electrode is smaller than an area of each of the first, second, third and fourth main electrodes.Type: GrantFiled: November 5, 2018Date of Patent: March 17, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Hiroshi Nishikawa
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Patent number: 10595396Abstract: In one or more embodiments, a circuit board may include a trace pair and a serpentine region of the trace pair, which may include: a first subregion in which the first trace includes a first portion that has a third width and a first length and in which the second trace includes a second portion, at least substantially parallel to the first portion, that has a fourth width, greater than the second width, and a second length; and a second subregion, adjacent to the first subregion, in which the first trace includes a third portion that has the third width and a third length and in which the second trace includes a third portion that has the fourth width and a third length, different from the second length.Type: GrantFiled: March 7, 2019Date of Patent: March 17, 2020Assignee: Dell Products L.P.Inventors: Bhyrav M. Mutnury, Chun-Lin Liao