Abstract: An apparatus includes a plurality of conductive layers and a plurality of traces configured to carry a plurality of signals through a change of direction. The traces may be routed parallel to each other in a first trace segment in a first of the conductive layers toward the change of direction. The traces may be routed parallel to each other in a second trace segment in a second of the conductive layers in the change of direction. One of the traces in a third trace segment in the first conductive layer may cross over another of the traces in the second trace segment in the second conductive layer in the change of direction. The traces may be routed parallel to each other in the third trace segment in the first conductive layer away from the change of direction.

Abstract: A low-temperature co-fired microwave dielectric ceramic material includes: (a) 85 wt % to 99 wt % ceramic material comprising Mg2SiO4, Ca2SiO4, CaTiO3, and CaZrO3, wherein a weight ratio of Mg2SiO4 relative to Ca2SiO4 is of (1?x):x, a weight ratio of CaTiO3 relative to CaZrO3 is of y:z, and a weight ratio of entities of Mg2SiO4 and Ca2SiO4 relative to CaTiO3 is of (1?y?z):y, 0.2?x?0.7, 0.05?y?0.2, 0.05?z?0.4; and (b) 1 wt % to 15 wt % glass material composed of Li2O, BaO, SrO, CaO, B2O3, and SiO2.

Abstract: Disclosed in various examples of the present application is an electronic device comprising: first and second conductive patterns electrically connected to a communication circuit; a conductive material electrically connected between the first and second conductive patterns; a third conductive pattern spaced apart in a first direction from the first and/or second conductive patterns; and a fourth conductive pattern spaced apart in a second direction opposite to the first direction from the first and/or second conductive patterns, wherein each of the first and second conductive patterns comprises a first part of a first width and a second part of a second width wider than the first width, and the conductive material is arranged on at least a portion of the second part of the first conductive pattern and the second part of the second conductive pattern.

Abstract: The QSFP-DD module has an internal printed circuit board defining a mating port at a front edge region, and a connecting port at a rear edge region, and plural sets of wires mechanically and electrically connected to the connecting port with a plurality of ground staples discrete from one another to secure the respective sets of wires to the printed circuit board. The pitch among the ground staples is essentially 3.38 mm, and the wires are connected to two opposite surfaces of the printed circuit board with the associated ground staples. The staples are arranged in rows along the transverse direction.

Abstract: Aspects are generally directed to systems and methods that integrate contactless electric field detectors to measure biophysical signals generated by a body. In one example, a biophysical sensing system includes a sensing assembly including an array of contactless electric field detectors, each of the contactless electric field detectors being configured to sense a corresponding component of an electric field generated by a body, a control system to receive sensor data indicative of the components of the electric field sensed by each of the contactless electric field detectors, the control system being configured to generate an estimate of the electric field based on the sensor data, and a feedback system coupled to at least the control system, the feedback system including at least one feedback interface, the feedback system being configured to operate the feedback interface to provide feedback based on the estimate of the electric field.

Abstract: [Object] To provide a method for producing an electrical wiring member having a layered structure of copper wiring and a blackening layer and to provide the electrical wiring member through a search for a material for the blackening layer, the material being etched at a rate close to that for the copper wiring under conditions where etching controllability is ensured. [Solution] A method for producing an electrical wiring member according to the present invention includes a step of forming, on at least one main surface of a substrate, a layered film 6 of a Cu layer 3 and CuNO-based blackening layers (2a and 2b); a step of forming a resist layer 4a in a predetermined region on the layered film 6; and a step of removing a partial region of the layered film 6 by bringing the layered film 6 into contact with an etchant.

Abstract: A method includes the following steps: S1, providing the insulating layer having an inclined face; S4, disposing a photomask so that in the photoresist, first and second exposure portions are exposed to light, and exposing the photoresist is to light through the photomask; S5, removing the first and the second exposure portions of the photoresist. On the assumption that in S4, light reflected at the metal thin film is focused between the first and the second exposure portions of the photoresist, the inclined face has a bending portion bending in one direction, the portion removed in S5 in the photoresist due to light focus being continuous with the first and the second exposure portions. The second exposure portion includes continuously an avoidance portion that avoids the bending portion and an overlapping portion that overlaps with at least a portion other than the bending portion in the inclined face.

Abstract: The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.

Abstract: A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

Abstract: By flexographic printing or inkjet printing, insulating ink is applied on a wiring pattern in accordance with a predetermined printing pattern. The insulating ink is hardened, whereby an insulating layer is formed. A contact region of the wiring pattern that is used for electrical connection with a conductor other than the wiring pattern is not covered with the insulating layer. The printing pattern is delimited by the outline of a non-printing region including the contact region. The wiring pattern includes, in the non-printing region, a trunk wiring line leading, to the contact region, from a position on the wiring pattern at which the wiring pattern overlaps with the outline and a branch wiring line extending from a point on at least one side of the trunk wiring line and terminating without making contact with the outline.

Abstract: By flexographic printing or inkjet printing, insulating ink is applied on a wiring pattern in accordance with a predetermined printing pattern. The insulating ink is hardened, whereby an insulating layer is formed. A contact region of the wiring pattern that is used for electrical connection with a conductor other than the wiring pattern is not covered with the insulating layer. The printing pattern is delimited by the outline of a non-printing region including the contact region. The wiring pattern includes, in the non-printing region, a trunk wiring line leading, to the contact region, from a position on the wiring pattern at which the wiring pattern overlaps with the outline and a branch wiring line extending from a point on at least one side of the trunk wiring line and terminating without making contact with the outline.

Abstract: The present invention relates to a conductive coating composition comprising a polyolefin copolymer resin comprising an olefin monomer and acrylic acid comonomer or (meth)acrylic acid comonomer, a plurality of anisotropic nanoparticles and a solvent.

Abstract: An electricity storage module unit that can improve installation work efficiency, and that can be used to build an electricity storage pack that is versatile in terms of installation. An electricity storage module unit is provided with an electricity storage module that includes a plurality of electricity storage elements, and the electricity storage module unit includes: a wiring member that is connected to the electricity storage module; a wiring connection part that connects the wiring member to the wiring member of another electricity storage module unit or to an external electrical component; and a unit base plate on which the electricity storage module is mounted. The unit base plate has a plurality of routing grooves that allow the wiring member to be routed such that a direction in which the wiring member is routed is changeable.

Abstract: A multilayer wiring board having a high degree of freedom of wiring design and realizing high-density wiring, and a method to simply manufacture the multilayer wiring board is provided. A core substrate with two or more wiring layers provided thereon through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically connected to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 ?m. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via.

Abstract: A battery module includes a housing, a plurality of battery cells disposed in the housing, and a printed circuit board (PCB) assembly disposed in the housing. The PCB assembly includes a PCB and a shunt disposed across a first surface of the PCB. A second surface of the shunt directly contacts the first surface of the PCB, and the shunt is electrically coupled between the battery cells and a terminal of the battery module.

Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Abstract: The present disclosure relates to a structure and a method for filling a via hole formed in a multilayer printed circuit board, and more particularly, to a structure and a method for filling a via hole formed in a multilayer printed circuit board, the structure and method enabling high-current transmission even in a narrow space in such a way that a via hole formed when a typical multilayer printed circuit board is manufactured is first filled with Cu and Ag plating, and the remaining vacant space is completely filled with a solder cream, thereby increasing the amount of conductors.

Abstract: This method for manufacturing a hermetic sealing lid member (1, 201, 301) includes forming a Ni plated metal plate (70, 170) by forming a Ni plated layer (11, 12, 41) on a surface of a metal plate (40) having a corrosion resistance and forming the hermetic sealing lid member by punching the Ni plated metal plate.

Abstract: A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

Abstract: According to various aspects, exemplary embodiments are disclosed of board level shields with virtual grounding capability. In an exemplary embodiment, a board level shield includes one or more resonators configured to be operable for virtually connecting the board level shield to a ground plane or a shielding surface. Also disclosed are exemplary embodiments of methods relating to making board level shields having virtual grounding capability. Additionally, exemplary embodiments are disclosed of methods relating to providing shielding for one or more components on a substrate by using a board level shield having virtual grounding capability. Further exemplary embodiments are disclosed of methods relating to making system in package (SiP) or system on chip (SoC) shielded modules and methods relating to providing shielding for one or more components of SiP or SoC module.

Abstract: Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.

Abstract: The present subject matter relates to the method of manufacturing circuit having lamination layer using LDS (Laser Direct Structuring) to ease the application on surface structure for applied product of various electronic circuit and particularly, in which can form circuit structure of single-layer to multiple-layer on the surface of injection-molded substrate in the shape of plane or curved surface, metal product, glasses, ceramic, rubber or other material.

Abstract: A coplanar waveguide may include a first transmission line extending between a first ground plane and a second ground plane at a first interconnect level. The coplanar waveguide may further include a shielding layer at a second interconnect level. The shielding layer may include a first set of conductive fingers coupled to the first ground plane. The first set of conductive fingers may be interdigitated with a second set of conductive fingers that are coupled to the second ground plane. Only a dielectric layer may be between the first set of conductive interdigitated fingers and the second set of conductive interdigitated fingers. The first ground plane, the second ground plane, the dielectric layer, and the shielding layer may form a capacitor.

Abstract: A multilayer printed circuit board (PCB) including a plurality of substrate layers formed in stack is provided. The multilayer printed circuit board includes a first substrate layer located on an outer side of the plurality of substrate layers, and a second substrate layer located on another outer side of the plurality of substrate layers that is opposite to the first substrate layer. The multilayer printed circuit board further includes a transmission line, connecting a first point of the first substrate layer and a second point of the second substrate layer, which passes through the first and second substrate layers, and includes a sub-transmission line disposed between and extended along at least two adjacent substrate layers among the plurality of substrate layers.

Abstract: The present disclosure relates to an electronic transmission controller, with a housing, a printed circuit board assembly, and at least one electronic module mounted on the printed circuit board assembly. The printed circuit board assembly may include a first region extending inside the housing, the first region being sealed from an external fluid. The printed circuit board assembly may include a second region extending outside the housing. The printed circuit board assembly may include a plurality of electrically conductive conductor path layers which are electrically insulated against one another by dielectric layers. An outer layer made of a fluid resistant and electrically insulating material may be applied to at least one outer electrically conductive conductor path layer of the plurality of conductive path layers at a location of the second region of the printed circuit board assembly.

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract: A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

Abstract: Systems and methods are provided for analyzing an electromagnetic field in an original domain. An original domain is decomposed into one or more finite-element-boundary-integral (FEBI) regions and one or more integral-equation (IE) regions. A model is determined for an electromagnetic field in the one or more FEBI regions and the one or more IE regions. An initial block system matrix for the original domain is generated based at least in part on the model. The initial block system matrix includes a first diagonal block corresponding to the one or more FEBI regions and a second diagonal block corresponding to the one or more IE regions. A replacement matrix is generated based at least in part on a physical optics (PO) method. A final block system matrix is generated by replacing the second diagonal block in the initial block system matrix with the replacement matrix.

Abstract: A ceramic multilayer substrate that includes a ceramic insulator layer, which includes a first layer, a second layer, and a third layer and in which the first layer is interposed between the second layer and the third layer, an inner pattern conductor, an outer pattern conductor, and outer electrodes. The ceramic insulator layer is interposed between the inner pattern conductor and the outer pattern conductor. The sintering shrinkage start temperatures of the second layer alone and the third layer alone in a green sheet state are higher than or equal to the sintering shrinkage stop temperature of the first layer alone in a green sheet state. The thickness of the ceramic insulator layer is 5.0 ?m to 55.7 ?m. The ratio of the total of the thickness of the second layer and the thickness of the third layer to the thickness of the first layer is 0.25 to 1.11.

Abstract: Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity.

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings.

Abstract: An electronic component package includes a substrate having an upper surface. Traces on the upper surface of the substrate extend in a longitudinal direction. The traces have a first latitudinal width in a latitudinal direction, the latitudinal direction being perpendicular to the longitudinal direction. Rectangular copper pillars are attached to bond pads of an electronic component, the copper pillars having a longitudinal length and a latitudinal second width. The latitudinal second width of the copper pillars is equal to and aligned with the first latitudinal width of the traces. Further, the longitudinal length of the copper pillars is parallel with the longitudinal direction of the trace and equal to the length of the bond pads. The copper pillars are mounted to the traces with solder joints.

Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.

Abstract: A ceramic multilayer substrate that includes a ceramic insulator layer, which includes a first layer, a second layer, and a third layer and in which the first layer is interposed between the second layer and the third layer, an inner pattern conductor, an outer pattern conductor, and outer electrodes. The ceramic insulator layer is interposed between the inner pattern conductor and the outer pattern conductor. The sintering shrinkage start temperatures of the second layer alone and the third layer alone in a green sheet state are higher than or equal to the sintering shrinkage stop temperature of the first layer alone in a green sheet state. The thickness of the ceramic insulator layer is 5.0 ?m to 55.7 ?m. The ratio of the total of the thickness of the second layer and the thickness of the third layer to the thickness of the first layer is 0.25 to 1.11.

Abstract: (1) A conductor layer is disposed on at least one surface of a dielectric layer, the dielectric layer including an intermediate layer and a pair or more of fluororesin layers disposed on both surfaces of the intermediate layer, in which the ratio of the total average thickness of the intermediate layer to the total average thickness of the fluororesin layers is 0.001 to 30, the relative dielectric constant of the intermediate layer is 1.2 to 10, the coefficient of linear expansion of the intermediate layer is ?1×10?4/° C. to 5×10?5/° C., and the adhesive strength between the fluororesin layer and the conductor layer is 300 g/cm or more.

Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.

Abstract: The present invention concerns a backplane electronic board (20) having on inner face (142) suitable for being connected to electronic board connectors (12) and an outer face (143) suitable for being connected to an outer connector (15), the backplane board (20) being characterized in that it has blind holes opening on the inner face (142) of same, and holes opening on the outer face (143) of same, the holes being suitable for receiving press-fit connection elements and forming therewith an electrical connection point.

Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.

Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.

Abstract: According to the present disclosure, a support structure for lighting devices, e.g. LED lighting devices, is provided with an electrically insulating core layer having a first and a second mutually opposed surfaces, with mounting locations for electrically-powered light radiation sources on the first surface, a network of electrically conductive lines printed on said first surface, at least some of said electrically conductive lines extending between the mounting locations and fixed locations on the first surface, and electrical distribution lines of electrically conductive material on the second surface of the core layer, and electrically conductive vias extending through core layer and electrically coupling the electrical distribution lines on the second surface with the electrically conductive lines at said fixed locations on the first surface.

Abstract: A flexible display apparatus is provided, including a flexible substrate including a bending area, an insulating layer formed on the flexible substrate and including at least one cutout at the bending area, and a plurality of wires configured following a surface shape of the insulating layer at the bending area. The at least one cutout includes sloped sidewalls protruding away from the flexible substrate.

Abstract: A touch sensor unit includes a substrate and a plurality of touch electrodes disposed on the substrate for generating sensing signals. Each of the touch electrodes includes an electrically insulating layer that is light-transmissible, and a plurality of nano-scale conducting elements distributed in the electrically insulating layer and electrically connected to one another. Each of the conducting elements includes a metal body that has a roughened surface, that has a twisted structure, or that is formed with a light light-absorbing member thereon.

Abstract: In a suspension board, a first insulating layer is formed on a support substrate. A ground layer and a power wiring trace are formed on the first insulating layer. The ground layer has electric conductivity higher than that of the support substrate. A second insulating layer is formed on the first insulating layer to cover the ground layer and the power wiring trace. A write wiring trace is formed on the second insulating layer to overlap with the ground layer. In a stacking direction of the support substrate, the first insulating layer and the second insulating layer, a distance between the ground layer and the write wiring trace is larger than a distance between the power wiring trace and the write wiring trace.

Abstract: A display device includes an array substrate and a counter substrate. On the array substrate, a TFT, a pixel electrode, an antenna coil, at least two external connection terminals, and a capacitor are provided. Two ends of the antenna coil are respectively connected to the at least two external connection terminals. The TFT includes a switching TFT. A set of the switching TFT and the capacitor or a plurality of sets of the switching TFT and the capacitor is provided. To the antenna coil, the set of the switching TFT and the capacitor or the plurality of sets of the switching TFT and the capacitor is connected.

Abstract: A flexible circuit board and an electronic device including a flexible circuit board are provided. The flexible circuit board may include a substrate having a bending area and a non-bending area, a wiring pattern layer provided on the bending area and the non-bending area, a plating layer provided on the wiring pattern layer and including an open area in an area corresponding to the bending area, and a protective layer that directly contacts one surface of the wiring pattern layer exposed at the open area and a side surface of the plating layer. The protective layer may have a larger thickness than a thickness of the plating layer.

Abstract: A flexible printed circuit board (PCB), a method for manufacturing the flexible PCB, and a PCB structure having the flexible PCB are disclosed. A flexible printed circuit board includes a first conductive pattern layer, a second conductive pattern layer, a plurality of first conductive pillars, and a plurality of second conductive pillars. Each of the plurality of first conductive pillars electrically connects to the first conductive pattern layer and is spaced from the second conductive pattern layer, and a plurality of second conductive pillars electrically connects to the second conductive pattern layer and is spaced from the first conductive pattern layer. The plurality of first conductive pillars and the plurality of second conductive pillars are exposed from one surface of the flexible printed circuit board to form a plurality of electrical contact pads.

Abstract: An electronic device includes a device controller and a microprocessor. The device controller is coupled to a device for controlling the device. The microprocessor is coupled to the device controller. The microprocessor obtains information regarding an amount of power consumption of the electronic device and dynamically determines an amount of current provided to the device according to the amount of power consumption. When the microprocessor determines that the amount of power consumption is greater than a threshold, the microprocessor determines to decrease the amount of current provided to the device.

Abstract: An electric distribution box includes a substrate, a first connector fitting part which includes first terminals, wherein one end portions of the first terminals are electrically connected to the substrate and the other end portions of the first terminals are disposed above the substrate so as to fit with the first connectors in a fitting direction parallel to the substrate, a second connector fitting part which includes a second terminal, wherein one end portion of the second terminal is electrically connected to the substrate and the other end portion of the second terminal is disposed above the substrate so as to fit with the second connector in a direction opposite to the fitting direction, electronic components on the substrate, a case body, and a cover which closes an opening part of the case body.

Abstract: An electronic component includes: a body containing a ceramic material; and an indication part formed on a surface of the body and including a base region and a marking region formed of a non-conductive paste on a portion of the base region.

Abstract: Disclosed are exemplary embodiments of thermal management and/or EMI (electromagnetic interference) mitigation materials with modified or custom colored exterior surfaces. The thermal management and/or EMI mitigation materials disclosed herein may comprise thermal interface materials (e.g., thermally-conductive pads or gap fillers, thermally-conductive dielectric materials, etc.), EMI shielding materials (e.g., EMI suppression materials, electrically-conductive thermal insulators, EMI absorbers etc.), microwave absorbers (e.g., microwave absorbing elastomers, microwave absorbing foams, EMI/RF/microwave absorbers, etc.), combinations thereof, etc. The thermal management and/or EMI mitigation materials disclosed herein may comprise combined thermal management and EMI mitigation materials, such as hybrid thermal/EMI absorbers, thermally-conductive microwave absorbers, hybrid absorber/thermal management materials usable for EMI mitigation, combined thermal interface and EMI shielding materials (e.g.