Abstract: A circuit board disclosed herein includes: two substrates opposed to each other, where a dielectric being interposed between the two substrates; a through hole formed in each of the two substrates and filled with the dielectric; a first conductor film formed on an inner surface of the through hole; and a second conductor film covering the through hole on a main surface of each of the two substrates on an opposite side to the dielectric, the second conductor film being connected to the first conductor film on the main surface side.

Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

Abstract: A display apparatus includes a printed circuit board (PCB). A power management integrated circuit (PMIC) is mounted on the PCB and is configured to generate first to fourth gate clock signals and first to fourth inversion gate clock signals. A phase of the first gate clock signal partially overlaps a phase of the second to fourth gate clock signal. Each of the first to fourth inversion gate clock signals has a phase opposite to that of a respective one of the first to fourth gate clock signals. A gate driver generates a plurality of gate signals based on the first to fourth gate clock signals and the first to fourth inversion gate clock signals and applies the plurality of gate signals to a plurality of gate lines. A display panel is connected to the plurality of gate lines.

Abstract: An array substrate and a display apparatus including the array substrate. The array substrate includes: a plurality of signal lines aligned in a display area of the array substrate; a plurality of signal pads aligned in a non-display area of the array substrate; a plurality of fan-out lines aligned in the non-display area and respectively connected to the signal lines and the signal pads; a plurality of auxiliary lines respectively overlapping and insulated from the fan-out lines; and a plurality of connection lines connecting in parallel at least two of the auxiliary lines that are adjacent to each other.

Abstract: A printed circuit board includes a main body of laminate structures, and a metal piece. The main body has a first opening and a second opening. The metal piece is held by the laminate structures of the main body. The metal piece has a first face and a second face opposite to the first face. The first opening and the second opening respectively extend to the first face and the second face of the metal piece. A semiconductor optical device can be mounted on the first face of the metal piece, in the first opening.

Abstract: A carbene-coated metal foil is produced by applying an N-heterocyclic carbene (NHC) compound to one or more surfaces of a metal foil (e.g., an electrodeposited copper foil having a surface that is smooth and non-oxidized). The NHC compound contains a matrix-reactive pendant group that includes at least one of a vinyl-, allyl-, acrylic-, methacrylic-, styrenic-, amine-, amide- and epoxy-containing moiety capable of reacting with a base polymer (e.g., a vinyl-containing resin such as a polyphenylene oxide/triallyl-isocyanurate (PPO/TAIC) composition). The NHC compound may be synthesized by, for example, reacting a halogenated imidazolium salt (e.g., 1,3-bis(4-bromo-2,6-dimethylphenyl)-4,5-dihydro-1H-imidazol-3-ium chloride) and an organostannane having a vinyl-containing moiety (e.g., tributyl(vinyl)stannane) in the presence of a palladium catalyst.

Abstract: An interconnection substrate having a barcode includes a core layer, an interconnection layer over a first surface of the core layer, an insulating layer to cover the interconnection layer, and one or more additional interconnection layers over the insulating layer, wherein the barcode includes cells arranged at spaced intervals, and a cell pattern is made by forming penetrating holes through the core layer in some of the cells but not in remaining ones of the cells, wherein the penetrating holes are filled with resin, and an end face of the resin is exposed on the same side as the first surface such that the interconnection layer is situated in a surrounding area of the end face but not over the end face, and wherein a number of interconnection layers over the end face is smaller than a number of interconnection layers in the surrounding area of the end face.

Abstract: A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern.

Abstract: A method of manufacturing an electronic module includes providing a conductive strip and a dielectric material. The method includes coating the dielectric material and the conductive strip to form a layered structure having a conductive layer defined by the conductive strip and a dielectric layer defined by the dielectric material. The method includes applying a carrier strip to the layered structure. The method includes processing the conductive layer to form a circuit while the layered structure is on the carrier strip. The method includes removing the carrier strip from the layered structure. The method includes applying the layered structure with the circuit to an electronic module substrate.

Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.

Abstract: A PCB includes a PCB body at least including a first metal layer, a second metal layer, and a first ground layer sandwiched therebetween; and a pair of transmission lines including a first transmission line conductor and a second transmission line conductor. The first transmission line conductor is located in the first metal layer which has two straight line sections at its two ends and a curved line section at its middle, the second transmission line conductor has two straight line sections at its two ends which are located in the first metal layer and a cross-via structure at the middle which has a buried trace buried in the second metal layer, and the curved line section and the buried trace are isolated by the first ground layer. Skew effect of the differential transmission circuit is reduced, thereby improving the signal transmission quality and improve signal transmission speed.

Abstract: Various embodiments includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may include a magnetic material directly contacts one of the conducting patterns and the substrate. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract: A handle substrate having at least one metallization region is provided on a stressor layer that is located above a base substrate such that the at least one metallization region is in contact with a surface of the stressor layer. An upper portion of the base substrate is spalled, i.e., removed, to provide a structure comprising, from bottom to top, a spalled material portion of the base substrate, the stressor layer and the handle substrate containing the at least one metallization region in contact with the surface of the stressor layer.

Abstract: A packaging substrate includes a holder, a first conductive pad disposed on the holder, a core layer disposed on the holder, a circuit layer disposed on the core layer, a plurality of conductive vias disposed in the core layer, and an insulating protection layer disposed on the core layer, wherein the first electrical pad is embedded in the core layer. By combining the holder on one side of the packaging substrate, cracks due to over-thinness can be prevented during transferring or packaging. A method of fabricating the packaging substrate, a package structure having a holder, a method of fabricating the package structure are also provided.

Abstract: A component-embedded substrate includes a substrate portion, an embedded electronic component, and a resin portion. The substrate portion has inner electrodes on an inner principal surface. The embedded electronic component has terminal electrodes and is mounted to the substrate portion via solder fillets adhering to the respective terminal electrodes and the respective inner electrodes. The resin portion is stacked on the substrate portion, with the embedded electronic component embedded therein. The resin portion includes a no-filler-added layer and a filler-added layer. The no-filler-added layer extends from the inner principal surface to a height which allows at least the solder fillets to be covered. The filler-added layer contains an inorganic filler and extends from an interface with the no-filler-added layer to a height which allows at least the embedded electronic component to be covered.

Abstract: The present application describes various embodiments regarding systems and methods for providing efficient heat rejection for a lightweight and durable compact computing system having a small form factor. The compact computing system can take the form of a desktop computer. The desktop computer can include a monolithic top case having an integrated support system formed therein, the integrated support system providing structural support that distributes applied loads through the top case preventing warping and bowing. A mixed flow fan is utilized to efficiently pull cooling air through the compact computing system.

Abstract: A method for fabricating a substrate structure is provided, which includes the steps of: disposing at least a strengthening member on a carrier; sequentially forming a first circuit layer and a dielectric layer on the carrier, wherein the strengthening member is embedded in the dielectric layer; forming a second circuit layer on the dielectric layer; removing the carrier; and forming an insulating layer on the first circuit layer and the second circuit layer. The strengthening member facilitates to reduce thermal warping of the substrate structure.

Abstract: Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a “known good” substrate on a support substrate.

Abstract: A multilayer ceramic capacitor is configured such that “a” is a distance in a height direction between an effective portion and a first principal surface; “b” is a distance in a length direction between a first end surface and the effective portion in the length direction; “c” is a thickness of the thickest portion of a first base layer provided over the first principal surface; “d” is a distance in the length direction between the thickest portion of the first base layer provided over the first end surface and a portion of the first base layer located over the first principal surface and closest to a second end surface; and “e” is a maximum thickness of a portion of the first base layer provided over the first end surface; and f: the height of the ceramic body, and 2?(c·d+e·f/2)/(a·b)?6 is satisfied.

Abstract: A method of soldering can include: providing a first electronic component having a first buttoned soldering pad including a first soldering pad and one or more first button heads protruding from a first surface of the soldering pad; providing a second electronic component having a soldering pad; and soldering the first buttoned soldering pad to the soldering pad. The method includes introducing solder to spaces around the one or more first buttons of the first buttoned soldering pad. The method includes introducing a first solder to spaces around the one or more first buttons of the first buttoned soldering pad; introducing a second solder to spaces around one or more second buttons of a second buttoned soldering pad of the first electronic component; and forming spaces between the first and second solder that electronically insulate the first solder from the second solder.

Abstract: A three-dimensional interconnect structure having a top surface, a first coaxial conductor, and a shielded chamber is disclosed. The first coaxial conductor is filled with a solid dielectric medium. The first coaxial conductor has a segment that runs parallel to the top surface and a segment connects the first coaxial conductor to the top surface. Conductive pads on the top surface are adapted to receive a signal and couple that signal to the first coaxial conductor at the top surface. The shielded chamber contains a device connecting two conductors that are part of the three-dimensional interconnect structure to one another in that chamber. The shielded chamber is filled with the solid dielectric medium. The structure is a solid block composed of a mixture of metal structures interspersed with the solid dielectric medium.

Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.

Abstract: A three-dimensional laminated wiring substrate is provided and includes a plurality of wiring substrates disposed on top of each other. Each of the plurality of wiring substrates includes an insulating film and a conductor pattern. The insulating film is disposed along a surface to provide a three-dimensional surface. The conductor pattern is disposed on and extending along the three-dimensional surface.

Abstract: An electrical conductor including a substrate, a first conductive layer including graphene, and a second conductive layer including a conductive metal nanowire, wherein the first conductive layer and the second conductive layer are disposed on the substrate, wherein the first conductive layer is disposed between the substrate and the second conductive layer or on the second conductive layer, wherein the first conductive layer has a first surface facing the second conductive layer and a second surface which is opposite to the first surface, and wherein, in the first surface and the second surface, the graphene is p-doped with a p-type dopant.

Abstract: An electronic device includes: a wiring substrate;a plurality of components having different heights mounted on one surface of the wiring substrate; and a flexible substrate, the flexible substrate being formed by laminating on a one surface side of the wiring substrate, that covers the plurality of components, the flexible substrate including a first portion that covers, among the plurality of components, one or more first components that have heights that are equivalent to or lower than a first height, and a second portion that covers, among the plurality of components, one or more second components other than the one or more first components, a first rigidity of the first portion being higher than a second rigidity of the second portion.

Abstract: Disclosed is a method for determining a contact resistance of an H bridge including four transistors, each transistor having a point of connection to two neighboring transistors, a bond being produced in each case between a connection point lying between two transistors and an access terminal. The method includes: acting on the open/closed state of the transistors of the bridge so that the transistors on either side of the connection point corresponding to the access terminal are open; applying a determined voltage to an access terminal; determining the current flowing through the bond corresponding to the access terminal; grounding an access terminal neighboring the access terminal if this neighboring access terminal is not already connected to ground; and measuring the voltage at the other neighboring access terminal.

Abstract: A package includes a corner, a device die having a front side and a backside, and a molding material molding the device die therein. A plurality of redistribution lines is on the backside of the device die. The plurality of redistribution lines includes a plurality of metal pads. A polymer layer contacts the plurality of metal pads. A plurality of openings is formed in the polymer layer, with the plurality of metal pads aligned to and exposed to the plurality of openings. The plurality of openings includes a corner opening that is elongated and an additional opening farther away from the corner than the corner opening. The additional opening is non-elongated.

Abstract: A mounting jig for a semiconductor device includes an insulated circuit board positioning jig positioning an insulated circuit board by housing the insulated circuit board at a predetermined position, a tubular contact element positioning jig having a plurality of positioning holes at predetermined positions to insert a plurality of tubular contact elements respectively, and a tubular contact element press-down jig for pressing down the plurality of tubular contact elements inserted into the respective positioning holes in the tubular contact element positioning jig.

Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.

Abstract: A composite substrate has a rigid substrate that includes: a core layer, a first laminated layer on a first surface of the core layer, and a second laminated layer on a second surface of the core layer, the rigid substrate having a cutout in the core layer and the second laminated layer on one side face of the rigid substrate; and a flexible substrate inserted into the cutout in the rigid substrate on the one side face and laterally and externally protruding from the one side face of the rigid substrate, wherein the rigid substrate has opposing walls each constituted of the second laminated layer and the core layer erected on the first laminated layer to define inner side faces, respectively, of the cutout so as to accommodate the flexible substrate in a direction perpendicular to a direction in which the side face of the rigid substrate extends.

Abstract: A module component includes a substrate including a liquid crystal polymer resin sheet, and an electronic component mounted on the substrate by ultrasonic bonding, wherein the electronic component includes a plurality of first substrate connecting electrodes including respective planar conductors provided on a substrate mounting surface separately from each other, and connected at a same potential or substantially a same potential, and the substrate includes a first component connecting electrode including a planar conductor provided on a component loading surface, and bonded to the plurality of first substrate connecting electrodes.

Abstract: A printed wiring board includes a first insulating layer, a first conductor layer formed on first surface of the first insulating layer, a second conductor layer formed on second surface of the first insulating layer, a first via structure formed in the first insulating layer such that the first via structure is connecting the first and second conductor layers, a second insulating layer formed on the second surface of the first insulating layer such that the second conductor layer is embedded into the second insulating layer, a third conductor layer formed on the second insulating layer, and a second via structure formed in the second insulating layer such that the second via structure is connecting the second and third conductor layers. The second conductor layer includes a dedicated wiring layer which transmits data between two electronic components to be mounted to the first surface of the first insulating layer.

Abstract: A circuit board includes an insulating layer, a ground layer formed on a first surface of the insulating layer and including a plurality of openings arranged in first and second surface directions, each of the openings having a shape of a polygon having five or more sides, and a wiring layer formed on a second surface of the insulating layer opposite to the first surface.

Abstract: An interposer includes an insulating plate including insulating layers and having first, second, third and fourth surfaces such that the second surface is on the opposite side of the first surface, the third surface is perpendicular to the first surface, the fourth surface is on the opposite side of the third surface, and the insulating layers are laminated on the third surface, and conductor layers formed in the insulating plate such that each conductor layer is interposed between adjacent insulating layers and includes straight conductors having first electrodes exposed from the first surface and second electrodes exposed from the second surface, respectively.

Abstract: In an electronic device having a compact form factor, such as a head mounted display device, flexible printed circuits may be utilized to provide interconnects between EMI-generating peripheral components and other components in the device such as those populated on main circuit boards. Coverlays utilized to protect circuit traces and ground planes in the flexible printed circuits are configured with openings that can expose ground planes at various locations throughout the electronic device. Electrical pathways are formed by conductive foam, conductive adhesives, and/or other conductive materials between the exposed ground planes and a device ground to establish multiple ground loops throughout the device that shunt EMI energy that is generated by electronic components and circuits during device operation. The coverlay openings can be positioned on the flexible printed circuits so that the lengths of the ground loops are minimized to enhance overall EMI emission management performance.

Abstract: A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.

Abstract: A cable connector includes a connection end portion of a flexible board, in which a rectangular reinforcing plate molded of a conductive resin material is fixed to part of an upper surface of a ground plate. The connection end portion of the flexible board is electrically connected to a printed circuit board through the cable connector.

Abstract: A display apparatus comprises: a display panel configured to display an image; a touch panel disposed on the display panel; and a circuit board electrically connected to each of the display panel and the touch panel, the circuit board including a first surface and a second surface opposite the first surface. The circuit board includes: a first circuit portion including a first connection disposed in the first surface and electrically connected to the display panel; a second circuit portion including a second connection disposed in the second surface and electrically connected to the touch panel; and a bending portion configured to link the first circuit portion to the second circuit portion, and curving in a direction toward the first circuit portion.

Abstract: An elastic flexible substrate includes an insulating base material having a first insulating film and a second insulating film, and a plurality of wires, each of which is disposed on one of the first insulating film and the second insulating film. The insulating base material has a plurality of bonding portions that are surface-bonded, openings are formed between the bonding portions, and two of the plurality of wires are electrically connected in the bonding portions.

Abstract: A sensing structure includes a sensing unit, a periphery circuit, and a connecting circuit. The connecting circuit connecting the sensing unit and the periphery circuit includes a connecting pattern. In an embodiment, the connecting pattern has at least two line widths. The line width of a part of the connecting pattern connecting the periphery circuit is greater than the line width of a part of the connecting pattern connecting the sensing unit. In an embodiment, the connecting pattern includes a mesh pattern having at least two mesh densities. The mesh density of a part of the mesh pattern connecting the periphery circuit is greater than the mesh density of a part of the mesh pattern connecting the sensing unit. In an embodiment, the connecting circuit includes lines between and connecting a single sensing series of the sensing unit and a periphery wire of the periphery circuit.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.

Abstract: The present disclosure provides a flexible printed circuit board (FPCB), a method for manufacturing the FPCB, and a capacitive touch display device with the FPCB. The FPCB comprises an FPCB substrate and a common electrode voltage (VCOM) filter circuit arranged on the FPCB substrate. The FPCB further includes one or more filter units. the filter units comprises: a conduction layer, arranged on the FPCB substrate and electrically connected to a VCOM output end of the VCOM filter circuit; an isolation layer, arranged on the conduction layer; and a shielding film, which is grounded, arranged on the isolation layer and arranged parallel with the conduction layer.

Abstract: A printed wiring board includes a first circuit board having a first surface and a second surface on the opposite side with respect to the first surface, and a second circuit board having a third surface and a fourth surface on the opposite side with respect to the third surface and having a mounting area on the third surface of the second circuit board. The first circuit board is laminated on the third surface of the second circuit board such that the first surface of the first circuit board faces the third surface of the second circuit board, and the first circuit board includes reinforcing material and has an opening portion exposing the mounting area of the second circuit board.

Abstract: Provided is a light receiving device including a transparent electrode and a method of manufacturing the light receiving device. A transparent electrode is formed so as to be in contact with a photoelectric conversion layer which absorbs light to generate electric energy, and the transparent electrode is formed by using a resistance change material which has high transmittance with respect to light in the entire wavelength range and of which resistance state is to be changed from a high resistance state into a low resistance state if a voltage exceeding a threshold voltage inherent in the resistance change material so that conducting filaments are formed in the transparent electrode. Accordingly, since the transparent electrode has high transmittance characteristic with respect to the light in the entire wavelength range and high conductivity characteristic, the light receiving device also has high photoelectric conversion efficiency and good electric characteristics.

Abstract: Solder material used in soldering of an Au electrode including Ni plating containing P includes Ag satisfying 0.3?[Ag]?4.0, Bi satisfying 0?[Bi]?1.0, and Cu satisfying 0<[Cu]?1.2, where contents (mass %) of Ag, Bi, Cu and In in the solder material are denoted by [Ag], [Bi], [Cu], and [In], respectively. The solder material includes In in a range of 6.0?[In]?6.8 when [Cu] falls within a range of 0<[Cu]<0.5, In in a range of 5.2+(6?(1.55×[Cu]+4.428))?[In]?6.8 when [Cu] falls within a range of 0.5?[Cu]?1.0, In in a range of 5.2?[In]?6.8 when [Cu] falls within a range of 1.0<[Cu]?1.2. A balance includes only not less than 87 mass % of Sn.

Abstract: Provided is a manufacturing method for an array substrate, which relates to the technical field of displaying and comprises the steps of: S1: forming a pattern which comprises a first gate electrode (2) on a substrate (1); S2: forming a second gate electrode (4) above the first gate electrode (2) on the substrate (1) after step S1, and conducting oxidation treatment on the surface of the second gate electrode (4) to form a gate-insulating layer, the first gate electrode (2) and the second gate electrode (4) forming a gate electrode together; and S3: forming a layer-level structure of a pattern which comprises an active layer, source and drain electrodes, a data line, a passivation layer and a pixel electrode on the substrate after step S2. Also provided are an array substrate and a display device.

Abstract: A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed on a first surface of the printed circuit board and corresponding to the memory chips; and resistance units disposed on a second surface of the printed circuit board and corresponding to the data buffers.

Abstract: According to one embodiment, a disk device includes a disk-shaped recording medium, a head which processes data on the recording medium, and a housing accommodating the recording medium and the head. The housing includes a base with a side wall, and a cover having a welded portion welded to the side wall by laser welding. The welded portion includes a first welded portion welded to a first region of the side wall and having weld beads with a first shape, and a second welded portion welded to a second region of the side wall and having welded beads with a second shape different from the first shape.

Abstract: Circuit boards and computer-implemented methods for designing circuit boards are disclosed. In one embodiment, a method of designing a circuit board having an insulator substrate includes determining, by a computer, a plurality of thermal conductor traces that is arranged to direct heat flux generated by a heat generating component away from a temperature sensitive component, and determining a plurality of electrical connection traces based on an input schematic. At least a portion of the plurality of electrical connection traces incorporate at least a portion of the plurality of thermal conductor traces to define a conductive trace pattern that electrically connects pins of two or more components located on the substrate. The conductive trace pattern includes the plurality of thermal conductor traces and the plurality of electrical connection traces. Disruption of the plurality of thermal conductor traces is avoided while determining the plurality of electrical connection traces.