Abstract: [Object] To provide a method for manufacturing a touch sensor capable of concurrently forming routed circuit patterns on both surfaces of a base film and capable of aligning the routed circuit patterns on the top and bottom surfaces with each other with high accuracy. [Solution] A method for manufacturing a touch sensor includes forming electrode patterns on both surfaces of a base film through concurrent light exposure on both surfaces and development using photosensitive electrically conductive films each including a support film, an electrically conductive layer disposed on the support film and containing an electrically conductive fiber, and a second photosensitive resin layer disposed on the electrically conductive layer. Routed circuit patterns obtained by patterning the light-shielding metal layers are formed in advance on both surfaces of the base film.

Abstract: Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure-to-circuit board protection. The tamper-respondent assemblies include a circuit board, and an enclosure mounted to the circuit board along an enclosure-to-board interface. The enclosure facilitates enclosing at least one electronic component coupled to the circuit board within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and includes one or more tamper-detect circuits including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface. The conductive trace(s) includes stress rise regions to facilitate tamper-detection at the enclosure-to-board interface. An adhesive is provided to secure the enclosure to the circuit board. The adhesive contacts, at least in part, the conductive trace(s) of the tamper-detect circuit(s) at the enclosure-to-board interface, including at the stress rise regions of the conductive trace(s).

Abstract: A package substrate with embedded noise shielding walls is disclosed. One of the embodiment comprises a signal line S sandwiched by a left shielding wall W1 and a right shielding wall W2. The signal line S, left shielding wall W1, and the right shielding wall W2 are embedded in a dielectric layer.

Abstract: In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.

Abstract: Anisotropic conductive film produced that a light-transmitting transfer die having openings with conductive particles disposed therein is prepared, and photopolymerizable insulating resin squeezed into openings to transfer conductive particles onto the surface of the photopolymerizable insulating resin layer, first connection layer is formed which has a structure in which conductive particles are arranged in a single layer in a plane direction of photopolymerizable insulating resin layer and the thickness of photopolymerizable insulating resin layer in central regions between adjacent ones of the conductive particles is smaller than thickness of photopolymerizable insulating resin layer in regions in proximity to conductive particles; first connection layer is irradiated with ultraviolet rays through light-transmitting transfer die; release film is removed from first connection layer; second connection layer is formed on the surface of first connection layer opposite to light-transmitting transfer die; and th

Abstract: An insulated glazing unit can include a spacer frame disposed between a first substrate from a second substrate and forming a portion of a sealed boundary and a flexible circuit extending through the sealed boundary. In an embodiment, the flexible circuit includes a flexible ribbon having a total length, LA, and an effective length, LE, and wherein LE is less than LA. In another embodiment, the flexible circuit includes an expandable portion adapted to expand a length of the flexible circuit to accommodate: relative movement between two or more portions of the insulated glazing unit, resizing of one or more portions of the insulated glazing unit, or any combination thereof.

Abstract: A flexible touch screen panel includes a thin film substrate including a first section and a second section and first sensing electrodes disposed in the first section and the second section, the first sensing electrodes being connected to one another along a first direction. The first sensing electrodes include a first stack structure in the first section and a second stack structure in the second section, the second stack structure being different from the first stack structure.

Abstract: A semiconductor device is disclosed including semiconductor die formed with functionally redundant main and optional die bond pads. In examples, the optional die bond pad is configured to be optionally redundant to the main die bond pad by forming the optional die bond pad with first and second electrically isolated portions, and electrically interconnecting the main die bond pad with the first portion of the second die bond pad. The second die bond pad may or may not be made redundant to the first die bond pad depending on whether an electrically conductive material is deposited on the first and second portions of the optional die bond pad.

Abstract: A method of fabricating a composite conductive film is provided. The method includes providing, as a matrix, a layer of cross-linkable polymer, where the cross-linkable polymer is in a non-cross-linked state. The method further includes introducing inorganic nanowires upon a surface of the layer of cross-linkable polymer. The inorganic nanowires are, in isolated form, characterized by a first conductivity stability temperature. The method further includes embedding at least some of the inorganic nanowires into the layer of cross-linkable polymer to form an inorganic mesh, thereby forming the composite conductive film. The method further includes cross-linking the polymer within a surface portion of the composite conductive film. Cross-linking the polymer within the surface portion of the composite conductive film results in the surface portion having a second conductivity stability temperature that is greater than the first conductivity stability temperature.

Abstract: An electronic component mounting device, including: a board conveyance device which conveys and positions a board on which an electronic component is mounted; a mounting device which positions and mounts the electronic component to a mounting position of the board; a loading device which picks up multiple engaged members (clips), and positions and loads the engaged members to a loading position of the board; and a placing device which picks up a cover component that covers the mounted electronic component and that is provided with an engaging portion at a predetermined position, and positions and places the cover component to a position such that the engaging portion corresponds to the engaged member.

Abstract: An electronic component package includes a substrate having an upper surface. Traces on the upper surface of the substrate extend in a longitudinal direction. The traces have a first latitudinal width in a latitudinal direction, the latitudinal direction being perpendicular to the longitudinal direction. Rectangular copper pillars are attached to bond pads of an electronic component, the copper pillars having a longitudinal length and a latitudinal second width. The latitudinal second width of the copper pillars is equal to and aligned with the first latitudinal width of the traces. Further, the longitudinal length of the copper pillars is parallel with the longitudinal direction of the trace and equal to the length of the bond pads. The copper pillars are mounted to the traces with solder joints.

Abstract: The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

Abstract: A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.

Abstract: Disclosed is a printed circuit hoard. The printed circuit board includes a plurality of insulation layers and a plurality of pattern layers alternately stacked. The printed circuit board includes a plurality of device areas on which semiconductor packages are mounted and a peripheral area adjacent the device areas. An electrostatic discharge pattern is in a respective pattern layer among the plurality of pattern layers and is disposed at a boundary region between a respective device area of the plurality of device areas and the peripheral area.

Abstract: A substrate includes a ceramic layer, a metal layer fixed in a planar manner on a surface side of the ceramic layer and a cutout arranged in an edge region of the metal layer. The cutout in the edge region codes information. A multiple substrate having a plurality of these substrates is also provided, as is a method for producing the substrate.

Abstract: The present application discloses a display substrate having a first area for bonding a driver integrated circuit. The display substrate includes a base substrate; an overcoat layer on the base substrate in a second area of the display substrate; the overcoat layer having an interface portion in an area abutting the first area, the interface portion having a plurality of teeth and a plurality of slits, two adjacent teeth being spaced apart by a slit; and a conductive line layer on a side of the overcoat layer proximal to the base substrate, having a plurality of conductive lines extending from the second area to the first area; each of the plurality of conductive lines electrically connected to a signal line in the second area.

Abstract: A touch sensor member includes a substrate sectioned into a display region and a design region; a conductive pattern formed on the display region and having a line width of 2 to 6 ?m; and a conductive pattern formed on the design region and having a line width of 7 to 100 ?m, wherein the conductive pattern having a line width of 2 to 6 ?m and the conductive pattern having a line width of 7 to 100 ?m have the same composition.

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract: We describe a method of manufacturing a plurality of electronic devices. The method comprises manufacturing a multi-device motherboard bearing programmable device circuit boards, each of these with an electronic device comprising a processor and programmable memory and being detachable from the motherboard except for one of more frangible links, at least one of these links comprising a programming connection. A device programming region bears a motherboard processor and program memory for programming the device circuit boards. Code for at least one application program for said electronic device is stored in said motherboard program memory. A user interface for the multi-device motherboard allows a user to configure each of the electronic devices to perform a defined function.

Abstract: An insulating board includes a first portion that is relatively thick and a second portion that is relatively thin. The first and second portions have different thicknesses so that a step is provided therebetween. The insulating board includes a first land conductor on a first mounting surface of the first portion at a side at which the step is provided, a second land conductor on a second mounting surface of the second portion at the side at which the step is provided, and an insulating protection film on the first mounting surface so that a portion of the first land conductor is exposed and another portion of the first land conductor is covered. An electronic component is soldered to the first land conductor. Another electronic component is joined to the second land conductor by an anisotropic conductive film that covers the second land conductor.

Abstract: A cable connection method is provided. In a cable connection structure, a connection agent in which fine solder particle are densely scattered in a thermosetting resin-based adhesive is interposed between a connection portion of a flexible printed cable (FPC) cable in which a shield layer is formed on one surface side of a signal layer and a connection portion on a substrate side. Then, the connection portion of the FPC cable and the connection portion on the substrate side are solder connected by heating. A shield layer corresponding to the connection portion of the FPC cable and/or a region portion up to a position separated from the base end side of the connection portion of the FPC cable by a predetermined length is configured with a conductive mesh structure body. The other region of the shield layer contains a conductive flat plate structure.

Abstract: A flexible cable may include: a flexible substrate having a first surface and a second surface that are on opposite sides of the flexible substrate; a first conductive line formed on the first surface of the flexible substrate, and structured to transmit a signal having a first frequency; a second conductive line formed on the first surface of the flexible substrate, and structured to transmit a signal having a second frequency lower than the first frequency; and a ground line formed on the second surface of the flexible substrate, and comprising a first region overlapping the first conductive line and a second region overlapping the second conductive line. The first and second regions may have different shapes.

Abstract: A wiring substrate includes a first insulation layer having a component mounting area and a mark formation area, an electrode pad arranged in the component mounting area and having an upper surface exposed from the first insulation layer and a side surface and a lower surface embedded in the first insulation layer, and a mark arranged in the mark formation area and formed of an insulation pattern layer having an upper surface exposed from the first insulation layer and a side surface and a lower surface embedded in the first insulation layer. A color of the first insulation layer and a color of the insulation pattern layer are different.

Abstract: Tamper-proof electronic packages and fabrication methods are provided including an enclosure enclosing, at least in part, at least one electronic component within a secure volume, a two-phase dielectric fluid within the secure volume, and a tamper-respondent detector. The tamper-respondent detector monitors, at least in part, temperature and pressure of the two-phase dielectric fluid. In operation, the two-phase dielectric fluid deviates from an established saturation line of the two-phase dielectric fluid within the secure volume with an intrusion event into the secure volume, and the tamper-respondent detector detects, from the monitoring of the temperature and pressure of the two-phase dielectric fluid, the deviation from the established saturation line, and thereby occurrence of the intrusion event.

Abstract: The present invention provides a light-transmitting conductor comprising: a substrate; and a conduction layer on the substrate, wherein the conduction layer comprises a conductive material, and the conduction layer has a pattern corresponding to a network formed such that nanostructures are arranged to intersect with each other that includes a substrate and a conduction layer on the substrate.

Abstract: The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.

Abstract: The objective of the present invention is to improve reliability in a solder connection portion between an electronic component and a wiring pattern. A pair of wiring patterns (31A and 31B) are formed on a circuit wiring board (30) with an insulation layer (37) therebetween. Each wiring pattern (31A and 31B) has a land (33a or 33b) and a wiring portion (34a or 34b) that is narrower than the land. By way of solder (42), a chip component (41) is soldered to the lands (33a and 33b). The x (width) direction center (Xa) of each connection portion (53) where a respective wiring portion (34a or 34b) is connected to a respective land (33a or 33b) is disposed at a position that is outside of both the region in which a region of predetermined width (Wc) of the chip component (41) extends in the x (longitudinal) direction, and the region in which a region of predetermined length (Lc) of the chip component (41) extends in a y (transverse) direction.

Abstract: The present invention relates to a substrate for an integrated circuit package and, more specifically, to a substrate for an integrated circuit package, which reduces mismatch of coefficients of thermal expansion with a semiconductor chip, thereby preventing or minimizing warpage during a reflow process.

Abstract: An extensible flexible printed circuit board sets one or a plurality of flexible printed circuit boards each including a plurality of conductive layers and an insulating layer as a base circuit board, and includes: component mounting parts which are provided at least at parts of the base circuit board, and capable of mounting electronic components; an extensible conductive part which is provided at least at a part of the base circuit board, includes a plurality of joint parts each intersecting a center line in an extension/contraction direction and a plurality of curved parts each continuing from an end part of each joint part and curve, and exhibits extensibility by the curved parts curving to open or close; and a covering member whose material is a flexibly deformable elastomer, and which covers the component mounting parts and the extensible conductive part.

Abstract: A carrier plate includes a substrate and at least one conductor track. The conductor track includes a first layer, which is applied directly on the substrate, and a second layer, which is arranged on the first layer. The second layer includes a supply line region and a soldering region. Furthermore, the second layer is completely interrupted between the supply line region and the soldering region. A device can be produced with a carrier plate and an electrical component arranged on the carrier plate.

Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

Abstract: Various methods related to antennas and embodiments of antennas are presented. The antenna may include an upper arm, wherein the upper arm is substantially parallel to a ground plane and is electrically coupled with at least a ground shorting structure, a support structure, and a feed structure. The antenna may include the ground shorting structure, which may be at a first end of the upper arm. The antenna may include the support structure, which may be at a second end of the length of the upper arm and may support the upper arm. The antenna may also include the feed structure, which is configured to provide a signal for wireless transmission, the feed structure may be attached to a side of the length of the upper arm.

Abstract: A wired circuit board, including a metal supporting layer; an insulating layer formed on one side of the metal supporting layer in a thickness direction thereof; and a conductive layer having a plurality of terminal portions placed to be spaced apart from each other and formed on one side of the insulating layer in the thickness direction. The insulating layer has a first opening which is formed to include the plurality of terminal portions, and the metal supporting layer includes a second opening formed to include the plurality of terminal portions, when projected in the thickness direction. The wired circuit board further includes at least one reinforcing insulating portion which is placed between the plurality of terminal portions in the first opening, and/or at least one reinforcing metal supporting portion which is placed between the plurality of terminal portions in the second opening, when projected in the thickness direction.

Abstract: A base insulating layer and a cover insulating layer of a first printed circuit board are formed of a first insulating material, and a base insulating layer and a cover insulating layer of a second printed circuit board are formed of a second insulating material. During inspection of the first printed circuit board, the first printed circuit board is irradiated with first light having a peak wavelength in a first wavelength range, and an image is produced based on reflected light from the first printed circuit board. During inspection of the second printed circuit board, the second printed circuit board is irradiated with second light having a peak wavelength in a second wavelength region different from the first wavelength region, and an image is produced based on reflected light from the second printed circuit board.

Abstract: In various embodiments, an organic light-emitting organic is provided. The organic light-emitting component may include a first electrode layer, an organic functional layer structure over the first electrode layer, and a second electrode layer over the organic functional layer structure. The second electrode layer and the organic functional layer structure are divided into subregions which are arranged laterally next to one another, which are respectively at least partially separated from one another. A plurality of the subregions are electrically connected to at least two neighboring subregions by at least two corresponding connecting elements with are formed by the second electrode layer and the organic functional layer structure.

Abstract: A circuit board assembly of an information handling system has an adjacent pair of vias that carry differential communication signal through printed circuit board (PCB) substrates. Pairs of ground vias each having a first ground via and a second ground via placed symmetrically on both sides of a virtual ground plane that passes between the adjacent pair of vias. Ground vias are placed at a substantially identical radius from a respective one of the adjacent pair of vias that is on the same side of the virtual ground plane. First ground via(s) are annularly spaced substantially equally from each other and from a pair of reference points on the virtual ground plane that are each radially spaced from both of the adjacent pair of vias by the substantially identical radius. The second ground via(s) are annularly spaced from each other and the pair of reference points.

Abstract: An embedded layered inductor is provided that includes a first inductor layer and a second inductor layer coupled to the first inductor layer. The first inductor layer comprises a patterned metal layer that may also be patterned to form pads. The second inductor layer comprises metal deposited in a dielectric layer adjacent the patterned metal layer.

Abstract: High-speed interconnects for printed circuit boards and methods for forming the high-speed interconnects are described. A high-speed interconnect may comprise a region of a conductive film having a reduced surface roughness and one or more regions that have been treated for improved bonding with an adjacent insulating layer. Regions of reduced roughness may be used to carry high data rate signals within PCBs. Regions treated for bonding may include a roughened surface, adhesion-promoting chemical treatment, and/or material deposited to improve wettability of the surface and/or adhesion to a cured insulator.

Abstract: An image pickup apparatus for an endoscope of the present invention includes a first circuit board on which a lead portion, a window portion in which a part of the lead portion is exposed, and a second circuit board on which a circuit pattern is fixed by soldering to the lead portion exposed on the window portion, and the lead portion that is exposed on the window portion extends from one end side of the window portion to the other end side, and has an enlarged end portion of the lead portion that is placed between two or more insulating layers and is formed with a larger width than a width of the lead portion in the window portion, at the other end side.

Abstract: A circuit board is provided including a top ground plane, a bottom ground plane, and a pin field of a connector with a plurality of pins that includes a plurality of differential pin pairs, one or more ground pins, and one or more sideband pins. At least a particular one of the sideband pins is positioned within the pin field adjacent to a first pin of a first one of the differential pin pairs. One or more ground vias are provided on the circuit board positioned to correspond to the particular sideband pin.

Abstract: A method for propagating a signal from an output driver on a PCB to a number of chips on the PCB. The signal is propagated from a first transmission line connected to the output driver, to a second transmission line connected to the first transmission line and a first chip, and to a third transmission line connected to the first transmission line and a second chip. The second transmission line has a length greater than or equal to 10 times the length of the first transmission line, and the third transmission line has a length greater than or equal to 10 times the length of the first transmission line. The lengths of the first transmission line, the second transmission line, and the third transmission line cause a reduction in reflections of the signal due to a change in impedance at a junction of the first, second, and third transmission lines.

Abstract: A touch window according to an embodiment includes a substrate; a sensing electrode disposed on the substrate; and a wire electrode disposed on the substrate, wherein the at least one of the sensing electrode and the wire electrode is arranged in a form of a mesh.

Abstract: Metal nanowires, such as silver nanowires coated on a substrate were fused together to form fused metal nanowire networks that have greatly improved conductivity while maintaining good transparency. Materials formed form the fused metal nanowire networks described herein can have a transparency to visible light of at least about 85% and a sheet resistance of no more than about 100 Ohms/square or a transparency to visible light of at least about 90% and a sheet resistance of no more than about 250 Ohms/square. The method of forming such a fused metal nanowire networks are disclosed that involves exposure of metal nanowires to various fusing agents on a short timescale. When formed into a film, materials comprising the metal nanowire network demonstrate low sheet resistance while maintaining desirably high levels of optical transparency, making them suitable for transparent electrode formation.

Abstract: A method of manufacturing a part-mounting package includes: forming a first through-hole in a first insulating sheet and forming a second through-hole whose opening area is larger than the first through-hole in a second insulating sheet; forming a penetration conductor covering an inner surface of the second through-hole and forming a conductor layer on a surface of at least the second insulating sheet; laminating the first insulating sheet and the second insulating sheet where center positions of the first through-hole and the second through-hole are matched to each other; causing linear laser division grooves to pass through a center of the first through-hole and the second through-hole; and dividing the sheet laminated body along the laser division grooves, and causing the side surface recess part and the end face through-hole conductor to appear.

Abstract: An electronic arrangement comprising: a carrier; at least one connecting area on the carrier; at least one electronic component, which is fixed at least on the connecting area by a contact material; a covering area, which surrounds the connecting area on the carrier; and at least one covered region covered by a covering material; wherein the covering area is highly reflective with a reflectivity of greater than 70%, exposed regions on the connecting area and on the contact material are covered with the covering material, and the covering material is colored by titanium dioxide particles in such a way that the titanium dioxide particles are provided in the covering material in a proportion between 25 percent and 70 percent by weight, such that the covering material is highly reflective with a reflectivity of greater than 70% to minimize optical contrast between the covering area and the covered region.

Abstract: A multilayer capacitor includes a capacitor body including a dielectric layer and a first internal electrode and a second internal electrode; a first via electrode exposed through first and second surfaces of the capacitor body, connected to the first internal electrode and spaced apart from the second internal electrode, a second via electrode exposed through the first and second surfaces of the capacitor body, and connected to the second internal electrode and spaced apart from the first internal electrode, a first and second external electrodes disposed on the first surface of the capacitor body to be spaced apart from each other, and connected to the first and the second via electrodes, respectively, and first and second covers disposed in sequence from a bottom in the second surface of the capacitor body, wherein the first and second cover are formed of different materials.

Abstract: In a heat insulating load jig 11 of the present invention, a solder material 14 having a melting point or a solidus temperature in a range between a thermal resistance temperature of a semiconductor chip 13 and a temperature 100° C. below the thermal resistance temperature is interposed between a circuit board 12 and the semiconductor chip 13; a heat insulating body 17 is placed on an upper side of the semiconductor chip 13 in this state; a metal weight 16 is disposed on the heat insulating body 17; and load is applied to the semiconductor chip 13 while the solder material 14 is melted and solidified.

Abstract: An electrical circuit including a circuit board on which a number of electrical and/or electronic components are mounted, and a busbar that has a supporting body and a first, second, and third connection. The supporting body is spaced apart from the circuit board and the connections are brought into electrical contact both with the supporting body and with the circuit board. The supporting body has a first cross section between the first and second connection and a second cross section between the second and third connection, wherein the first cross section is smaller than the second cross section. The invention further relates to a bus bar.

Abstract: A circuit board, and a lighting device and board housing module having the circuit board. The circuit board includes a support substrate having a first region and a second region bent from the first region, light emitting devices disposed on the first region, and a protective support portion protruding more than the light emitting devices from the support substrate of the first region.

Abstract: Provided are a semiconductor package and a manufacturing method thereof for securing a space for mounting a semiconductor device by etching a temporary metal plate to form a plurality of conductive posts.