Gas Phase Etching Of Substrate Patents (Class 216/58)
  • Patent number: 9082796
    Abstract: A processing device for processing stacked processed goods for the production of conducting, semiconducting, or insulating thin layers includes, in at least one embodiment, an evacuatable process chamber configured to receive a process gas. A tempering device keeps at least a partial region of a wall of the evacuatable process chamber at a predetermined first temperature during at least part of the processing. The first temperature is between a second temperature that is room temperature and a third temperature, generated in the evacuatable process chamber, that is above room temperature. A heated gas flow cycle flows through a gas guiding device in the evacuatable process chamber. The stacked processed goods are insertable through a lockable loading opening into the gas guiding device, and a gas inlet device feeds the process gas into the gas flow cycle. A process system may further include a cooling device and/or a channeling device.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: July 14, 2015
    Inventor: Volker Probst
  • Patent number: 9039909
    Abstract: There is provided a plasma etching method for forming a hole in a silicon oxide film formed on an etching stopper layer. The plasma etching method includes a main etching process for etching the silicon oxide film; and an etching process that is performed when at least a part of the etching stopper layer is exposed after the main etching process. The etching process includes a first etching process using a gaseous mixture of a C4F6 gas, an Ar gas and an O2 gas as the processing gas; and a second etching process using a gaseous mixture of a C4F8 gas, an Ar gas and an O2 gas or a gaseous mixture of a C3F8 gas, an Ar gas and an O2 gas as the processing gas. The first etching process and the second etching process are alternately performed plural times.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 26, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Nakagawa, Yuji Otsuka
  • Patent number: 9034199
    Abstract: A machined ceramic article having an initial surface defect density and an initial surface roughness is provided. The machined ceramic article is heated to a temperature range between about 1000° C. and about 1800° C. at a ramping rate of about 0.1° C. per minute to about 20° C. per minute. The machined ceramic article is heat-treated in air atmosphere. The machined ceramic article is heat treated at one or more temperatures within the temperature range for a duration of up to about 24 hours. The machined ceramic article is then cooled at the ramping rate, wherein after the heat treatment the machined ceramic article has a reduced surface defect density and a reduced surface roughness.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: May 19, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Ren-Guan Duan, Thorsten Lill, Jennifer Y. Sun, Benjamin Schwarz
  • Patent number: 9029264
    Abstract: Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 12, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Errol Antonio C. Sanchez, Yi-Chiau Huang
  • Patent number: 9023222
    Abstract: According to one embodiment, a pattern forming method includes forming a first guide layer on a processed film, phase-separating a first self-assembly material with the use of the first guide layer to form a first self-assembly pattern including a first polymer portion and a second polymer portion, selectively removing the first polymer portion, forming a second guide layer with the use of the second polymer portion, and phase-separating a second self-assembly material with the use of the second guide layer to form a second self-assembly pattern including a third polymer portion and a fourth polymer portion.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ayako Kawanishi, Shinichi Ito, Hirokazu Kato, Shimon Maeda, Hideki Kanai
  • Patent number: 9023225
    Abstract: A pattern forming method includes forming a pattern forming material film on a substrate as an etching target film, the pattern forming material film having an exposing section that has porosity upon exposure and a non-exposing section, patterning and exposing the pattern forming material film for the exposing section to have the porosity, selectively infiltrating a filling material into voids of the exposing section to reinforce the exposing section, and removing the non-exposing section of the pattern forming material film by dry etching to form a predetermined pattern.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 5, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Kenichi Oyama, Hidetami Yaegashi
  • Patent number: 9023218
    Abstract: Methods of fabricating the fusible link are directed to processing a multi-layer clad foil having a first layer suitable for forming a fusible link and a second layer suitable for forming one or more welding tabs. In some embodiments, the first layer is an aluminum layer and the second layer is a nickel layer. A two-step etching process or a single step etching process is performed on the clad foil to form an etched clad foil having multiple tabs made of the second layer and connected to the current collector conductor pads and battery cell conductor pads, and one or more connections made of the first layer that form aluminum conductors. The aluminum conductors are shaped and sized to form aluminum fusible conductors during either the etching process or a subsequent stamping process. A single fusible link or an array of fusible links can be formed.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: May 5, 2015
    Assignee: SinoElectric Powertrain Corporation
    Inventors: Peng Zhou, Paul Tsao
  • Publication number: 20150118625
    Abstract: Provided herein is a method, including a) transferring an initial pattern of an initial template to a substrate; b) performing block copolymer self-assembly over the substrate with a density multiplication factor k; c) creating a subsequent pattern in a subsequent template with the density multiplication factor k; and d) repeating steps a)-c) with the subsequent template as the initial template until a design specification for the subsequent pattern with respect to pattern density and pattern resolution is met.
    Type: Application
    Filed: January 2, 2015
    Publication date: April 30, 2015
    Inventors: XiaoMin Yang, Zhaoning Yu, Kim Yang Lee, Michael Feldbaum, Yautzong Hsu, Wei Hu, Shuaigang Xiao, Henry Yang, HongYing Wang, Rene Johannes Marinus van de Veerdonk, David Kuo
  • Patent number: 9017564
    Abstract: A plasma etching method performs plasma etching on a sample, which has laminated films containing a variable layer of a magnetic film, a barrier layer of an insulating material, and a fixed layer of a magnetic film, using a hard mask, which includes at least one of a Ta film and a TiN film. The plasma etching method includes a first step of etching the laminated films using N2 gas; and a second step of etching the laminated films after the first step using mixed gas of N2 gas and gas containing carbon elements.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 28, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Atsushi Yoshida, Naohiro Yamamoto, Makoto Suyama, Kentaro Yamada, Daisuke Fujita
  • Patent number: 9017571
    Abstract: A dry etching agent according to the present invention preferably contains: (A) 1,3,3,3-tetrafluoropropene; (B) at least one kind of additive gas selected from the group consisting of H2, O2, O3, CO, CO2, COCl2, COF2, CF3OF, NO2, F2, NF3, Cl2, Br2, I2, CH4, C2H2, C2H4, C2H6, C3H4, C3H6, C3H8, HF, HI, HBr, HCl, NO, NH3 and YFn (where Y represents Cl, Br or I; and n represents an integer satisfying 1?n?7); and (C) an inert gas. This dry etching agent has less effect on the global environment and can obtain a significant improvement in process window and address processing requirements such as low side etching ratio and high aspect ratio even without any special substrate excitation operation.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 28, 2015
    Assignee: Central Glass Company, Limited
    Inventors: Tomonori Umezaki, Yasuo Hibino, Isamu Mori, Satoru Okamoto, Akiou Kikuchi
  • Patent number: 9017561
    Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 28, 2015
    Assignee: NXP, B.V.
    Inventors: Gerhard Koops, Jozef Thomas Martinus van Beek
  • Patent number: 9011707
    Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Darwin Rusli
  • Patent number: 8999177
    Abstract: Out-of-plane microneedle manufacturing process comprising the simultaneous creation of a network of microneedles and the creation of a polygonal shaped hat (2) above each microneedle (1) under formation, said process comprising the following steps: providing bridges (3) between the hats (3), maintaining the bridges (3) during the remaining microneedle manufacturing steps, removing the bridges (3), together with the hats (2), when the microneedles (1) are formed.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: April 7, 2015
    Assignee: Debiotech S.A.
    Inventors: Astrid Cachemaille, Francois Cannehan
  • Patent number: 8999184
    Abstract: A method for forming via holes in an etch layer disposed below a patterned organic mask with a plurality of patterned via holes is provided. The patterned organic mask is treated by flowing a treatment gas comprising H2. A plasma is formed from the treatment gas. The patterned via holes are rounded to form patterned rounded via holes by exposing the patterned via holes to the plasma. The flow of the treatment gas is stopped. The plurality of patterned rounded via holes are transferred into the etch layer.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: April 7, 2015
    Assignee: Lam Research Corporation
    Inventors: Ming-Shu Kuo, Siyi Li, Yifeng Zhou, Ratndeep Srivastava, Tae Won Kim, Gowri Kamarthy
  • Patent number: 8992789
    Abstract: According to one embodiment, a method is disclosed for manufacturing a mold. The method can include forming a second major surface receded from a first major surface by irradiating a portion of the first major surface with a charged beam to etch a base material having the first major surface. The method can include forming a mask pattern on the first major surface and the second major surface. In addition, the method can include forming a first pattern on the first major surface and a second pattern on the second major surface by etching the base material through the mask pattern.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Suzuki, Tetsuro Nakasugi
  • Patent number: 8987143
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated hydrogen species. The activated hydrogen species can be used to etch/clean semiconductor oxide surfaces such as silicon oxide or germanium oxide.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: March 24, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ratsamee Limdulpaiboon, Chi-I Lang, Sandip Niyogi, J. Watanabe
  • Patent number: 8986556
    Abstract: A TAMR (Thermally Assisted Magnetic Recording) write head is formed with a narrow pole tip, a trailing edge magnetic shield and, optionally, a plasmon shield. The narrow pole tipped write head uses the energy of laser generated edge plasmons, formed in a plasmon generating layer, to locally heat a PMR magnetic recording medium slightly below its Curie temperature, Tc. When combined with the effects of the narrow tip, this local heating to a temperature below Tc is sufficient to create good transitions and narrow track widths in the magnetic medium. The write head is capable of writing effectively on state-of-the-art PMR recording media having Hk of 20 kOe or more.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: March 24, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Xuhui Jin, Yuchen Zhou, Kenichi Takano, Joe Smyth
  • Publication number: 20150075283
    Abstract: The present invention provides a capacitive acceleration sensor with a bending elastic beam and a preparation method. The sensor at least includes a first electrode structural layer, a middle structural layer and a second electrode structural layer; wherein the first electrode structural layer and the second electrode structural layer are provided with an electrode lead via-hole, respectively; the middle structural layer includes: a frame formed on a SOI silicon substrate with a double device layers, a seismic mass whose double sides are symmetrical and a bending elastic beam with one end connected to the frame and the other end connected to the seismic mass, wherein anti-overloading bumps and damping grooves are symmetrically provided on two sides of the seismic mass, and the bending elastic beams at different planes are staggered distributed and are not overlapped with each other in space.
    Type: Application
    Filed: December 4, 2012
    Publication date: March 19, 2015
    Inventors: Lufeng Che, Xiaofeng Zhou, Yuelin Wang
  • Patent number: 8980111
    Abstract: A method for patterning a substrate is described. The patterning method may include conformally depositing a material layer over a pattern according to a conformal deposition process, selectively depositing a second material layer on an exposed surface of the material layer according to a selected deposition process recipe; partially removing the material layer using a plasma etching process to expose a top surface of the pattern, open a portion of the material layer at a bottom region between adjacent features of the pattern, and retain a remaining portion of the material layer on sidewalls of the pattern; and removing the pattern using one or more etching processes to leave a final pattern comprising the remaining portion of the material layer and the second layer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Akiteru Ko, Kosuke Ogasawara
  • Patent number: 8974678
    Abstract: Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock copolymers, triblock copolymers, multiblock copolymers, or combinations thereof. Such methods can be useful for making devices that include, for example, sub-lithographic conductive lines.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Dan Millward
  • Patent number: 8975190
    Abstract: A plasma processing method includes a surface improving step of improving a surface of the photoresist film by performing plasma processing using a hydrogen-containing gas as a processing gas and an etching step of etching the SiON film by performing plasma processing using a processing gas including a gas containing a CHF-based gas and a chlorine-containing gas while using as a mask the photoresist film having the improved surface.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 10, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Ryoichi Yoshida
  • Patent number: 8975192
    Abstract: A method is provided for manufacturing a semiconductor device having a heat-resistant resin film with flip-chip connection structure using a solder bump or a gold bump and an epoxy resin compound laminated thereon, in which adhesiveness is improved particularly after exposure to high temperature and high humidity environments for a long period of time, thereby enhancing the reliability of the semiconductor device. The method, in accordance with the present invention, for manufacturing a semiconductor device having a heat-resistant resin film formed on a semiconductor element and an epoxy resin compound layer laminated thereon, comprises the steps of carrying out a plasma treatment on a surface of the heat-resistant resin film on which the epoxy resin compound layer is laminated using a nitrogen atom-containing gas containing at least one of nitrogen, ammonia, and hydrazine.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: March 10, 2015
    Assignee: Hitachi Chemical Dupont Microsystems Ltd.
    Inventors: Yasunori Kojima, Toshiaki Itabashi
  • Patent number: 8968585
    Abstract: Methods to fabricate reaction cartridges for biological sample preparation and analysis are disclosed. A cartridge may have a reaction chamber and openings to allow fluids to enter the chamber. The cartridge may also have handles to facilitate its use. Such cartridges may be used for polymerase chain reaction.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: March 3, 2015
    Assignee: California Institute of Technology
    Inventors: Imran R. Malik, Axel Scherer, Erika F. Garcia, Xiomara L. Madero
  • Patent number: 8969209
    Abstract: A method for removing oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A removing oxide process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: March 3, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Yen-Chu Chen, Teng-Chun Tsai, Chien-Chung Huang, Keng-Jen Liu
  • Patent number: 8961799
    Abstract: A method of forming a nano-structured substrate is provided, the method comprising including forming non-integral nano-pillars on a substrate surface and directionally etching the substrate surface using the non-integral nano-pillars as a mask to form integral nano-structures in the substrate.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: February 24, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter Mardilovich, Anthony M. Fuller, Qingqiao Wei
  • Patent number: 8956546
    Abstract: A substrate processing method for removing an Si-based film on a surface of a substrate accommodated in a processing chamber includes a first step in which the Si-based film on the surface of the substrate is transformed into a reaction product by a gas containing a halogen element and an alkaline gas in the processing chamber and a second step in which the reaction product is vaporized in the processing chamber which is depressurized to a pressure lower than a pressure during the first step. The first step and the second step are repeated two or more times.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: February 17, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Hajime Ugajin, Shigeki Tozawa
  • Patent number: 8956513
    Abstract: There is provided a substrate processing method, in which a throughput can be improved even in case the time for recovery processing for restoring the state of a processing chamber is longer than the time for predetermined processing to be performed in the processing chamber. Substrates are alternately transferred to two processing chambers C, D, and the same film forming processing is performed on the substrates in the processing chambers C, D in parallel with each other. When the number of substrates processed in the processing chamber C has reached a predetermined number (11 substrates), dummy sputtering processing in the film forming chamber C is started and also 23rd-25th substrates of the first lot are transferred to the film forming chamber D to thereby perform film forming processing until the dummy sputtering processing is finished.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: February 17, 2015
    Assignee: Ulvac, Inc.
    Inventors: Shinya Nakamura, Yoshinori Fujii, Hideto Nagashima
  • Patent number: 8951428
    Abstract: This invention presents a method for the fabrication of periodic nanostructures on polymeric surfaces by means of plasma processing, which method comprises the following steps: (i) provision of a homogeneous organic polymer (such as PMMA, or PET, or PEEK, or PS, or PE, or COC) or inorganic polymer (such as PDMS or ORMOCER); (ii) exposure of the polymer to an etching plasma such as oxygen (O2) or sulphur hexafluoride (SF6) or a mixture of oxygen (O2) and sulphur hexafluoride (SF6), or mixtures of etching gases with inert gases such as any Noble gas (Ar, He, Ne, Xe).
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: February 10, 2015
    Inventors: Evangelos Gogolides, Angeliki Tserepi, Vassilios Constantoudis, Nikolaos Vourdas, Georgios Boulousis, Maria-Elena Vlachopoulou, Aikaterini Tsougeni, Dimitrios Kontziampasis
  • Patent number: 8951424
    Abstract: A substrate for an electrowetting display device including a pixel electrode, a partition wall pattern and a water-repellent pattern. The pixel electrode is formed on a base substrate. The partition wall pattern is disposed along an edge of the pixel electrode to expose the pixel electrode. The water-repellent pattern is disposed at a space formed by the pixel electrode and the partition wall pattern to be extended along a lower portion of side surfaces of the partition wall pattern from an area on which the pixel electrode is formed. The water-repellent pattern exposes an upper portion of the side surfaces and an upper surface of the partition wall pattern. Thus, a manufacturing reliability of a substrate for an electrowetting display device is improved to prevent a display quality from being reduced.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 10, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Seung Bo Shim, Jin-Ho Ju, Dae Ho Kim, Sang-Il Kim, Sung-Kyun Park, Jae-Jin Lyu
  • Patent number: 8945406
    Abstract: A method for manufacturing a symbol on an exterior of an electronic device is provided. The method includes preparing a support layer, preparing a nanograting layer on the support layer, the nanograting layer including a first nanograting area corresponding to a preset symbol and a second nanograting area corresponding to an area other than the preset symbol, wherein each of the first nanograting area and the second nanograting area includes three-dimensional (3D) nanostructures and a pitch between the 3D nanostructures arranged in the first nanograting area is different from a pitch between the 3D nanostructures arranged in the second nanograting area.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-eun Chung, Il-yong Jung
  • Publication number: 20150027982
    Abstract: A method of forming an imaging blanket for a printing apparatus comprises preparing a support structure (e.g., mold) for receipt of a polymer blanket compound, introducing the polymer blanket compound in liquid state over the support structure, curing the polymer blanket compound to produce an imaging blanket, releasing the imaging blanket from the support structure, and etching a surface of the imaging blanket to form a texture pattern therein, the surface forming an imaging surface of said imaging blanket. An imaging surface providing desirable dampening fluid retention is provided. Wet etch, dry etch or a combination of both may be used. The polymer may be a silicone compound, may include 3 percent by weight granular material.
    Type: Application
    Filed: July 29, 2013
    Publication date: January 29, 2015
    Applicants: Xerox Corporation, Palo Alto Research Center Incorporated
    Inventors: Timothy D. Stowe, Sourobh Raychaudhuri, Carolyn P. Moorlag, Michael Y. Young
  • Publication number: 20150011088
    Abstract: Methods are disclosed for depositing material onto and/or etching material from a substrate in a surface processing tool having a processing chamber, a controller and one or more devices for adjusting the process parameters within the chamber. The method comprises: the controller instructing the one or more devices according to a series of control steps, each control step specifying a defined set of process parameters that the one or more devices are instructed to implement, wherein at least one of the control steps comprises the controller instructing the one or more devices to implement a defined set of constant process parameters for the duration of the step, including at least a chamber pressure and gas flow rate through the chamber, which duration is less than the corresponding gas residence time (Tgr) of the processing chamber for the step.
    Type: Application
    Filed: February 27, 2013
    Publication date: January 8, 2015
    Inventors: Mark Edward McNie, Michael Joseph Cooke, Leslie Michael Lea
  • Patent number: 8926849
    Abstract: A diffraction-type 3D display element is arranged on an image output face of a 3D display device and comprises a first diffraction area and a second diffraction area. The first diffraction area has a plurality of first stepped gratings spaced apart from each other. The second diffraction area has a plurality of second stepped gratings spaced apart from each other. The second diffraction area is adjacent to the first diffraction area and is arranged symmetrically to the first diffraction area with a central line being the symmetric axis. The diffraction-type 3D display element of the invention diffracts the images output by the 3D display device and projects the diffracted images to two different viewing areas to provide 3D images for users.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 6, 2015
    Assignee: National Yunlin University of Science and Technology
    Inventors: Chien-Yue Chen, Wen-Chen Hung, Yao-Ru Chang
  • Patent number: 8926848
    Abstract: Provided are a method of forming a through hole, which can inhibit misalignment between central axes of holes in both surfaces of a substrate, which is free from metal contamination, and which inhibits notching so as to improve the dimensional accuracy, the method including: preparing a silicon substrate; preparing a supporting substrate for supporting the silicon substrate; fixing the silicon substrate and the supporting substrate to form a composite substrate; and carrying out dry etching to the composite substrate from a silicon substrate side of the composite substrate toward a supporting substrate side of the composite substrate to form a through hole in the silicon substrate, in which the supporting substrate in the preparing a supporting substrate has a hole formed at a region corresponding to a region of the through hole to be formed in the silicon substrate, on a surface of the supporting substrate facing the silicon substrate.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: January 6, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoichi Ikarashi
  • Patent number: 8920666
    Abstract: Disclosed herein is a dry etching method for a work layer formed over a substrate, including the steps of forming a hard mask layer over the work layer formed over the substrate, forming a resist pattern over the hard mask layer, transferring the resist pattern to the hard mask layer by first dry etching conducted using the resist pattern, and patterning the work layer by second dry etching conducted using a hard mask pattern obtained upon the transfer to the hard mask layer, wherein after the hard mask layer is patterned by the first dry etching, the patterning of the work layer by the second dry etching is conducted through changing the concentration of an auxiliary ingredient of a dry etching gas, without changing a main ingredient of the dry etching gas, in an etching apparatus in which the first dry etching has been conducted.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: December 30, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shinichi Igarashi, Yukio Inazuki, Hideo Kaneko, Hiroki Yoshikawa, Yoshinori Kinase
  • Patent number: 8921234
    Abstract: Methods of etching exposed titanium nitride with respect to other materials on patterned heterogeneous structures are described, and may include a remote plasma etch formed from a fluorine-containing precursor. Precursor combinations including plasma effluents from the remote plasma are flowed into a substrate processing region to etch the patterned structures with high titanium nitride selectivity under a variety of operating conditions. The methods may be used to remove titanium nitride at faster rates than a variety of metal, nitride, and oxide compounds.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jie Liu, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Seung Park, Zhijun Chen, Ching-Mei Hsu
  • Patent number: 8920662
    Abstract: A nozzle plate manufacturing method that offers excellent protection against discharge liquid and that enables a nozzle plate having high nozzle-hole accuracy to be manufactured with good yield. The invention also provides a nozzle plate, a droplet discharge head manufacturing method, and a droplet discharge head.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 30, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Junichi Takeuchi
  • Patent number: 8921232
    Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 30, 2014
    Inventors: Hironori Araki, Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura
  • Patent number: 8916477
    Abstract: Provided are methods and systems for removing polysilicon on a wafer. A wafer can include a polysilicon layer and an exposed nitride and/or oxide structure. An etchant with a hydrogen-based species, such as hydrogen gas, and a fluorine-based species, such as nitrogen trifluoride, can be introduced. The hydrogen-based species and the fluorine-based species can be activated with a remote plasma source. The layer of polysilicon on the wafer can be removed at a selectivity over the exposed nitride and/or oxide structure that is greater than about 500:1.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: December 23, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Bayu Thedjoisworo, Jack Kuo, David Cheung, Joon Park
  • Publication number: 20140360978
    Abstract: Provided is a method of manufacturing a liquid ejection head including: a substrate having energy generating elements disposed thereon; and an ejection orifice forming member having ejection orifices, the substrate and the ejection orifice forming member forming a flow path therebetween, the method including: forming, on the substrate, a mold having a recessed portion at a position corresponding to a region in which each of the ejection orifices is formed and in a vicinity of the position; forming a coating layer by chemical vapor deposition so as to cover the mold; and forming the ejection orifices through the coating layer to obtain the ejection orifice forming member.
    Type: Application
    Filed: May 27, 2014
    Publication date: December 11, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Masaya Uyama
  • Publication number: 20140360979
    Abstract: A dry non-plasma treatment system and method for removing oxide material is described. The treatment system is configured to provide chemical treatment of one or more substrates, wherein each substrate is exposed to a gaseous chemistry under controlled conditions including surface temperature and gas pressure. Furthermore, the treatment system is configured to provide thermal treatment of each substrate, wherein each substrate is thermally treated to remove the chemically treated surfaces on each substrate.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Martin Kent, Eric J. Strang
  • Patent number: 8906248
    Abstract: A method etching features through a stack of a silicon nitride layer over a silicon layer over a silicon oxide layer in a plasma processing chamber is provided. The silicon nitride layer is etched in the plasma processing chamber, comprising; flowing a silicon nitride etch gas; forming the silicon nitride etch gas into a plasma to etch the silicon nitride layer, and stopping the flow of the silicon nitride etch gas. The silicon layer is, comprising flowing a silicon etch gas, wherein the silicon etch gas comprises SF6 or SiF4, forming the silicon etch gas into a, and stopping the flow of the silicon etch gas. The silicon oxide layer is etched in the plasma processing chamber, comprising flowing a silicon oxide etch gas, forming the silicon oxide etch gas into a plasma, and stopping the flow of the silicon oxide etch gas.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: December 9, 2014
    Assignee: Lam Research Corporation
    Inventors: Siyi Li, Robert C. Hefty, Mark Todhunter Robson, James R. Bowers, Audrey Charles
  • Patent number: 8900471
    Abstract: Methods and apparatus for in-situ plasma cleaning of a deposition chamber are provided. In one embodiment a method for plasma cleaning a deposition chamber without breaking vacuum is provided. The method comprises positioning a substrate on a susceptor disposed in the chamber and circumscribed by an electrically floating deposition ring, depositing a metal film on the substrate and the deposition ring in the chamber, grounding the metal film deposited on the deposition ring without breaking vacuum, and removing contaminants from the chamber with a plasma formed in the chamber without resputtering the metal film on the grounded deposition ring and without breaking vacuum.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: December 2, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Richard J. Green, Cheng-hsiung Tsai, Shambhu N. Roy, Puneet Bajaj, David H. Loo
  • Patent number: 8900467
    Abstract: A method for making a chemical contrast pattern uses directed self-assembly of block copolymers (BCPs) and sequential infiltration synthesis (SIS) of an inorganic material. For an example with poly(styrene-block-methyl methacrylate) (PS-b-PMMA) as the BCP and alumina as the inorganic material, the PS and PMMA self-assemble on a suitable substrate. The PMMA is removed and the PS is oxidized. A surface modification polymer (SMP) is deposited on the oxidized PS and the exposed substrate and the SMP not bound to the substrate is removed. The structure is placed in an atomic layer deposition chamber. Alumina precursors reactive with the oxidized PS are introduced and infuse by SIS into the oxidized PS, thereby forming on the substrate a chemical contrast pattern of SMP and alumina. The resulting chemical contrast pattern can be used for lithographic masks, for example to etch the underlying substrate to make an imprint template.
    Type: Grant
    Filed: May 25, 2013
    Date of Patent: December 2, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Yves-Andre Chapuis, Ricardo Ruiz, Lei Wan
  • Publication number: 20140349469
    Abstract: This disclosure provides systems, methods and apparatus for processing multiple substrates in a processing tool. An apparatus for processing substrates can include a process chamber, a common reactant source, and a common exhaust pump. The process chamber can be configured to process multiple substrates. The process chamber can include a plurality of stacked individual subchambers. Each subchamber can be configured to process one substrate. The common reactant source can be configured to provide reactant to each of the subchambers in parallel. The common exhaust pump can be connected to each of the subchambers.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Teruo Sasagawa, Sandeep K. Giri, Ana R. Londergan, Shih-chou Chiang
  • Publication number: 20140349488
    Abstract: Disclosed is an etching gas provided containing CHF2COF. The etching gas may contain, as an additive, at least one kind of gas selected from O2, O3, CO, CO2, F2, NF3, Cl2, Br2, I2, XFn (In this formula, X represents Cl, I or Br. n represents an integer satisfying 1?n?7.), CH4, CH3F, CH2F2, CHF3, N2, He, Ar, Ne, Kr and the like, from CH4, C2H2, C2H4, C2H6, C3H4, C3H6, C3H8, HI, HBr, HCl, CO, NO, NH3, H2 and the like, or from CH4, CH3F, CH2F2 and CHF3. This etching gas is not only excellent in etching performances such as the selection ratio to a resist and the patterning profile but also easily available and does not substantially by-produce CF4 that places a burden on the environment.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Inventors: Naoto TAKADA, Isamu MORI
  • Patent number: 8895452
    Abstract: A semiconductor substrate support for use in a plasma processing apparatus comprises a chuck body having a plenum and three radially extending bores extending between the plenum and an outer periphery of the chuck body, wherein the chuck body is sized to support a semiconductor substrate having a diameter of at least 450 mm. The semiconductor substrate support further comprises three tubular support arms which include a first section extending radially outward from the outer periphery of the chuck body, and a second section extending vertically from the first section. The tubular support arms provide a passage therethrough which communicates with a respective bore in the chuck body. The second section of each tubular support arm is configured to engage with a respective actuation mechanism outside the chamber operable to effect vertical translation and planarization of the chuck body in the interior of a plasma processing chamber.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: November 25, 2014
    Assignee: Lam Research Corporation
    Inventors: Jerrel Kent Antolik, Yen-kun Victor Wang, John Holland
  • Patent number: 8894870
    Abstract: A system and method for etching a material, including a compound having a formulation of XYZ, wherein X and Y are one or more metals and Z is selected from one or more Group 13-16 elements, such as carbon, nitrogen, boron, silicon, sulfur, selenium, and tellurium, are disclosed. The method includes a first etch process to form one or more first volatile compounds and a metal-depleted layer and a second etch process to remove at least a portion of the metal-depleted layer.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: November 25, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Jereld Lee Winkler, Eric James Shero, Fred Alokozai
  • Patent number: 8894868
    Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: November 25, 2014
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Andy Hooper, Daragh Finn, Tim Webb, Lynn Sheehan, Kenneth Pettigrew, Yu Chong Tai
  • Patent number: 8895449
    Abstract: A method of selectively removing fluorocarbon layers from overlying low-k dielectric material is described. These protective plasma treatments (PPT) are delicate alternatives to traditional post-etch treatments (PET). The method includes sequential exposure to (1) a local plasma formed from a silicon-fluorine precursor followed by (2) an exposure to plasma effluents formed in a remote plasma from a fluorine-containing precursor. The remote plasma etch (2) has been found to be highly selective of the residual material following the local plasma silicon-fluorine exposure. The sequential process (1)-(2) avoids exposing the low-k dielectric material to oxygen which would undesirably increase its dielectric constant.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Lina Zhu, Sean S. Kang, Srinivas D. Nemani, Chia-Ling Kao