Gas Phase Etching Of Substrate Patents (Class 216/58)
  • Publication number: 20140342156
    Abstract: A product formed from a first material including a geopolymer resin material, a geopolymer resin, or a combination thereof by contacting the first material with a fluid and removing at least some of the fluid to yield a product. The first material may be formed by heating and/or aging an initial geopolymer resin material to yield the first material before contacting the first material with the fluid. In some cases, contacting the first material with the fluid breaks up or disintegrates the first material (e.g., in response to contact with the fluid and in the absence of external mechanical stress), thereby forming particles having an external dimension in a range between 1 nm and 2 cm.
    Type: Application
    Filed: September 21, 2012
    Publication date: November 20, 2014
    Inventors: Dong-Kyun Seo, Dinesh Medpelli, Danielle Ladd, Milad Mesgar
  • Patent number: 8889559
    Abstract: A method of forming a pattern on a substrate includes forming spaced first material-comprising pillars projecting elevationally outward of first openings formed in second material. Sidewall spacers are formed over sidewalls of the first material-comprising pillars. The sidewall spacers form interstitial spaces laterally outward of the first material-comprising pillars. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall spacers that are over sidewalls of four of the first material-comprising pillars.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: November 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Patent number: 8889558
    Abstract: A method of forming a pattern on a substrate includes forming openings in material of a substrate. The openings are widened to join with immediately adjacent of the openings to form spaced pillars comprising the material after the widening. Other embodiments are disclosed.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: November 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Ranjan Khurana, Anton J. deVillers, Kevin J. Torek, Shane J. Trapp, Scott L. Light, James M. Buntin
  • Patent number: 8877079
    Abstract: The present invention relates to a method of manufacturing a semiconductor device wherein etching is performed on films on a wafer using a plasma treatment apparatus. In the manufacturing method according to the present invention, a change in the difference between the emission intensities of a first wavelength component and a second wavelength component in plasma is monitored during etching. If the amount of change in the difference per unit time exceeds a predetermined threshold a given number of times in a row, then the flow rate of oxygen introduced to the plasma treatment apparatus is increased or, if the amount of change exceeding the predetermined threshold has not been seen, then the oxygen flow rate is set back to the original value thereof. This series of actions is repeated all the time during a set period of time.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: November 4, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Yasuhiko Ueda
  • Patent number: 8877001
    Abstract: Embodiments of gate valves and methods of using same are provided herein. In some embodiments, a gate valve for use in a process chamber may include a body having an opening disposed therethrough from a first surface to an opposing second surface of the body; a pocket extending into the body from a sidewall of the opening; a gate movably disposed within the pocket between a closed position that seals the opening and an open position that reveals the opening and disposes the gate completely within the pocket; and a shutter configured to selectively seal the pocket when the gate is disposed in the open position. In some embodiments, one or more heaters may be coupled to at least one of the body or the shutter.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: November 4, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Shin Kitamura, Mitsutoshi Fukada
  • Patent number: 8871102
    Abstract: A method for fabricating a structure in magnetic recording head is described. First and second hard mask layers are provided on the layer(s) for the structure. A BARC layer and photoresist mask having a pattern are provided on the second hard mask layer. The pattern includes a line corresponding to the structure. The pattern is transferred to the BARC layer and the second hard mask layer in a single etch using an etch chemistry. At least the second hard mask layer is trimmed using substantially the same first etch chemistry. A mask including a hard mask line corresponding to the line and less than thirty nanometers wide is thus formed. The pattern of the second hard mask is transferred to the first hard mask layer. The pattern of the first hard mask layer is transferred to the layer(s) such that the structure has substantially the width.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: October 28, 2014
    Assignee: Western Digital (Fremont), LLC
    Inventor: Wei Gao
  • Patent number: 8865597
    Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: John M. Cotte, Nils Hoivik, Christopher V. Jahnes, Robert L. Wisnieff
  • Patent number: 8865011
    Abstract: The invention provides a method for optimizing the spectroscopy performance of a spectroscopy scintillator by surrounding the scintillator by a reflector material, performing a scan measuring resolution and light output at three or more axial locations on the crystal, where at least one location is close to the PMT or below the crystal (near the PMT) at least one location is at the end away from the PMT of the scintillator), and adjusting the surface finish of the crystal and/or the reflector to obtain equal light output and optimal resolution over the length and different azimuth of the crystal.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: October 21, 2014
    Assignee: Schlumberger Technology Corporation
    Inventors: Olivier G. Philip, Markus Berheide
  • Patent number: 8858811
    Abstract: A method for manufacturing a device comprising an elastic member on a substrate includes steps of: forming a sacrificial layer by forming a plurality of sacrificial sub-layers on the substrate; forming a plate member in or on the sacrificial layers connected to the substrate and substantially parallel to a top surface of the substrate; and removing the sacrificial sub-layers after forming the plate member by removing the sacrificial sub-layers in an order different from the reverse order of forming the sacrificial sub-layers.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: October 14, 2014
    Inventors: Yoshihiro Maeda, Fusao Ishii, Kazuhiro Watanabe, Hirotoshi Ichikawa
  • Patent number: 8858809
    Abstract: A manufacturing method of a magnetic recording medium includes steps of forming a magnetic recording layer, a first mask layer, a second mask layer containing silicon as primary component, a strip layer, a third mask layer, and a resist layer, a step of patterning the resist layer to provide a pattern, steps of transferring the pattern to the third mask layer, to the strip layer, and to the second mask layer, a step of removing the strip layer by wet etching and of stripping the third mask layer and the resist layer above the magnetic recording layer, steps of transferring the pattern to the first mask layer and to the magnetic recording layer, and a step of stripping the first mask layer remaining on the magnetic recording layer.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Watanabe, Kaori Kimura, Kazutaka Takizawa, Takeshi Iwasaki, Tsuyoshi Onitsuka, Akihiko Takeo
  • Publication number: 20140290566
    Abstract: Disclosed is a process of surface treatment of a substrate. The method of treating a surface of a substrate comprises preparing the substrate, and performing an etching process with respect to a surface of the substrate. The etching process comprises a step of introducing etching gas to the surface of the substrate, and the etching gas comprises a halogen compound and a silane compound.
    Type: Application
    Filed: August 21, 2012
    Publication date: October 2, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventor: Heung Teak Bae
  • Patent number: 8846537
    Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8845909
    Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 30, 2014
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Tzu-Shih Shen
  • Patent number: 8840258
    Abstract: The present invention provides such a formation method that an antireflection structure having excellent antireflection functions can be formed in a large area and at small cost. Further, the present invention also provides an antireflection structure formed by that method. In the formation method, a base layer and particles placed thereon are subjected to an etching process. The particles on the base layer serve as an etching mask in the process, and hence they are more durable against etching than the base layer. The etching rate ratio of the base layer to the particles is more than 1 but not more than 5. The etching process is stopped before the particles disappear. It is also possible to produce an antireflection structure by nanoimprinting method employing a stamper. The stamper is formed by use of a master plate produced according to the above formation method.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Nakanishi, Akira Fujimoto, Koji Asakawa, Takeshi Okino, Shinobu Sugimura
  • Patent number: 8828245
    Abstract: A fabricating method of a flexible circuit board includes the following steps. The metal carrier foil with metal oxide layer on its surfaces is provided first. The metal oxide layer is formed from the spontaneous oxidization of the metal carrier foil in ambient air and provides passive protection in a sulfuric acid solution or an acidic copper sulphate solution. A conductive seed layer is electroplated onto the metal oxide layer. A flexible insulating layer is formed onto the conductive seed layer by performing a polyimide casting process. The metal carrier foil is then peeled off from the conductive seed layer, which is supported by the insulating layer. A patterned circuit is formed on the insulating layer by performing photoresist coating, developing and etching.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: September 9, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Chung Chen, Yi-Ling Lo, Hung-Kun Lee, Tzu-Ping Cheng
  • Patent number: 8828254
    Abstract: A plasma processing method and a plasma processing apparatus in which a stable process region can be ensured in a wide range, from low microwave power to high microwave power. The plasma processing method includes making production of plasma easy in a region in which production of plasma by continuous discharge is difficult, and plasma-processing an object to be processed, with the generated plasma, wherein the plasma is produced by pulsed discharge in which ON and OFF are repeated, radio-frequency power for producing the pulsed discharge, during an ON period, is a power to facilitate production of plasma by continuous discharge, and a duty ratio of the pulsed discharge is controlled so that an average power of the radio-frequency power per cycle is power in the region in which production of plasma by continuous discharge is difficult.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 9, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yoshiharu Inoue, Tetsuo Ono, Michikazu Morimoto, Masaki Fujii, Masakazu Miyaji
  • Patent number: 8828252
    Abstract: A silsesquioxane resin is applied on top of the patterned photo-resist and cured to produce a cured silsesquioxane resin on top of the pattern surface. Subsequently, an aqueous base stripper or a reactive ion etch recipe containing CF4 is used to “etch back” the silicon resin to the top of the photoresist material, exposing the entire top surface of the photoresist. Then, a second reactive ion etch recipe containing O2 to etch away the photoresist. The result is a silicon resin film with via holes with the size and shape of the post that were patterned into the photoresist. Optionally, the new pattern can be transferred into the underlying layer(s).
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: September 9, 2014
    Assignee: Dow Corning Corporation
    Inventors: Michael L. Bradford, Eric Scott Moyer, Kasumi Takeuchi, Sheng Wang, Craig Rollin Yeakle
  • Patent number: 8828881
    Abstract: The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: September 9, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Lingkkuan Meng, Huaxiang Yin
  • Patent number: 8822345
    Abstract: A plasma processing apparatus includes a gas distribution member which supplies a process gas and radio frequency (RF) power to a showerhead electrode. The gas distribution member can include multiple gas passages which supply the same process gas or different process gases at the same or different flow rates to one or more plenums at the backside of the showerhead electrode. The gas distribution member provides a desired process gas distribution to be achieved across a semiconductor substrate processed in a gap between the showerhead electrode and a bottom electrode on which the substrate is supported.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: September 2, 2014
    Assignee: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Eric Lenz
  • Patent number: 8821736
    Abstract: A method for making a perpendicular magnetic recording disk includes forming a template layer below a Ru or Ru alloy underlayer, with a granular Co alloy recording layer formed on the underlayer. The template layer is formed by depositing a solution of a polymer with a functional end group and nanoparticles, allowing the solution to dry, annealing the polymer layer to thereby form a polymer layer with embedded spaced-apart nanoparticles, and then etching the polymer layer to a depth sufficient to partially expose the nanoparticles so they protrude above the surface of the polymer layer. The protruding nanoparticles serve as controlled nucleation sites for the Ru or Ru alloy atoms. The nanoparticle-to-nanoparticle distances can be controlled during the formation of the template layer. This enables control of the Co alloy grain diameter distribution as well as grain-to-grain distance distribution.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 2, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Bruce Alvin Gurney, Dan Saylor Kercher, Alan C Lam, Ricardo Ruiz, Manfred Ernst Schabes, Kentaro Takano, Shi-Ling Chang Wang, Qing Zhu
  • Patent number: 8821743
    Abstract: The disclosure relates to a method for making a grating. The method includes the following steps. First, a substrate is provided. Second, a patterned mask layer is formed on a surface of the substrate. Third, the substrate with the patterned mask layer is placed in a microwave plasma system. Fourth, a plurality of etching gases are guided into the microwave plasma system simultaneously to etch the substrate through three stages. The etching gas includes carbon tetrafluoride (CF4), argon (Ar2), and sulfur hexafluoride (SF6). Finally, the patterned mask layer is removed.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: September 2, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Li-Hui Zhang, Mo Chen, Shou-Shan Fan
  • Publication number: 20140243224
    Abstract: Provided is an array including a solid support having a surface, the surface having a plurality of wells, the wells containing a gel material, the wells being separated from each other by interstitial regions on the surface, the interstitial regions segregating the gel material in each of the wells from the gel material in other wells of the plurality; and a library of target nucleic acids in the gel material, wherein the gel material in each of the wells comprises a single species of the target nucleic acids of the library. Methods for making and using the array are also provided.
    Type: Application
    Filed: March 6, 2013
    Publication date: August 28, 2014
    Applicant: ILLUMINA, INC.
    Inventors: Steven M. Barnard, M. Shane Bowen, Maria Candelaria Rogert Bacigalupo, Wayne N. George, Andrew A. Brown, James Tsay
  • Patent number: 8815107
    Abstract: An aspect of the present invention relates to a method of etching a surface layer portion of a silicon wafer comprising: positioning the silicon wafer within a sealed vessel containing a mixed acid A of hydrofluoric acid and sulfuric acid so that the silicon wafer is not in contact with mixed acid A; introducing a solution B in the form of nitric acid containing nitrogen oxides into the sealed vessel and causing solution B to mix with mixed acid A; and vapor phase decomposing the surface layer portion of the silicon wafer within the sealed vessel within which mixed acid A and solution B have been mixed.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: August 26, 2014
    Assignee: Sumco Corporation
    Inventors: Jiahong Wu, Shabani B. Mohammad
  • Patent number: 8815106
    Abstract: A method of supplying an etching gas includes: supplying a first etching gas used in an etching process into a processing container; and supplying a second etching gas used in the etching process into the processing container, in which, when the first etching gas and the second etching gas are switched therebetween, only a small amount of a gas, which is needed as an etching gas before the switching and is not needed as an etching gas after the switching, is continuously supplied into the processing container.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: August 26, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Masahiro Ogasawara, Yoshiyuki Kato, Hideki Mizuno, Yoshinobu Hayakawa
  • Publication number: 20140235012
    Abstract: Embodiments disclosed herein provide devices having a nozzle die with one or more nozzles, each of which has one or more integrated skimmers. The use of an integrated nozzle/skimmer structure allows for higher-resolution printing in OVJP-type deposition techniques without requiring the use of a shadow mask by allowing for a relatively narrow organic material beam that can be placed at relatively high distances away from the substrate.
    Type: Application
    Filed: May 17, 2013
    Publication date: August 21, 2014
    Inventors: Gregory McGraw, Paul E. Burrows, Siddharth Harikrishna Mohan
  • Publication number: 20140234579
    Abstract: The present invention relates to a novel composite preventing ice adhesion. A plurality of micro-roughened surfaces or organometallized micro-roughened surfaces wetted with a hydrophobic, low freezing-point liquid results in a durable, renewable anti-icing composite. The preparation method for novel icing and rain protecting composite is disclosed.
    Type: Application
    Filed: February 15, 2013
    Publication date: August 21, 2014
    Inventors: LIANG WANG, Viktoria Ren Wang
  • Patent number: 8808563
    Abstract: Methods of etching exposed silicon on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a hydrogen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon while very slowly removing other exposed materials. The silicon selectivity results, in part, from a preponderance of hydrogen-containing precursor in the remote plasma which hydrogen terminates surfaces on the patterned heterogeneous structures. A much lower flow of the fluorine-containing precursor progressively substitutes fluorine for hydrogen on the hydrogen-terminated silicon thereby selectively removing silicon from exposed regions of silicon.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Anchuan Wang, Jingchun Zhang, Nitin K. Ingle, Young S. Lee
  • Patent number: 8808558
    Abstract: The invention provides a system and method for alignment of nanoparticles on a substrate. The system includes: a substrate; a plurality of polypeptide templates formed on the substrate; and a plurality of nanoparticles formed on the polypeptide templates. The method includes: providing a substrate; forming a plurality of polypeptide templates on the substrate; and forming a plurality of nanoparticles on the polypeptide templates.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: August 19, 2014
    Assignee: National Sun Yat-Sen University
    Inventor: Shu-Chen Hsieh
  • Patent number: 8808562
    Abstract: A method of etching an aluminum-containing layer on a substrate is described. The method includes forming plasma from a process composition containing a halogen element, and exposing the substrate to the plasma to etch the aluminum-containing layer. The method may additionally include exposing the substrate to an oxygen-containing environment to oxidize a surface of the aluminum-containing layer and control an etch rate of the aluminum-containing layer. The method may further include forming first plasma from a process composition containing HBr and an additive gas having the chemical formula CxHyRz (wherein R is a halogen element, x and y are equal to unity or greater, and z is equal to zero or greater), forming second plasma from a process composition containing HBr, and exposing the substrate to the first plasma and the second plasma to etch the aluminum-containing layer.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: August 19, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Yusuke Ohsawa, Hiroto Ohtake, Eiji Suzuki, Kaushik Arun Kumar, Andrew W. Metz
  • Patent number: 8801950
    Abstract: A substrate processing chamber includes a lift actuator that moves a pedestal between a substrate loading position and a substrate processing position. An adjustable seal defines an expandable sealed volume between a bottom surface of the pedestal and a bottom surface of the substrate processing chamber and is moveable between the substrate loading position and the substrate processing position. When the pedestal is in the substrate processing position, the pedestal and the adjustable seal define a first inert volume and a first process volume. When the pedestal is in the substrate loading position, the pedestal and the adjustable seal define a second inert volume and a second process volume. The second inert volume is less than the first inert volume and the second process volume is greater than the first process volume.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: August 12, 2014
    Assignee: Novellus Systems, Inc.
    Inventor: James F. Lee
  • Patent number: 8790522
    Abstract: A method includes forming a chemical guide layer above a process layer. A template having a plurality of elements is formed above the process layer. The chemical guide layer is disposed on at least portions of the process layer disposed between adjacent elements of the template. A directed self-assembly layer is formed over the chemical guide layer. The directed self-assembly layer has alternating etchable components and etch-resistant components. The etchable components of the directed self-assembly layer are removed. The process layer is patterned using the template and the etch-resistant components of the directed self-assembly layer as an etch mask.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: July 29, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Gerard M. Schmid, Richad A. Farrell, Ji Xu, Jason R. Cantone, Moshe E. Preil
  • Patent number: 8790863
    Abstract: In a method for imaging a solid state substrate, a vapor is condensed to an amorphous solid water condensate layer on a surface of a solid state substrate. Then an image of at least a portion of the substrate surface is produced by scanning an electron beam along the substrate surface through the water condensate layer. The water condensate layer integrity is maintained during electron beam scanning to prevent electron-beam contamination from reaching the substrate during electron beam scanning. Then one or more regions of the layer can be locally removed by directing an electron beam at the regions. A material layer can be deposited on top of the water condensate layer and any substrate surface exposed at the one or more regions, and the water condensate layer and regions of the material layer on top of the layer can be removed, leaving a patterned material layer on the substrate.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 29, 2014
    Assignee: President and Fellows of Harvard College
    Inventors: Daniel Branton, Anpan Han, Jene A. Golovchenko
  • Patent number: 8790529
    Abstract: A gas supply system for supplying a gas into a processing chamber for processing a substrate to be processed includes: a processing gas supply unit; a processing gas supply line; a first and a second branch line; a branch flow control unit; an additional gas supply unit; an additional gas supply line; and a control unit. The control unit performs, before processing the substrate to be processed, a processing gas supply control and an additional gas supply control by using the processing gas supply unit and the additional gas supply unit, respectively, wherein the additional gas supply control includes a control that supplies the additional gas at an initial flow rate greater than a set flow rate and then at the set flow rate after a lapse of a period of time.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: July 29, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shinichiro Hayasaka, Ken Horiuchi, Fumiko Yagi, Takeshi Yokouchi
  • Patent number: 8778205
    Abstract: The present invention is a processing method including a processing step of performing predetermined processing for a workpiece; an unnecessary portion removal step of removing an unnecessary portion produced on a surface of the workpiece due to the predetermined processing; and a surface structure evaluation step of evaluating a surface structure of the workpiece from which the unnecessary portion has been removed by the unnecessary portion removal step.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: July 15, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tsuyoshi Ohno, Toshihiko Kikuchi, Machi Moriya, Yoshitaka Saita
  • Patent number: 8771530
    Abstract: A method for producing a polarizing element includes: forming particulate materials of a metal halide on a glass substrate; forming a protective film that covers the particulate materials in a non-plasma environment; stretching the particulate materials by heating and stretching the glass substrate; and forming acicular metal particles by reducing the metal halide constituting the stretched particulate materials.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: July 8, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Yoshitomo Kumai
  • Patent number: 8771525
    Abstract: In one embodiment, a rotary device includes a multiwall nanotube that extends substantially perpendicularly from a substrate. A rotor may be coupled to an outer wall of the multiwall nanotube, be spaced apart from the substrate, and be free to rotate around an elongate axis of the multiwall nanotube.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: July 8, 2014
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: David J. Carter, Marc S. Weinberg, Eugene Cook, Peter Miraglia
  • Patent number: 8764905
    Abstract: A method and system for cleaning lithography components including contacting a substrate having residue including organic compounds and graphitic carbon deposited on a surface thereof with hydrogen peroxide vapor. The hydrogen peroxide vapor is irradiated with electromagnetic radiation having a wavelength in the range of 100 nm to 350 nm forming hydroxyl radicals. The hydroxyl radicals react with the residue to remove the residue from the surface of the substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: Paul A. Zimmerman, Christof G. Krautschik
  • Patent number: 8764999
    Abstract: A method for patterning a substrate is described. The patterning method may include performing a lithographic process to produce a pattern and a critical dimension (CD) slimming process to reduce a CD in the pattern to a reduced CD. Thereafter, the pattern is doubled to produce a double pattern using a sidewall image transfer technique.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: July 1, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shannon W. Dunn, Dave Hetzer
  • Patent number: 8764952
    Abstract: In a method of irradiating a gas cluster ion beam on a solid surface and smoothing the solid surface, the angle formed between the solid surface and the gas cluster ion beam is chosen to be between 1° and an angle less than 30°. In case the solid surface is relatively rough, the processing efficiency is raised by first irradiating a beam at an irradiation angle ? chosen to be something like 90° as a first step, and subsequently at an irradiation angle ? chosen to be 1° to less than 30° as a second step. Alternatively, the set of the aforementioned first step and second step is repeated several times.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: July 1, 2014
    Assignee: Japan Aviation Electronics Industry Limited
    Inventors: Akinobu Sato, Akiko Suzuki, Emmanuel Bourelle, Jiro Matsuo, Toshio Seki, Takaaki Aoki
  • Patent number: 8759227
    Abstract: A method for processing a target object includes arranging a first electrode and a second electrode for supporting the target object in parallel to each other in a processing chamber and processing the target object supported by the second electrode by using a plasma of a processing gas supplied into the processing chamber, the plasma being generated between the first electrode and the second electrode by applying a high frequency power between the first electrode and the second electrode. The target object includes an organic film and a photoresist layer formed on the organic film. The processing gas contains H2 gas, and the organic film is etched by a plasma containing H2 by using the photoresist layer as a mask while applying a negative DC voltage to the first electrode.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 24, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Kazuki Narishige, Kazuo Shigeta
  • Patent number: 8747684
    Abstract: A method and apparatus for plasma etching a workpiece, such as a semiconductor wafer, including a thin film stack having a top film disposed over a bottom film with an intervening middle film there between. Etch selectivity between the top and bottom films may be as low as between 1:1 and 2:1 and a first carbon-lean gas chemistry is used to etch through the top film, a second carbon-lean gas chemistry is used to etch through the middle film, and the bottom film is etched through by alternating between depositing a polymer passivation on the top film using a carbon-rich gas chemistry and an etching of the bottom film with a third carbon-lean gas chemistry, which may be the same as the first carbon-lean gas chemistry.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: June 10, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Sunil Srinivasan, Jinhan Choi, Anisul H. Khan
  • Patent number: 8748318
    Abstract: The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a radiation-imageable layer over a material. A lattice pattern is then formed within the radiation-imageable layer, with the lattice pattern defining a plurality of islands of the radiation-imageable layer. The lattice-patterned radiation-imageable layer is utilized as a mask while subjecting the material under the lattice-patterned layer to an etch which transfers the lattice pattern into the material. The etch forms a plurality of pillars which extend only partially into the material, with the pillars being spaced from one another by gaps. The gaps are subsequently narrowed with a second material which only partially fills the gaps.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Publication number: 20140151330
    Abstract: The present invention relates to a method for treating a block copolymer solution, wherein the method comprises: providing a solution comprising a block copolymer in a non aqueous solvent; and, treating the solution to remove metals using an ion exchange resin. The invention also relates to a method of forming patterns using the treated block copolymer.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 5, 2014
    Applicant: AZ ELECTRONIC MATERIALS (LUXEMBOURG) S.A.R.L.
    Inventors: Jian YIN, Hengpeng WU, Muthiah THIYAGARAJAN, SungEun HONG, Mark NEISSER, Yi CAO
  • Patent number: 8741165
    Abstract: An apparatus for etching a dielectric layer contained by a substrate is provided. An etch reactor comprises a top electrode and a bottom electrode. An etch gas source supplies an etch gas into the etch reactor. A first Radio Frequency (RF) source generates a first RF power with a first frequency and supplies the first RF power into the etch reactor, whereas the first frequency is between 100 kilo Hertz (kHz) and 600 kHz. A second RF source generates a second RF power with a second frequency and supplies the second RF power into the etch reactor, whereas the second frequency is at least 10 mega Hertz (MHz).
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: June 3, 2014
    Assignee: Lam Research Corporation
    Inventors: Bing Ji, Erik A. Edelberg, Takumi Yanagawa
  • Patent number: 8728333
    Abstract: A three step ion beam etch (IBE) sequence involving low energy (<300 eV) is disclosed for trimming a sensor critical dimension (free layer width=FLW) to less than 50 nm. A first IBE step has a steep incident angle with respect to the sensor sidewall and accounts for 60% to 90% of the FLW reduction. The second IBE step has a shallow incident angle and a sweeping motion to remove residue from the first IBE step and further trim the sidewall. The third IBE step has a steep incident angle to remove damaged sidewall portions from the second step and accounts for 10% to 40% of the FLW reduction. As a result, FLW approaching 30 nm is realized while maintaining high MR ratio of over 60% and low RA of 1.2 ohm-?m2. Sidewall angle is manipulated by changing one or more ion beam incident angles.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: May 20, 2014
    Assignee: Headway Technologies, Inc.
    Inventors: Hui-Chuan Wang, Tong Zhao, Min Zheng, Minghui Yu, Min Li, Cherng Chyi Han
  • Patent number: 8728335
    Abstract: A silsesquioxane resin is applied over the patterned photo-resist and cured at the pattern surface to produce a cured silsesquioxane resin on the pattern surface. The uncured silsesquioxane resin layer is then removed leaving the cured silsesquioxane resin on the pattern surface. The cured silsesquioxane resin on horizontal surfaces is removed to expose the underlying photo-resist. This photo-resist is removed leaving a pattern of cured silsesquioxane. Optionally, the new pattern can be transferred into the underlying layer(s).
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: May 20, 2014
    Assignee: Dow Corning Corporation
    Inventors: Peng-Fei Fu, Eric Scott Moyer, Jason D. Suhr
  • Patent number: 8728337
    Abstract: A method is for processing a substrate. The method includes placing the substrate in a process volume and introducing a process gas or vapor into the process volume and/or subsequently removing gas or vapor from the volume. The step of introducing and/or removing the gas is at least partially performed by moving a movable wall to change the process volume in an appropriate sense.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: May 20, 2014
    Assignee: SPTS Technologies Limited
    Inventors: Carl Brancher, John MacNeil, Robert Trowell
  • Patent number: 8721906
    Abstract: An embodiment of the present inventions provides a method for preconditioning a semiconductor fabrication component using a plasma etching process and an optional enhanced ultrasonic and/or megasonic preconditioning step in order to eliminate the need for a burn-in period typically associated with said components, as well as extend the useful life of the component during its wear-out phase.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: May 13, 2014
    Assignee: Poco Graphite, Inc.
    Inventor: Wayne Hambek
  • Patent number: 8715516
    Abstract: An optical element having a three-dimensional structure which can function in a visible range and can improve adherence at a structural interface of the element, and a method of manufacturing the optical element. The optical element includes a substrate, and at least a first layer and a second layer on the substrate are manufactured such that each of the first layer and the second layer has a repetition structure of spaces and structural parts at a pitch equal to or less than a wavelength of visible light, and at an interface between the first layer and the second layer, overlapped structures are provided in which the repetition structure of the first layer and the repetition structure of the second layer overlap in a stack direction of the layers.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: May 6, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Jun-ichi Sakamoto, Junji Terada, Noriyuki Nakai, Kazuhiro Arai
  • Patent number: 8715514
    Abstract: Provided are a micro-electromechanical systems (MEMS) microphone and a method of manufacturing the same. A manufacturing process is simplified compared to a conventional art using both upper and lower substrate processes. Since defects which may occur during manufacturing are reduced due to the simplified manufacturing process, the manufacturing throughput is improved, and since durability of the MEMS microphone is improved, system stability against the external environment is improved.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: May 6, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae Woo Lee, Kang Ho Park, Jong Dae Kim