Gas Phase Etching Of Substrate Patents (Class 216/58)
  • Patent number: 8206605
    Abstract: A substrate processing method capable of preventing a reduction in productivity of the fabrication of a semiconductor device from a substrate. An HF gas is supplied toward a wafer having a thermally-oxidized film, a BPSG film, and a deposit film, to thereby selectively etch the BPSG film and the deposit film using fluorinated acid. A residual matter of H2SiF6 produced at the time of etching is decomposed into HF and SiF4 by being heated.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: June 26, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Daisuke Hayashi
  • Patent number: 8202439
    Abstract: A diaphragm is formed by etching a substrate. This substrate has a first surface provided with a depression by isotropic dry etching, and a second surface opposite the first surface. Furthermore, a through-hole is formed from the depression to the second surface by anisotropic dry etching. The depression and the through-hole are formed by using one resist mask. The depression has a hemispherical shape or a semi-elliptical spherical shape.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: June 19, 2012
    Assignee: Panasonic Corporation
    Inventors: Masaya Nakatani, Soichiro Hiraoka, Hiroshi Ushio, Akiyoshi Oshima, Hiroaki Oka, Fumiaki Emoto
  • Patent number: 8202435
    Abstract: A method for selectively etching areas of a substrate is described. The method includes providing in a process chamber a substrate containing a first material having a film deposition surface and a second material having an etch surface. The method further includes forming a gas cluster ion beam (GCIB) from a pressurized gas containing a deposition-etch gas, and exposing the substrate to the GCIB to remove at least a portion of the second material from the etch surface and deposit a thin film on the film deposition surface of the first material. According to some embodiments, the deposition-etch gas may contain silicon (Si) and carbon (C), and it may possess a Si—C bond.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: June 19, 2012
    Assignee: TEL Epion Inc.
    Inventor: Martin D. Tabat
  • Patent number: 8197701
    Abstract: Diamond SPM and AFM probes which are durable, particularly for scanning hard surfaces such as diamond surfaces. Interlayers and seeding can be used to improve diamond deposition, and the diamond can be ultrananocrystalline diamond (UNCD). Tip sharpening improves resolution.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: June 12, 2012
    Assignee: Advanced Diamond Technologies, Inc.
    Inventors: John A. Carlisle, Nicolaie Moldovan
  • Patent number: 8197703
    Abstract: A method and system to modify a surface composition of thin film Group IBIIIA VIA solar cell absorbers having non-uniformly distributed Group IIIA materials or graded materials, such as Indium (In), gallium (Ga) and aluminum (Al). The graded materials distribution varies between the surface and the bottom of the absorber layer such that a molar ratio of (Ga+Al)/(Ga+Al+In) is the highest at the bottom of the absorber layer and the lowest at the surface of the absorber. Within the bulk of the absorber, the molar ratio gradually changes between the bottom and the surface of the absorber. In one embodiment, the surface composition of a graded absorber layer may be modified by removing a top portion or slice of the absorber layer, where the molar ratio is low so as to expose the inner portions of the absorber layer having a higher molar ratio of graded materials.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: June 12, 2012
    Assignee: SoloPower, Inc.
    Inventor: Bulent M. Basol
  • Patent number: 8187389
    Abstract: A resist removing device 1 functions to remove a resist from a substrate while preventing occurrence of popping phenomenon and at the same time attains reduction in cost of energy for the resist removing and has a simplified constitution. The resist removing device 1 is equipped with a chamber 2 for containing therein a substrate 16 (for example, a substrate having a high-doze ion implanted resist), and with a pressure below the atmospheric pressure, the chamber 2 is fed with ozone gas, unsaturated hydrocarbons and water vapor. The ozone gas may be an ultra-high concentrated ozone gas that is produced by subjecting an ozone containing gas to a liquefaction-separation with the aid of a vapor pressure difference and then vaporizing the liquefied ozone. For cleaning the substrate 16 thus treated, it is preferable to use ultra-pure water. The chamber 2 is equipped with a susceptor 15 for holding the substrate 16. The susceptor 15 is heated to a temperature of 100° C. or below.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: May 29, 2012
    Assignee: Meidensha Corporation
    Inventor: Toshinori Miura
  • Patent number: 8182707
    Abstract: A method for etching a layer that is to be removed on a substrate, in which a Si1-xGex layer is the layer to be removed, this layer being removed, at least in areas, in gas phase etching with the aid of an etching gas, in particular ClF3. The etching behavior of the Si1-xGex layer can be controlled via the Ge portion in the Si1-xGex layer. The etching method is particularly well-suited for manufacturing self-supporting structures in a micromechanical sensor and for manufacturing such self-supporting structures in a closed hollow space, because the Si1-xGex layer, as a sacrificial layer or filling layer, is etched highly selectively relative to silicon.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: May 22, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Franz Laermer, Silvia Kronmueller, Tino Fuchs, Christina Leinenbach
  • Publication number: 20120120153
    Abstract: A nozzle plate including protruding nozzles and a method of manufacturing the nozzle plate. The nozzle plate may include a body unit and at least one nozzle protruding from the body unit. The at least one nozzle may include an exit part having a constant cross-sectional area and a damper part having a cross-sectional area that decreases in a direction toward the exit part, wherein the damper part of the at least one nozzle includes a plurality of inner wall surfaces having different angles of inclination.
    Type: Application
    Filed: April 25, 2011
    Publication date: May 17, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sung-gyu Kang
  • Patent number: 8178857
    Abstract: A method for flattening a sample surface by irradiating the sample surface with a gas cluster ion beam, generates clusters of source gas in a cluster generating chamber, ionizes the generated clusters in an ionization chamber, accelerates the ionized cluster beam in an electric field of an accelerating electrode, selects a cluster size using a magnetic field of a sorting mechanism, and irradiates the surface of a sample. An irradiation angle between the sample surface and the gas cluster ion beam is less than 30° and an average cluster size of the gas cluster ion beam is 50 or above.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: May 15, 2012
    Assignee: Japan Aviation Electronics Industry, Limited
    Inventors: Akinobu Sato, Akiko Suzuki, Emmanuel Bourelle, Jiro Matsuo, Toshio Seki
  • Publication number: 20120111833
    Abstract: There is provided a substrate processing method, in which a throughput can be improved even in case the time for recovery processing for restoring the state of a processing chamber is longer than the time for predetermined processing to be performed in the processing chamber. Substrates are alternately transferred to two processing chambers C, D, and the same film forming processing is performed on the substrates in the processing chambers C, D in parallel with each other. When the number of substrates processed in the processing chamber C has reached a predetermined number (11 substrates), dummy sputtering processing in the film forming chamber C is started and also 23rd-25th substrates of the first lot are transferred to the film forming chamber D to thereby perform film forming processing until the dummy sputtering processing is finished.
    Type: Application
    Filed: July 15, 2010
    Publication date: May 10, 2012
    Inventors: Shinya Nakamura, Yoshinori Fujii, Hideto Nagashima
  • Patent number: 8173035
    Abstract: A surface texturization method is provided. First, a polymer film is formed on a substrate. Thereafter, a heating treatment is performed on the substrate. The heating treatment results in a textured polymer film having island-shaped and/or microcrack-shaped patterns. Afterwards, an etching process is performed using the textured polymer film as a mask, so as to remove a portion of the substrate to form a textured structure on the surface of the substrate.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: May 8, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Ching-Hsi Lin, Chen-Hsun Du, Chung-Wen Lan
  • Patent number: 8173031
    Abstract: Nozzle members, such as for a micro-fluid ejection head, micro-fluid ejection heads, and a method for making the same. One such nozzle member includes a negative photoresist composition derived from a first di-functional epoxy compound, a relatively high molecular weight polyhydroxy ether, a photoacid generator devoid of aryl sulfonium salts, an adhesion enhancer, and an aliphatic ketone solvent. The nozzle member has a thickness ranging from about 10 microns to about 30 microns.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: May 8, 2012
    Assignee: Lexmark International, Inc.
    Inventors: Sean T. Weaver, Rich Wells
  • Patent number: 8173029
    Abstract: According to one embodiment, a cured first ultraviolet-curing resin material layer having a first three-dimensional pattern is formed on a first principal surface of a magnetic recording medium having a central hole. A cured second ultraviolet-curing resin material layer having a second three-dimensional pattern is formed on a second principal surface opposite to the first principal surface of the magnetic recording.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Morita, Shinobu Sugimura, Kazuyo Umezawa, Masatoshi Sakurai
  • Patent number: 8173028
    Abstract: A magnetic head includes a pole layer, first and second side shields, and an encasing layer having first to third grooves that accommodate the pole layer and the first and second side shields. A manufacturing method for the magnetic head includes the step of forming the first to third grooves in a nonmagnetic layer by using an etching mask layer having first to third openings. This step includes the steps of forming the first groove by etching the nonmagnetic layer using the first opening, with the second and third openings covered with a first mask; and forming the second and third grooves by etching the nonmagnetic layer using the second and third openings, with the first opening covered with a second mask.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: May 8, 2012
    Assignee: Headway Technologies, Inc.
    Inventors: Kazuo Ishizaki, Yoshitaka Sasaki, Hironori Araki, Hiroyuki Ito, Shigeki Tanemura, Cherng-Chyi Han
  • Patent number: 8158521
    Abstract: A method of lowering the dielectric constant of an organosilicon low k dielectric layer while improving the hardness and thermal stability is provided. A deposited layer of carbon doped oxide, HSQ, or MSQ is cured and treated with a He plasma which improves hardness for a subsequent CMP step and lowers the dielectric constant. There is no loss of H2O or CH4 during the He treatment. The low k dielectric layer is then treated with a H2 plasma which converts some of the Si—O and Si—CH3 bonds near the surface to Si—H bonds, thereby further lowering the dielectric constant and increasing thermal stability that improves breakdown resistance. Moisture uptake is also reduced. The method is especially useful for interconnect schemes with deep sub-micron ground rules. Surprisingly, the k value obtained from two different plasma treatments is lower than when two He treatments or two H2 treatment are performed.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: April 17, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Chung-Chi Ko, Tien I Bao, Yun-Chen Lu
  • Patent number: 8159056
    Abstract: A method of forming a device is provided. A substrate having a component is provided and a sacrificial layer is formed over the component. The sacrificial layer includes a cavity portion disposed about the component and a tunnel portion adjacent to the cavity portion. In addition, an encapsulation layer having a cover portion and a perimeter portion is formed over the sacrificial layer. The cover portion encapsulates the cavity portion such that the cavity portion forms a cavity within the cover portion. The perimeter portion is disposed over the tunnel portion. Moreover, an access hole is formed in the perimeter portion of the encapsulation layer.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: April 17, 2012
    Assignee: RF Micro Devices, Inc.
    Inventors: Sangchae Kim, Steven Crist
  • Patent number: 8158017
    Abstract: A method of detecting substrate arcing in a semiconductor plasma processing apparatus is provided. A substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. Process gas is introduced into the reaction chamber. A plasma is generated from the process gas and the substrate is processed with the plasma. Intensities of real-time spectrometry signals of selected gas species produced in the reaction chamber during plasma processing are monitored. The selected gas species are generated by a substrate arcing event. The arcing event is detected when the intensities are above a threshold value.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: April 17, 2012
    Assignee: Lam Research Corporation
    Inventor: Eric Hudson
  • Publication number: 20120085167
    Abstract: The invention relates to measuring devices to be used in the measuring of angular velocity and, more precisely, to vibrating micromechanical sensors of angular velocity. In a sensor of angular velocity according to the invention, a mass is supported to the frame of the sensor component by means of an asymmetrical spring structure (1), (2), (3), (4), (22), (24) in such a way, that the coupling from one mode of motion to another, conveyed by the spring (1), (2), (3), (4), (22), (24), cancels or alleviates the coupling caused by the non-ideality due to the skewness in the springs or in their support. The structure of the sensor of angular velocity according to the invention enables reliable measuring with good performance, particularly in small vibrating micromechanical solutions for sensors of angular velocity.
    Type: Application
    Filed: December 16, 2011
    Publication date: April 12, 2012
    Applicant: VTI Technologies Oy
    Inventors: Petri KLEMETTI, Kaisa NERA, Antti LIPSANEN, Anssi BLOMQVIST, Altti TORKKELI
  • Patent number: 8153533
    Abstract: Methods for preventing feature collapse subsequent to etching a layer encasing the features include adding a non-aqueous liquid to a microelectronic topography having remnants of an aqueous liquid arranged upon its surface and subsequently exposing the topography to a pressurized chamber including a fluid at or greater than its saturated vapor pressure or critical pressure. The methods include flushing from the pressurized chamber liquid arranged upon the topography and, thereafter, venting the chamber in a manner sufficient to prevent liquid formation therein. The topography features may be submerged in a liquid while pressurizing the chamber. A process chamber used to prevent feature collapse includes a substrate holder for supporting a microelectronic topography, a vessel configured to contain the substrate holder, and a sealable region surrounding the substrate holder and the vessel. The chamber is configured to sequester wet chemistry supplied to the vessel from metallic surfaces of the sealable region.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: April 10, 2012
    Assignee: Lam Research
    Inventors: James P. DeYoung, Mark I. Wagner
  • Patent number: 8147914
    Abstract: Disclosed is a structure made of a trench patterned substrate having a pre-determined trench period and a pre-determined mesa to trench width ratio, and a block copolymer on top of the trench patterned substrate. The block copolymer has at least an organic block and a silicon-containing block, wherein the block copolymer can have either perpendicular or parallel cylinders. The structure is annealed under a pre-determined vapor pressure for a predetermined annealing time period, wherein the pre-determined trench period, the pre-determined mesa to trench width ratio, the predetermined vapor pressure and the predetermined annealing time period are chosen such that cylinders formed in the block copolymer are either perpendicular or parallel with respect to the trench-patterned substrate. A method is also described to form the above-mentioned structure.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: April 3, 2012
    Assignee: Massachusetts Institute of Technology
    Inventors: Yeon Sik Jung, Caroline A. Ross
  • Patent number: 8143165
    Abstract: A method of manufacturing an integrated circuit on semiconductor substrates, e.g., silicon wafer. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. In a specific embodiment, the semiconductor substrate has an overlying film of material with a second lattice with a second structure and a second spacing, the second spacing placing the film of material in a strain mode characterized by a first tensile and/or compressive mode along a single film surface crystal axis across a first portion of the film of material relative to the semiconductor substrate with the first structure and the first spacing. The method patterns a predetermined region of the first portion of the film of material to cause the first tensile and/or compressive mode in the first portion of the film of material to change to a second tensile and/or compressive mode in a resulting patterned portion of the first portion of the film of material.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: March 27, 2012
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Patent number: 8137575
    Abstract: The invention relates to a control of etching processes of insulating substrates by means of gloss measurement. By this method a surface roughness can be achieved which leads to good adhesion of metals layers deposited in subsequent metallization steps. This method is particularly suited for the production of printed circuit boards.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: March 20, 2012
    Assignee: Atotech Deutschland GmbH
    Inventors: Merten Piel, Brigitte Steder, legal representative, Rolf Piel, legal representative, Elke Piel, legal representative, Lutz Stamp, Christiane Moepert
  • Patent number: 8137573
    Abstract: A method for manufacturing a liquid ejection head including a substrate and a member, disposed above the substrate, having passages communicatively connected to discharge ports through which a liquid is ejected includes providing first solid layers made of a positive photosensitive resin above the substrate such that outer side surfaces of the first solid layers form an obtuse angle with the substrate; providing a second solid layer above the substrate such that the second solid layer abuts the outer side surfaces of the first solid layers, the second solid layer being processed into at least one portion of a mold for the passages; exposing portions of the outer side surfaces of the first solid layers through the second solid layer; removing the exposed portions from the first solid layers; and providing a cover layer over the second solid layer, the cover layer being processed into the member.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: March 20, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Isamu Horiuchi
  • Patent number: 8138096
    Abstract: In a plasma etching method, a substrate including an underlying film, an insulating film and a resist mask is plasma etched to thereby form a number of holes in the insulating film including a dense region and a sparse region by using a parallel plate plasma etching apparatus for applying a plasma-generating high frequency electric power to a space between an upper and a lower electrode and a biasing high frequency electric power to the lower electrode. The plasma etching method includes mounting the substrate on a mounting table; supplying a first process gas containing carbon and fluorine to form the holes in the insulating film to a depth close to the underlying film; and supplying a second process gas including an inert gas and another gas contain carbon and fluorine to have the holes reach the underlying film while applying a negative DC voltage to the upper electrode.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: March 20, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Ryoichi Yoshida
  • Patent number: 8137641
    Abstract: A method of making a microfluidic module is disclosed that includes forming a fluid flow channel in a self-bonding rebondable polyimide film to provide a channel sheet, the self-bonding rebondable polyimide film having a first mask layer self-bonded thereto; removing the first mask layer from the channel sheet after forming the fluid flow channel; and self-bonding the surface of the channel sheet exposed by removal of the first mask layer to a cover sheet.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: March 20, 2012
    Assignee: YSI Incorporated
    Inventor: Donald R. Moles
  • Patent number: 8133818
    Abstract: In a method of forming a hard mask pattern in a semiconductor device, only processes for forming patterns having a row directional line shape and a column directional line shape on a plane are performed so that the hard mask patterns can be formed to define densely disposed active regions. A pitch of the hard mask patterns is less than a resolution limit of an exposure apparatus.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: March 13, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Woo Yung Jung
  • Patent number: 8129285
    Abstract: A substrate processing method implemented in a substrate processing system that includes an etching apparatus that carries out plasma etching processing on a substrate and a vacuum-type substrate transferring apparatus to which the etching apparatus is connected is provided. A first step includes forming a protective film on a rear surface of the substrate before the plasma etching processing is carried out. The protective film prevents the rear surface of the substrate from being scratched by an electrostatic chuck that electrostatically attracts the substrate during the plasma etching processing. A second step includes electrostatically attracting the substrate to the electrostatic chuck such that the electrostatic chuck directly contacts the rear surface of the substrate and of carrying out the plasma etching processing on the substrate. A third step includes removing the protective film from the rear surface of the substrate after the plasma etching processing has been carried out.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: March 6, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Eiichi Nishimura
  • Patent number: 8129286
    Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
  • Publication number: 20120052597
    Abstract: The invention relates to a recognizable carrier for determining physical, chemical or biochemical interactions by means of optical measurement methods. The carrier comprises a surface that defines a substrate surface and that has a base layer coated with reactive elements, which are bonded to receptor molecules, wherein the base layer and/or the reactive elements are provided with a pattern of holes which forms a code and/or the reactive elements are provided with linker molecules or markers which form a code. The substrate surface may additionally have a macroscopically planar pattern which is applied using laser light or chemical etching and forms a code. The invention likewise relates to a method for producing a recognizable carrier for spectroscopic processes and/or intensiometric tests to determine said interactions. The code to recognize the carrier can be controlled via a read-out unit coupled to the photometric analysis unit.
    Type: Application
    Filed: May 4, 2010
    Publication date: March 1, 2012
    Inventors: Johannes Landgraf, Günther Proll, Florian Pröll
  • Patent number: 8123960
    Abstract: Methods for fabricating sublithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Patent number: 8124541
    Abstract: An etchant gas and a method for removing at least a portion of a late transition metal structure. The etchant gas includes PF3 and at least one oxidizing agent, such as at least one of oxygen, ozone, nitrous oxide, nitric oxide and hydrogen peroxide. The etchant gas provides a method of uniformly removing the late transition metal structure or a portion thereof. Moreover, the etchant gas facilitates removing a late transition metal structure with an increased etch rate and at a decreased etch temperature. A method of removing a late transition metal without removing more reactive materials proximate the late transition metal and exposed to the etchant gas is also disclosed.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8124537
    Abstract: A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O2 plasma etch is performed to etch through the CF-based polymer at the bottom of the trench. The O2 plasma etch has little effect on the SiOCl-based polymer, the thus the upper surfaces of the structure remain covered with polymer. Thus, these upper surfaces remain fully protected during subsequent etching of the layer to be etched.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: February 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hung Lee, Chia-Chi Chung, Hsin-Chih Chen, Jeff J. Xu, Neng-Kuo Chen
  • Patent number: 8123961
    Abstract: Methods for fabricating sublithographic, nanoscale arrays of openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Embodiments of the invention use a self-templating or multilayer approach to induce ordering of a self-assembling block copolymer film to an underlying base film to produce a multilayered film having an ordered array of nanostructures that can be removed to provide openings in the film which, in some embodiments, can be used as a template or mask to etch openings in an underlying material layer.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Patent number: 8119475
    Abstract: A method of forming a gate of a semiconductor device comprising providing a semiconductor substrate over which a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer are sequentially formed, the semiconductor substrate defining gate line regions; removing he second conductive layer between gate line regions; removing the dielectric layer so that a top surface of the first conductive layer between the gate line regions is exposed; performing a first etch process in order to lower a height of the first conductive layer between the gate line region; removing he dielectric layer between the gate line regions; and, performing a second etch process in order to remove the first conductive layer between the gate line regions.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: February 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Hoon Lee
  • Patent number: 8119020
    Abstract: A method for manufacturing an electronic device using a closed-type transport container, includes: controlling relative humidity inside the closed-type transport container to be lower than ambient relative humidity outside the closed-type transport container on a particular interprocess transport path in which an intermediate product stored in the closed-type transport container is transported from a first manufacturing process to a second manufacturing process. The first manufacturing process allows basic compounds containing nitrogen atoms to be released from the intermediate product. The second manufacturing process is susceptible to degradation due to contamination by the basic compounds.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: February 21, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Ito, Makiko Katano, Atsuko Kawasaki, Masahiro Kiyotoshi
  • Patent number: 8119018
    Abstract: A magnetoresistive effect element manufacturing method includes a first step of preparing a magnetoresistive effect element including a magnetic film and a substrate, a second step of etching a predetermined region of the magnetic film by a reactive ion etching method, and a third step of exposing the magnetic film having undergone the second step to a plasma at an ion current density of 4×10?7 A/cm2 or less.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: February 21, 2012
    Assignee: Canon Anelva Corporation
    Inventors: Manabu Ikemoto, Tomoaki Osada, Naoaki Yokokawa
  • Patent number: 8119017
    Abstract: The invention is a method for making a master mold to be used for nanoimprinting patterned-media magnetic recording disks. The method uses conventional optical or e-beam lithography to form a pattern of generally radial stripes on a substrate, with the stripes being grouped into annular zones or bands. A block copolymer material is deposited on the pattern, resulting in guided self-assembly of the block copolymer into its components to multiply the generally radial stripes into generally radial lines of alternating block copolymer components. The radial lines of one of the components are removed and the radial lines of the remaining component are used as an etch mask to etch the substrate. Conventional lithography is used to form concentric rings over the generally radial lines. After etching and resist removal, the master mold has pillars arranged in circular rings, with the rings grouped into annular bands.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: February 21, 2012
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Thomas R. Albrecht, Ricardo Ruiz
  • Patent number: 8114782
    Abstract: A method of etching or removing an amorphous carbon organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an amorphous carbon organic hardmask to be removed, the dielectric film having a dielectric constant no greater than about 4.0, introducing over the amorphous carbon organic hardmask an ionizable gas comprising a mixture of hydrogen and an oxidizing gas, and applying energy to the mixture to create a plasma of the mixture. The method further includes contacting the amorphous carbon organic hardmask with the plasma, with the amorphous carbon organic hardmask being at a temperature in excess of 200° C., to remove the amorphous carbon organic hardmask without substantially harming the underlying substrate.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: February 14, 2012
    Assignee: Novellus Systems, Inc.
    Inventor: Wesley P. Graff
  • Publication number: 20120027998
    Abstract: The present invention relates to a method for the replication of a patterned surface relief microstructure, comprising the steps of generation of a first layer with a patterned surface relief microstructure, generation of a master, by copying the microstructure of the first layer into a second layer, thereby involving at least one dry or wet etching step, characterized by an additional step, in which the microstructure of the master is brought into contact with a replica material, such that the microstructure of the master is reproduced in the replica. The invention further relates to the elements made as a replica according to the method. The surface relief microstructures are suitable to display images with a positive-negative and/or color image flip. The elements according to the invention are particularly useful for securing documents and articles against counterfeiting and falsification.
    Type: Application
    Filed: February 15, 2010
    Publication date: February 2, 2012
    Applicant: ROLIC AG
    Inventors: Mohammed Ibn-Elhaj, Julien Martz, Hubert Seiberle, Wolfgang Wernet
  • Patent number: 8105496
    Abstract: Improvements in an interferometric modulator that cavity defined by two walls.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: January 31, 2012
    Assignee: Qualcomm MEMS Technologies, Inc.
    Inventor: Mark W Miles
  • Patent number: 8097174
    Abstract: A microelectromechanical systems device having an electrical interconnect connected to at least one of an electrode and a movable layer within the device. At least a portion of the electrical interconnect is formed from the same material as a movable layer of the device. A thin film, particularly formed of molybdenum, is provided underneath the electrical interconnect. The movable layer preferably comprises aluminum.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: January 17, 2012
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Wonsuk Chung, SuryaPrakash Ganti, Stephen Zee
  • Patent number: 8097178
    Abstract: A surface acoustic wave device configured by forming an oxide layer 2 on a piezoelectric substrate 1 composed of a lithium tantalate single crystal or a lithium niobate single crystal and having weak pyroelectric properties having a lower oxygen content than a stoichiometric composition ratio, and forming thereon an IDT electrode 3. There is no static destruction of a minute electrode due to the pyroelectric effect of the piezoelectric substrate having weak pyroelectric properties, and frequency characteristics are not degraded.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: January 17, 2012
    Assignee: Kyocera Corporation
    Inventors: Ikuo Obara, Daisuke Makibuchi, Kunihiko Muraoka, Kiyohiro Iioka
  • Patent number: 8097179
    Abstract: A method for abating effluent from an etching process in one embodiment includes advancing etch gas product into a passageway of a gas connector in direct fluid communication with a first chamber of an interior void of an apparatus, advancing a gas from a gas source into said passageway of said gas connector at the same time said etch gas product is being advanced into said passageway, and advancing humidified gas from a humidified gas source into a second chamber of said interior void.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: January 17, 2012
    Assignee: LSI Corporation
    Inventors: Michael Williams, Michael Barthman
  • Patent number: 8092702
    Abstract: A method of multi-stage substrate etching and a terahertz oscillator manufactured by using the method are provided. The method comprises the steps of forming a first mask pattern on any one surface of a first substrate, forming a hole by etching the first substrate using the first mask pattern as an etching mask, bonding, to the first substrate, a second substrate having the same thickness as a depth to be etched, forming a second mask pattern on the second substrate bonded, forming a hole by etching the second substrate using the second mask pattern as an etching mask, and removing an oxide layer having the etching selectivity between the first substrate and the second substrate, whereby the etched bottom is made uniformly even in a deep step, the edge curvature is minimized, and a T-shape is prevented from being formed on the etched wall face to thereby improve the etching quality.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: January 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan Wook Baik, Jong Seok Kim, Seong Chan Jun, Sun Il Kim, Jong Min Kim, Chan Bong Jun, Sang Hun Lee
  • Patent number: 8092701
    Abstract: A grating of the present invention has a groove cross section shaped, for example, like a sinusoidal wave or a sawtooth other than a laminar shape, and a groove bottom part shaped as a flat form. In a region wherein the groove cycle and the used wavelength are the same degree for wavelengths from near infrared to infrared, the grating of the present invention has the excellent spectrum performance (high efficiency in balance in a wide wavelength zone) more than a holographic grating and an echellette grating in related arts. When replicas for the grating of the present invention are manufactured, the engagement force of grooves with each other is small as the groove aspect ratio is small, and a release agent sufficiently reaches the groove bottom as the groove bottom is large.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: January 10, 2012
    Assignee: Shimadzu Corporation
    Inventors: Tetsuya Nagano, Masaru Koeda, Makoto Sato, Akira Sato, Shinji Miyauchi
  • Publication number: 20120003142
    Abstract: A vapor-phase process apparatus and a vapor-phase process method capable of satisfactorily maintaining quality of processes even when different types of processes are performed are obtained. A vapor-phase process apparatus includes a process chamber, gas supply ports serving as a plurality of gas introduction portions, and a gas supply portion (a gas supply member, a pipe, a flow rate control device, a pipe, and a buffer chamber). The process chamber allows flow of a reaction gas therein. The plurality of gas supply ports are formed in a wall surface (upper wall) of the process chamber along a direction of flow of the reaction gas. The gas supply portion can supply a gas into the process chamber at a different flow rate from each of one gas supply port and another gas supply port different from that one gas supply port among the plurality of gas supply ports.
    Type: Application
    Filed: September 13, 2011
    Publication date: January 5, 2012
    Inventors: Eiryo Takasuka, Toshio Ueda, Toshiyuki Kuramoto, Masaki Ueno
  • Publication number: 20110318930
    Abstract: A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 29, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Ho Jeon, Dong-Hyun Kim, Je-Woo Han, Kyoung-Sub Shin
  • Patent number: 8083961
    Abstract: A method and system for treating a substrate using a ballistic electron beam is described, whereby the radial uniformity of the electron beam flux is adjusted by modulating the source radio frequency (RF) power. For example, a plasma processing system is described having a first RF power coupled to a lower electrode, which may support the substrate, a second RF power coupled to an upper electrode that opposes the lower electrode, and a negative high voltage direct current (DC) power coupled to the upper electrode to form the ballistic electron beam. The amplitude of the second RF power is modulated to affect changes in the uniformity of the ballistic electron beam flux.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: December 27, 2011
    Assignees: Tokyo Electron Limited, Texas Instruments Incorporated
    Inventors: Lee Chen, Ping Jiang
  • Publication number: 20110299969
    Abstract: The present invention relates to design and microfabrication methods for forming devices that are capable of grasping and actively releasing micro or nanometer-sized objects in ambient and vacuum environments. Grasping motion is produced by one or more microactuators, and rapid, accurate, highly reproducible active release is achieved through impacting an adhered object with a high-speed plunging structure. Two fabrication processes for constructing these new types of micro and nano gripping devices are also described.
    Type: Application
    Filed: February 17, 2009
    Publication date: December 8, 2011
    Inventors: Yu Sun, Brandon K. Chen, Yong Zhang
  • Patent number: 8070968
    Abstract: According to one embodiment, this invention uses an ultraviolet-curable resin material for pattern transfer containing 80 to 95 wt % of isobornyl acrylate, 1 to 20 wt % of trifunctional acrylate, and 0.5 to 6 wt % of a polymerization initiator.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: December 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyo Umezawa, Seiji Morita, Masatoshi Sakurai