Gas Phase Etching Of Substrate Patents (Class 216/58)
  • Patent number: 8329053
    Abstract: In accordance with an illustrative embodiment, a method of fabricating a transducer is described. The method comprises providing a transducer over a first surface of a substrate, wherein the substrate comprises a thickness. The method further comprises patterning a mask over a second surface. The mask comprises an opening for forming a scribe etch. The method comprises etching through the opening in the mask and into but not through the thickness of the substrate to provide the scribe etch.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: December 11, 2012
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: David Martin, Joel Philliber
  • Publication number: 20120308917
    Abstract: One aspect of the invention is a method of surface alloying stainless steel, In one embodiment, the method includes providing a stainless steel surface having an initial amount of iron and an initial amount of chromium; and preferentially removing iron from the stainless steel surface to obtain a surface having an amount of iron less than the initial amount of iron and an amount of chromium greater than the initial amount of chromium. Another aspect of the invention is a unitary stainless steel article.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 6, 2012
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Mahmoud H. Abd Elhamid, Gayatri Vyas Dadheech
  • Patent number: 8323515
    Abstract: A method for making a master disk to be used for nanoimprinting patterned-media magnetic recording disks uses sidewall lithography. In one implementation, the master disk substrate has a first pattern of concentric rings formed on it by sidewall lithography, followed by a second pattern of generally radially-directed pairs of parallel lines, also formed by sidewall lithography, with the pairs of parallel lines intersecting the rings. An etching process is then performed, using the upper pattern as an etch mask, to remove unprotected portions of the underlying concentric rings. This leaves a pattern of pillars on the substrate, which then serve as an etch mask for an etching process that etches unprotected portions of the master disk substrate. The resulting master disk then has pillars of substrate material arranged in a pattern of concentric rings and generally radially-directed pairs of parallel lines.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: December 4, 2012
    Assignee: Hitachi Global Technologies Netherlands B.V.
    Inventor: Thomas R. Albrecht
  • Patent number: 8324108
    Abstract: In a dual stress liner approach, unwanted material provided between closely spaced gate electrode structures may be removed to a significant degree on the basis of a wet chemical etch process, thereby reducing the risk of creating patterning-related irregularities. Consequently, the probability of contact failures in sophisticated interlayer dielectric material systems formed on the basis of a dual stress liner approach may be reduced.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: December 4, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Markus Lenski, Torsten Huisinga
  • Publication number: 20120298883
    Abstract: Provided are flow cell devices—referred to as nanoaquariums—that are microfabricated devices featuring a sample chamber having a controllable height in the range of nanometers to micrometers. The cells are sealed so as to withstand the vacuum environment of an electron microscope without fluid loss. The cells allow for the concurrent flow of multiple sample streams and may be equipped with electrodes, heaters, and thermistors for measurement and other analysis devices.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 29, 2012
    Applicant: THE TRUSTEES OF THE UNIVERSITY OF PENNSYLVANIA
    Inventors: Joseph M. Grogan, Haim H. Bau
  • Publication number: 20120292290
    Abstract: A substrate processing method is used for a substrate processing system having a substrate processing device and a substrate transfer device. The substrate processing method includes a substrate transfer step of transferring a substrate and a substrate processing step of performing a predetermined process on the substrate. The substrate transfer step and the substrate processing step include a plurality of operations, and at least two operations among the plurality of the operations are performed simultaneously. Preferably, the substrate processing device includes an accommodating chamber, a mounting table placed in the accommodating chamber to be mounted thereon the substrate, and a heat transfer gas supply line for supplying a heat transfer gas to a space between the substrate mounted on the mounting table and the mounting table.
    Type: Application
    Filed: August 2, 2012
    Publication date: November 22, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Seiichi Kaise, Noriyuki Iwabuchi, Shigeaki Kato, Hiroshi Nakamura, Takeshi Yokouchi, Mariko Shibata, Akira Obi
  • Publication number: 20120292289
    Abstract: A transport cylinder for the vacuum treatment of substrates includes a roll body and at least one spacer element arranged on the roll body and enveloping the roll body. The spacer element is made of a knitted tube containing metallic or/and metallic threads.
    Type: Application
    Filed: May 17, 2012
    Publication date: November 22, 2012
    Applicant: VON ARDENNE ANLAGENTECHNIK GMBH
    Inventors: Steffen MOSSHAMMER, Reinhardt BAUER, Thomas MEYER, Matthias SMOLKE, Michael HOFMANN, Torsten DSAAK
  • Patent number: 8313663
    Abstract: A method of treating a workpiece is described. The method comprises selectively forming a sacrificial material on one or more regions of a substrate or a layer on the substrate using a gas cluster ion beam (GCIB), and adjusting a surface profile of a surface on the substrate or the layer on the substrate by performing an etching process following the selective formation.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: November 20, 2012
    Assignee: TEL Epion Inc.
    Inventor: John J. Hautala
  • Publication number: 20120288686
    Abstract: A multi-layer stack for imprint lithography is formed by applying a first polymerizable composition to a substrate, polymerizing the first polymerizable composition to form a first polymerized layer, applying a second polymerizable composition to the first polymerized layer, and polymerizing the second polymerizable composition to form a second polymerized layer on the first polymerized layer. The first polymerizable composition includes a polymerizable component with a glass transition temperature less than about 25° C., and the first polymerized layer is substantially impermeable to the second polymerizable composition.
    Type: Application
    Filed: July 11, 2012
    Publication date: November 15, 2012
    Applicant: MOLECULAR IMPRINTS, INC.
    Inventors: Frank Y. Xu, Weijun Liu, Cynthia B. Brooks, Dwayne L. LaBrake, David J. Lentz
  • Publication number: 20120288672
    Abstract: The present invention relates to a method of producing a microstructured device, as well as a method of processing a microstructured substrate to heal surface defects therein, a method of bonding substrates and healing surface defects in a substrate, and microstructured devices produced by these methods.
    Type: Application
    Filed: May 12, 2011
    Publication date: November 15, 2012
    Inventors: Iain Rodney George Ogilvie, Cedric Florian Aymeric Floquet, Hywel Morgan, Vincent Joseph Sieben, Matthew Charles Mowlem
  • Patent number: 8308968
    Abstract: A scanning probe where the micromachined pyramid tip is extended by the growth of an epitaxial nanowire from the top portion of the tip is disclosed. A metallic particle, such as gold, may terminate the nanowire to realize an apertureless near-field optical microscope probe.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Hendrik F. Hamann
  • Patent number: 8303834
    Abstract: A plasma processing apparatus includes an inner upper electrode provided to face a lower electrode mounting thereon a substrate, an outer upper electrode provided in a ring shape at a radially outside of the inner upper electrode and electrically isolated from the inner upper electrode in a vacuum evacuable processing chamber and a processing gas supply unit for supplying a processing gas into a processing space between the inner and the outer upper electrode and the lower electrode. A radio frequency (RF) power supply unit is also provide to apply a RF power to the lower electrode or the inner and the outer upper electrode to generate a plasma of the processing gas by RF discharge. A first and a second DC power supply unit are provided to apply a first and a second variable DC voltage to the inner upper electrode, respectively.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: November 6, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Masanobu Honda, Kenji Masuzawa, Hiroyuki Nakayama, Manabu Iwata, Manabu Sato, Kazuki Narishige
  • Publication number: 20120273462
    Abstract: An etching device is provided, the etching device including a process chamber including an etchant, a structure configured to provide a laminar flow of the etchant, and a workpiece handler configured to move a workpiece through the laminar flow of the etchant along a predefined track.
    Type: Application
    Filed: April 28, 2011
    Publication date: November 1, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Fischer, Raimund Foerg, Sebastian Bernrieder, Michael Larisch
  • Publication number: 20120273458
    Abstract: The invention relates to a method for processing a substrate with a focussed particle beam which incidents on the substrate, the method comprising the steps of: (a) generating at least one reference mark on the substrate using the focused particle beam and at least one processing gas, (b) determining a reference position of the at least one reference mark, (c) processing the substrate using the reference position of the reference mark, and (d) removing the at least one reference mark from the substrate.
    Type: Application
    Filed: May 9, 2011
    Publication date: November 1, 2012
    Inventors: Tristan Bret, Petra Spies, Thorsten Hofmann
  • Patent number: 8298431
    Abstract: A first etching stop layer and an active layer are formed on an inner surface of a first glass substrate, and a second etching stop layer and a cover layer are formed on an inner surface of a second glass substrate. A display media is formed between the first glass substrate and the second glass substrate. A first passivation layer is formed on an outer surface of the second glass substrate. A first etching process is performed to expose the first etching stop layer. A first flexible substrate is formed on the exposed first etching stop layer, and a second passivation layer is formed on the first flexible substrate. The first passivation layer is removed. A second etching process is performed to expose the second etching stop layer. A second flexible substrate is formed on the exposed second etching stop layer, and the second passivation layer is removed.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: October 30, 2012
    Assignee: Au Optronics Corporation
    Inventors: Jong-Wen Chwu, Chao-Cheng Lin, Che-Yao Wu, Yu-Chen Liu, Wei-Chieh Yang
  • Patent number: 8298432
    Abstract: A method and system of location specific processing on a substrate is described. The method comprises establishing a gas cluster ion beam (GCIB) according to a set of beam properties and measuring metrology data for a substrate. Thereafter, the method comprises determining at least one spatial gradient of the metrology data at one or more locations on the substrate and adjusting at least one beam property in the set of beam properties for the GCIB according to the determined at least one spatial gradient. Using the metrology data and the adjusted set of beam properties, correction data for the substrate is computed. Following the computing, the adjusted GCIB is applied to the substrate according to the correction data.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: October 30, 2012
    Assignee: TEL Epion Inc.
    Inventors: Ruairidh MacCrimmon, Nicolaus J. Hofmeester, Steven P. Caliendo
  • Patent number: 8293126
    Abstract: A method and system of location specific processing on a substrate is described. The method comprises acquiring metrology data for a substrate, and computing correction data for adjusting a first region of the metrology data on the substrate. Thereafter, a first gas cluster ion beam (GCIB) for treating the high gradient regions is established, and the first GCIB is applied to the substrate according to the correction data. The method further comprises optionally acquiring second metrology data following the applying of the first GCIB, and computing second correction data for adjusting a second region of the metrology data, or the second metrology data, or both on the substrate. Thereafter, a second gas cluster ion beam (GCIB) for treating the second region is established, and the second GCIB is applied to the substrate according to the second correction data.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: October 23, 2012
    Assignee: TEL Epion Inc.
    Inventors: Ruairidh MacCrimmon, Nicolaus J. Hofmeester, Steven P. Caliendo
  • Patent number: 8288287
    Abstract: The invention provides an etching method for realizing trench etching without causing any damages to the side walls of the trench while maintaining a high-etching rate. The plasma etching method relates to forming a groove or a hole by forming a silicon trench to a silicon substrate or a silicon substrate having a silicon oxide dielectric layer via a mixed gas plasma containing a mixed gas of SF6 and O2 or a mixed gas of SF6, O2 and SiF4 and having added thereto a gas containing hydrogen within the range of 5 to 16% (percent concentration) of the total gas flow rate of the mixed gas.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: October 16, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Kazuo Takata, Yutaka Kudou, Satoshi Tani
  • Patent number: 8282848
    Abstract: A plasma processing apparatus includes: a film which is made of an insulative material and constructs a surface of a sample stage on which a sample is put; a disk-shaped member whose upper surface is joined with the film in a lower portion of the film and which is made of a heat conductive member; heaters which are arranged in the film and arranged in a center portion and regions of its outer peripheral side of the film; coolant channels which are arranged in the disk-shaped member and in which a coolant for cooling the disk-shaped member flows; a plurality of power sources each of which adjusts an electric power to each of the heaters in the plurality of regions; and a controller which adjusts outputs from the plurality of power sources by using a result obtained by presuming a temperature of the upper surface of the disk-shaped member.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: October 9, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yutaka Ohmoto, Mamoru Yakushiji, Yutaka Kouzuma, Ken Yoshioka, Tsunehiko Tsubone
  • Patent number: 8277673
    Abstract: In a plasma processing method, a conductor of an electrostatic chuck (ESC) and an electrode are electrically grounded prior to starting the plasma processing. A DC voltage with a polarity is applied to the conductor at a first time point after loading a substrate on the electrode. Then, the electrode is switched from an electrically grounded state to an electrically floating state at a second time point. A RF power is then applied to the electrode at a third time point. The application of the RF power is stopped at a fourth time point after a specified time has lapsed from the third time point. Then, the electrode is switched from the electrically floating state to the electrically grounded state at a fifth time point. Thereafter, the application of the DC voltage is stopped and the conductor is restored to a ground potential at a sixth time point.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: October 2, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Tsujimoto, Toshifumi Nagaiwa, Yuji Otsuka
  • Publication number: 20120241410
    Abstract: A process for treating a target region of a component surface with a treatment fluid including: a) determining an amount of treatment fluid required to treat the target region; b) feeding the determined amount of treatment fluid to a treatment device; c) continuously circulating the treatment fluid through an applicator of the treatment device whilst applying the applicator to the target region; and d) discarding the treatment fluid once the target region of the component surface has been treated. An apparatus for treating a target region of a component surface with a treatment fluid is also disclosed and which includes: a treatment fluid reservoir; a treatment device, operable to receive treatment fluid from the treatment fluid reservoir and to apply treatment fluid to the component; a holding fixture for supporting the component; and a sealable enclosure containing the treatment fluid reservoir, the treatment device and the holding fixture.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 27, 2012
    Applicant: ROLLS-ROYCE PLC
    Inventors: David W. MILLS, Daniel CLARK
  • Publication number: 20120245568
    Abstract: The present invention provides novel medical instruments and methods for fabricating them by using nano-technology processes.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 27, 2012
    Applicant: Anpac Bio-Medical Science Co., Ltd.
    Inventors: Chris C. Yu, Xuedong Du
  • Patent number: 8273260
    Abstract: A method of etching a semiconductor wafer is provided. The method comprises the steps of: jetting a mixed gas including hydrogen fluoride and ozone onto a surface of a semiconductor wafer; monitoring the surface of the semiconductor wafer; analyzing the surface of the semiconductor wafer; and adjusting at least one of the hydrogen fluoride concentration and the ozone concentration in the mixed gas based on a result of the analysis.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: September 25, 2012
    Assignee: Sumco Techxiv Corporation
    Inventors: Kazuaki Kozasa, Tomonori Kawasaki
  • Patent number: 8273257
    Abstract: In a method for processing a nanotube, a vapor is condensed to a solid condensate layer on a surface of the nanotube and then at least one selected region of the condensate layer is locally removed by directing a beam of energy at the selected region. The nanotube can be processed with at least a portion of the solid condensate layer maintained on the nanotube surface and thereafter the solid condensate layer removed. Nanotube processing can include, e.g., depositing a material layer on an exposed nanotube surface region where the condensate layer was removed. After forming a solid condensate layer, an electron beam can be directed at a selected region along a nanotube length corresponding to a location for cutting the nanotube, to locally remove the condensate layer at the region, and an ion beam can be directed at the selected region to cut the nanotube at the selected region.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: September 25, 2012
    Assignee: President and Fellows of Harvard College
    Inventors: Jene A Golovchenko, Gavin M King, Gregor M Schurmann, Daniel Branton
  • Patent number: 8273258
    Abstract: A disclosed fine pattern forming method includes steps of: forming patterns made of a first photoresist film, arranged at a first pitch on a film; trimming the patterns made of the first photoresist film; depositing a protection film on the patterns made of the first photoresist film on the trimmed patterns made of the first photoresist film, the protection film being made of reaction products of an etching gas, thereby obtaining first patterns; forming other patterns made of a second photoresist film, arranged at a second pitch, on the protection film, the other patterns made of the second photoresist film being shifted by half of the first pitch from the corresponding patterns made of the first photoresist film; trimming the other patterns made of the second photoresist film into second patterns; and etching the film using the first patterns and the second patterns.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: September 25, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Takashi Sone, Eiichi Nishimura
  • Patent number: 8268183
    Abstract: A solid surface is processed while corner portions of a relief structure are protected from deformation. A method of processing a solid surface with a gas cluster ion beam includes a cluster protection layer formation step of forming, on the solid surface, a relief structure having protrusions with a cluster protection layer formed to cover an upper part thereof and recesses without the cluster protection layer; an irradiation step of emitting a gas cluster ion beam onto the solid surface having the relief structure formed in the cluster protection layer formation step; and a removal step of removing the cluster protection layer. A thickness T of the cluster protection layer satisfies T > nY + ( b 2 ? Y 2 ? n - nY 2 ? ( b 4 - 16 ? a 2 ) 1 2 2 ) 1 2 , where n is a dose of the gas cluster ion beam, and Y is an etching efficiency of the cluster protection layer, expressed as an etching volume per cluster (a and b are constants).
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: September 18, 2012
    Assignee: Japan Aviaton Electronics Industry, Limited
    Inventors: Akiko Suzuki, Akinobu Sato, Emmanuel Bourelle, Jiro Matsuo, Toshio Seki
  • Patent number: 8262920
    Abstract: A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C4F8, forming a plasma from the deposition gas, depositing a polymer from the plasma for at least 20 seconds, and stopping the depositing the polymer after the at least 20 seconds. The deposited polymer layer is opened by flowing an opening gas, forming a plasma from the opening gas which selectively removes the deposited polymer on bottoms of the plurality of mask openings with respect to deposited polymer on sides of the plurality of mask openings, and stopping the opening when at least some of the plurality of mask features are opened. The silicon layer is etched through the mask and deposited polymer layer.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: September 11, 2012
    Assignee: Lam Research Corporation
    Inventors: Tamarak Pandhumsoporn, Patrick Chung, Jackie Seto, S. M. Reza Sadjadi
  • Patent number: 8257599
    Abstract: In a thermal head manufacturing method, at least one concave portion is formed on a surface of a first substrate, and a second substrate comprised of a first layer and a second layer that is denser and harder than the first layer is provided. The first and second substrates are bonded to one another so that the second layer of the second substrate covers the concave portion of the first substrate. The first layer of the second substrate is then etched until a surface of the second layer of the second substrate is exposed. At least one heating resistor is formed on the exposed surface of the second layer of the second substrate after the etching step so that the heating resistor is disposed over the concave portion of the first substrate.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: September 4, 2012
    Assignee: Seiko Instruments Inc.
    Inventors: Norimitsu Sanbongi, Toshimitsu Morooka, Keitaro Koroishi, Noriyoshi Shoji, Yoshinori Sato
  • Patent number: 8257597
    Abstract: Methods of forming a write pole are disclosed. A first photomask having a first opening over one of a yoke region and a pole tip region of the write pole is formed over an insulation layer having an insulator material. A first etch process is performed on the insulation layer via the first opening, the first etch process removing the insulator material from a corresponding one of the yoke region and the pole tip region. A second photomask having a second opening over the other one of the yoke region and the pole tip region is formed over the insulation layer. A second etch process is performed on the insulation layer via the second opening, the second etch process removing the insulator material from a corresponding one of the yoke region and the pole tip region.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: September 4, 2012
    Assignee: Western Digital (Fremont), LLC
    Inventors: Lijie Guan, Changqing Shi, Ming Jiang, Yun-Fei Li
  • Patent number: 8257601
    Abstract: A substrate processing method is used for a substrate processing system having a substrate processing device and a substrate transfer device. The substrate processing method includes a substrate transfer step of transferring a substrate and a substrate processing step of performing a predetermined process on the substrate. The substrate transfer step and the substrate processing step include a plurality of operations, and at least two operations among the plurality of the operations are performed simultaneously. Preferably, the substrate processing device includes an accommodating chamber, a mounting table placed in the accommodating chamber to be mounted thereon the substrate, and a heat transfer gas supply line for supplying a heat transfer gas to a space between the substrate mounted on the mounting table and the mounting table.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: September 4, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Seiichi Kaise, Noriyuki Iwabuchi, Shigeaki Kato, Hiroshi Nakamura, Takeshi Yokouchi, Mariko Shibata, Akira Obi
  • Patent number: 8257598
    Abstract: The invention is a method for making a master mold to be used for nanoimprinting patterned-media magnetic recording disks. The method uses conventional optical or e-beam lithography to form a pattern of generally radial stripes on a substrate, with the stripes being grouped into annular zones or bands. A block copolymer material is deposited on the pattern, resulting in guided self-assembly of the block copolymer into its components to multiply the generally radial stripes into generally radial lines of alternating block copolymer components. The radial lines of one of the components are removed and the radial lines of the remaining component are used as an etch mask to etch the substrate. Conventional lithography is used to form concentric rings over the generally radial lines. After etching and resist removal, the master mold has pillars arranged in circular rings, with the rings grouped into annular bands.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: September 4, 2012
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Thomas R. Albrecht, Ricardo Ruiz
  • Patent number: 8252690
    Abstract: A method of forming a seed layer of an interconnect structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form the seed layer; and in-situ performing a first etch step to remove a portion of the seed layer. The method may further includes additional deposition and etch steps for forming the seed layer.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: August 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Lin Su, Cheng-Lin Huang, Shing-Chyang Pan, Ching-Hua Hsieh
  • Patent number: 8246846
    Abstract: A method for fabricating integrated MEMS switches and filters includes forming cavities in a silicon substrate, metalizing a first pattern on a quartz substrate to form first switch and filter elements, bonding the quartz substrate to the silicon substrate so that the first switch and filter elements are located within one of the cavities, thinning the quartz substrate, forming conductive vias in the quartz substrate, metalizing a second pattern on a second surface of the quartz substrate to form second switch and filter elements, etching the quartz substrate to separate MEMS switches from filters, forming protrusions on a host substrate, metalizing a third metal pattern on the host substrate to form metal anchors and third switch elements, compression bonding the metal anchors on the host substrate to second switch and filter elements, forming signal lines to integrate the MEMS switches and filters and removing the silicon substrate.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: August 21, 2012
    Assignee: HRL Laboratories, LLC
    Inventors: David T. Chang, Tsung-Yuan Hsu
  • Patent number: 8241510
    Abstract: A method for producing an inkjet recording head includes preparing the substrate having a through hole to be formed into a supply port, the through hole having openings on the first surface and the second surface, the substrate having a first protective layer disposed on the second surface, the first protective layer having an overhang extending into the region of the opening on the second surface. The method also includes forming a second protective layer so as to continuously cover at least the overhang of the first protective layer and the inner wall of the through hole, and removing a portion of the second protective layer corresponding to the opening on the first surface.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: August 14, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Makoto Sakurai
  • Patent number: 8236700
    Abstract: A method of pattern etching a Si-containing anti-reflective coating (ARC) layer is described. The method comprises etching a feature pattern into the silicon-containing ARC layer using plasma formed from a process gas containing SF6 and a hydrocarbon gas. The method further comprises adjusting a flow rate of the hydrocarbon gas relative to a flow rate of the SF6 to reduce a CD bias between a final CD for nested structures in the feature pattern and a final CD for isolated structures in the feature pattern.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: August 7, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Christopher Cole, Akiteru Ko
  • Patent number: 8231798
    Abstract: A tray for a dry etching apparatus includes substrate accommodation holes penetrating a thickness direction and a substrate support portion supporting an outer peripheral edge portion of a lower surface of a substrate. A dielectric plate includes a tray support surface supporting a lower surface of the tray, substrate placement portions inserted from a lower surface side of the tray into the substrate accommodation holes and having a substrate placement surface at its upper end surface. A dc voltage applying mechanism applies a dc voltage to an electrostatic attraction electrode. A heat conduction gas supply mechanism supplies a heat conduction gas between the substrate and substrate placement surface. The substrate is retained on the substrate placement surface with high degree of adhesion. Cooling efficiency of the substrate is improved and processing is uniform at the entire region of the substrate surface.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: July 31, 2012
    Assignee: Panasonic Corporation
    Inventors: Shogo Okita, Hiromi Asakura, Syouzou Watanabe, Ryuzou Houchin, Hiroyuki Suzuki
  • Patent number: 8231799
    Abstract: A plasma reactor for processing a workpiece such as a semiconductor wafer has a housing defining a process chamber, a workpiece support configured to support a workpiece within the chamber during processing and comprising a plasma bias power electrode. The reactor further includes plural gas sources containing different gas species, plural process gas inlets and an array of valves capable of coupling any of said plural gas sources to any of said plural process gas inlets. The reactor also includes a controller governing said array of valves and is programmed to change the flow rates of gases through said inlets over time. A ceiling plasma source power electrode of the reactor has plural gas injection zones coupled to the respective process gas inlets. In a preferred embodiment, the plural gas sources comprise supplies containing, respectively, fluorocarbon or fluorohydrocarbon species with respectively different ratios of carbon and fluorine chemistries.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: July 31, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Kallol Bera, Xiaoye Zhao, Kenny L. Doan, Ezra Robert Gold, Paul Lukas Brillhart, Bruno Geoffrion, Bryan Pu, Daniel J. Hoffman
  • Patent number: 8221635
    Abstract: A process for manufacturing a printed wiring board includes specifying overlapping etches for a first portion of the printed wiring board and a second portion of the printed wiring board, the first portion of the printed wiring board having disposed thereon a printed circuit having at least one dimension critical to printed wiring board operation, etching a first conductor in the first portion of the printed wiring board when a first conductor thickness is a predetermined thickness, completing all plating steps, and etching a second conductor in the second portion of the printed wiring board.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: July 17, 2012
    Assignee: Raytheon Company
    Inventor: John W. Hauff
  • Patent number: 8222143
    Abstract: A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 17, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Yan-Home Liu, Yung-Chieh Kuo, Yi-Ham Tsou, Jeng-Ho Wang, Cheng-Wei Chen, Hsin-Yi Lu
  • Patent number: 8221638
    Abstract: Prior to wafer processing, pressure ratio control is executed on a divided flow rate adjustment means so as to adjust the flow rates of divided flows to achieve a target pressure ratio with regard to the pressures in the individual branch passages. As the processing gas from a processing gas supply means is diverted into first and second branch pipings under the pressure ratio control and the pressures in the branch passages then stabilize, the control on the divided flow rate adjustment means is switched to steady pressure control for adjusting the flow rates of the divided flows so as to hold the pressure in the first branch passage at the level achieved in the stable pressure condition. Only after the control is switched to the steady pressure control, an additional gas is delivered into the second branch passage via an additional gas supply means.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: July 17, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Kenetsu Mizusawa
  • Patent number: 8221595
    Abstract: The invention provides a method for forming a patterned material layer on a structure, by condensing a vapor to a solid condensate layer on a surface of the structure and then localized removal of selected regions of the condensate layer by directing an ion beam at the selected regions, exposing the structure at the selected regions. A material layer is then deposited on top of the solid condensate layer and the exposed structure at the selected regions. Then the solid condensate layer and regions of the material layer that were deposited on the solid condensate layer are removed, leaving a patterned material layer on the structure.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: July 17, 2012
    Assignee: President and Fellows of Harvard College
    Inventors: Daniel Branton, Jene A Golovchenko, Gavin M King, Warren J MoberlyChan, Gregor M Schurmann
  • Publication number: 20120175343
    Abstract: An apparatus and method for etching a portion of a wafer include a mount for holding a wafer having an edge, a front surface, a back surface and an axis perpendicular to the front and back surfaces. A frame is used to deliver an etchant to the wafer edge while the wafer is held with the wafer edge at a distance from the frame. A nonreactive fluid flow may be provided and directed along the front and back surfaces of the wafer edge to drive the etchant away from the front and back surfaces. The frame can be configured either to deliver the etchant in liquid form or to deliver the etchant in vapor form. The frame can include a plenum for directing the etchant in vapor form to the wafer edge within a receiving area of the plenum, or the frame can include a roller having a groove for receiving the wafer edge and for drawing the etchant in liquid form to the wafer edge.
    Type: Application
    Filed: January 12, 2011
    Publication date: July 12, 2012
    Applicant: SILTRONIC CORPORATION
    Inventor: Randal Gieker
  • Patent number: 8216485
    Abstract: A plasma etching method etches an organic film formed on a target substrate by using a plasma of a processing gas via a silicon-containing mask. The processing gas is a gaseous mixture of an oxygen-containing gas, a rare gas and a carbon fluoride gas. A computer-executable control program controls a plasma etching apparatus to perform the plasma etching method. A computer-readable storage medium stores therein a computer-executable control program.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: July 10, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Yoshimitsu Kon, Yoshinobu Hayakawa
  • Patent number: 8216484
    Abstract: A method for fabricating a capacitor includes forming a first storage node (SN) oxide layer over a substrate, forming a second SN oxide layer over the first SN oxide layer, forming a mask pattern over the second SN oxide layer, dry-etching the first and the second SN oxide layers using the mask pattern as an etch barrier to form a capacitor region, and wet-etching a resultant structure including the capacitor region to enlarge a bottom width of the capacitor region, thereby forming a final capacitor region having the enlarged bottom width, wherein the first SN oxide layer comprises one portion of high impurity concentration and the other portion of low impurity concentration, the one portion corresponding to a region where the final capacitor region is to be formed.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: July 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jin-Ho Yang, Sang-Do Lee
  • Patent number: 8216434
    Abstract: A micromachined sensor for measuring vascular parameters, such as fluid shear stress, includes a substrate having a front-side surface, and a backside surface opposite the front-side surface. The sensor includes a diaphragm overlying a cavity etched within the substrate, and a heat sensing element disposed on the front-side surface of the substrate and on top of the cavity and the diaphragm. The heat sensing element is electrically couplable to electrode leads formed on the backside surface of the substrate. The sensor includes an electronic system connected to the backside surface and configured to measure a change in heat convection from the sensing element to surrounding fluid when the sensing element is heated by applying an electric current thereto, and further configured to derive from the change in heat convection vascular parameters such as the shear stress of fluid flowing past the sensing element.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: July 10, 2012
    Assignee: University of Southern California
    Inventors: Tzung K. Hsiai, Gopikrishnan Soundararajan, Eun Sok Kim, Hongyu Yu, Mahsa Rouhanizadeh, Christina Tiantian Lin
  • Publication number: 20120169320
    Abstract: A planar patch clamp device includes a substrate comprising a first planar surface, a second planar surface opposing the first planar surface, and an inside surface defining an aperture extending from the first planar surface to the second planar surface; and an adhesion layer conformally disposed on the substrate including on the inside surface, wherein the adhesion layer defines a shape of the aperture, and the aperture is smooth and free of sharp corners. The substrate may be composed of silicon or a silicon-inclusive compound, and the adhesion layer may be composed of a glass material having a low-temperature reflow property. The device may be annealed to reflow the adhesion layer, thereby providing the aperture with smooth surfaces.
    Type: Application
    Filed: December 15, 2011
    Publication date: July 5, 2012
    Applicant: MOLECULAR DEVICES, LLC
    Inventor: Yiching LIANG
  • Patent number: 8211323
    Abstract: The invention relates to a method for the one-sided removal of a doped surface layer on rear sides of crystalline silicon solar wafers. In accordance with the object set, doped surface layers should be able to be removed from rear sides of such solar wafers in a cost-effective manner and with a handling which is gentle on the substrate. In addition, the front side should not be modified. In accordance with the invention, an etching gas is directed onto the rear side surface of silicon solar wafers with a plasma atmospheric pressure.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: July 3, 2012
    Assignees: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V., Centrotherm Photovoltaics AG
    Inventors: Moritz Heintze, Rainer Moeller, Harald Wanka, Elena Lopez, Volkmar Hopfe, Ines Dani, Milan Rosina
  • Patent number: 8211805
    Abstract: The invention provides a method for forming a via. A first dielectric layer is formed on a substrate. A conductive structure is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and conductive structure. A first etching step is performed by using a first etching mixture to form a first via in the second dielectric layer. A second etching step is performed by using a second etching mixture to form a second via under the first via. The second via exposes at least a top surface of the conductive structure. An etching rate of the second etching step is slower than the first etching step.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: July 3, 2012
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Shun Lo, Hsing-Chao Liu
  • Publication number: 20120164389
    Abstract: Imprinted apparatuses, such as Bit-Patterned Media (BPM) templates, Discrete Track Recording (DTR) templates, semiconductors, and photonic devices are disclosed. Methods of fabricating imprinted apparatuses using a combination of patterning and block copolymer (BCP) self-assembly techniques are also disclosed.
    Type: Application
    Filed: December 28, 2010
    Publication date: June 28, 2012
    Inventors: XIAOMIN YANG, ZHAONING YU, KIM YANG LEE, MICHAEL FELDBAUM, YAUTZONG HSU, WEI HU, SHUAIGANG XIAO, HENRY YANG, HONGYING WANG, RENE JOHANNES MARINUS VAN DE VEERDONK, DAVID KUO
  • Publication number: 20120160805
    Abstract: A substrate processing method comprises: an execution step of executing the first processing for the plurality of substrates, and executing the second processing for the substrates having undergone the first processing; a recovery step of recovering the plurality of substrates having undergone the first processing and the second processing to the retraction chamber; a conditioning step of, after completion of the first processing for the last substrate among the plurality of substrates, loading a dummy substrate into the first processing chamber, executing the third processing for the dummy substrate, and unloading the dummy substrate from the first processing chamber; and a second execution step of, after the dummy substrate is unloaded from the first processing chamber in the conditioning step, loading the substrates recovered in the recovery step into the first processing chamber, and executing the third processing for the substrates loaded into the first processing chamber.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 28, 2012
    Applicant: CANON ANELVA CORPORATION
    Inventors: Kiyoshi Ehara, Mitsuo Suzuki