Gas Phase Etching Of Substrate Patents (Class 216/58)
  • Patent number: 8465596
    Abstract: Disclosed is a supercritical processing apparatus and a supercritical processing method for suppressing the pattern collapse or the injection of material constituting a processing liquid into a substrate. A processing chamber receives a substrate subjected to a processing with supercritical fluid, and a liquid supply unit supplies a processing liquid including a fluorine compound to the processing chamber. A liquid discharge unit discharges the supercritical fluid from the processing chamber, a pyrolysis ingredient removing unit removes an ingredient facilitating the pyrolysis of a liquid from the processing chamber or from the liquid supplied from the liquid supply unit, and a to heating unit heats the processing liquid including a fluorine compound of hydrofluoro ether or hydrofluoro carbon.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: June 18, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Takayuki Toshima, Mitsuaki Iwashita, Kazuyuki Mitsuoka, Hidekazu Okamoto, Hideo Namatsu
  • Patent number: 8465658
    Abstract: In a method of forming a main pole, an initial accommodation layer is etched by RIE using a first etching mask having a first opening, whereby a groove is formed in the initial accommodation layer. Next, a part of the initial accommodation layer including the groove is etched by RIE using a second etching mask having a second opening, so that the groove becomes an accommodation part. The main pole is then formed in the accommodation part. The first etching mask has first and second sidewalls that face the first opening and are opposed to each other at a first distance in a track width direction. The second etching mask has third and fourth sidewalls that face the second opening and are opposed to each other at a second distance greater than the first distance.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: June 18, 2013
    Assignee: Headway Technologies, Inc.
    Inventors: Hironori Araki, Yoshitaka Sasaki, Hiroyuki Ito, Kazuki Sato, Shigeki Tanemura, Yukinori Ikegawa
  • Patent number: 8460564
    Abstract: A drug-delivery chip and a method of fabricating the same are provided. The drug-delivery chip has a main body having at least one drug receiving space individually formed with an opening for storing drugs therein; a thin film for sealing up the at least one drug receiving space; a first conductive wire connecting to one end of the thin film; a second conductive wire connecting to another end of the thin film; a signal-receiving module for receiving actuated signals; and a control module for applying voltages to first and second wire conductive s according to the actuated signal, thereby generating heat to break off the thin film for the release of a drug or drugs received in the at least one drug receiving space.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: June 11, 2013
    Assignee: National Taiwan University
    Inventors: Shey-Shi Lu, Yao-Joe Yang, Yu-Jie Huang, Chii-Wann Lin, Hsin-Hung Liao, Tao Wang, Pen-Li Huang, Yao-Hong Wang
  • Publication number: 20130134128
    Abstract: A method and device for processing wafer-shaped articles comprises a closed process chamber. A rotary chuck is located within the process chamber, and is adapted to hold a wafer shaped article thereon. An interior fluid distribution ring is positioned above the rotary chuck, and comprises an annular surface inclined downwardly from a radially inner edge to a radially outer edge thereof. At least one fluid distribution nozzle extends into the closed process chamber and is positioned so as to discharge fluid onto the annular surface of the fluid distribution ring.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: LAM RESEARCH AG
    Inventors: Ulrich TSCHINDERLE, Andreas GLEISSNER, Michael BRUGGER
  • Patent number: 8449785
    Abstract: A substrate processing method is provided to process a substrate having a structure in which a lower photoresist layer, a hard mask layer containing silicon, and an upper photoresist layer are sequentially formed on a target layer to be processed. The substrate processing method includes reducing by using a plasma a width of a first opening formed in the upper photoresist layer, so that the hard mask layer is exposed; reducing by using a plasma a width of a second opening formed in the hard mask layer through the first opening having the reduced width so that the lower photoresist layer is exposed; forming a third opening through the second opening having the reduced width so that the target layer is exposed; and a third width reducing step of reducing a width of the third opening by using a plasma.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: May 28, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Takashi Kondo
  • Patent number: 8444868
    Abstract: The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tien-Jen Cheng, Stephan Grunow, Zhengwen Li, Huilong Zhu
  • Patent number: 8444870
    Abstract: A method and apparatus are provided for processing a substrate with a radiofrequency inductive plasma in the manufacture of a device. The inductive plasma is maintained with an inductive plasma applicator having one or more inductive coupling elements. There are thin windows between the inductive coupling elements and the interior of the processing chamber. Various embodiments have magnetic flux concentrators in the inductive coupling elements and feed gas holes interspersed among the inductive coupling elements. The thin windows, magnetic flux concentrators, and interspersed feed gas holes are useful to effectuate uniform processing, high power transfer efficiency, and a high degree of coupling between the applicator and plasma. In some embodiments, capacitive current is suppressed using balanced voltage to power an inductive coupling element.
    Type: Grant
    Filed: May 23, 2009
    Date of Patent: May 21, 2013
    Assignee: Mattson Technology, Inc.
    Inventor: Valery Godyak
  • Publication number: 20130111991
    Abstract: A gyro sensor according to the invention includes a driving portion that includes a driving support portion connected to a driving spring portion and a detecting portion that includes a detecting support portion connected to the driving support portion with the detecting spring portion interposed. The driving support portion is configured to vibrate in a first axis (X-axis) direction, and the detecting support portion is configured to be displaced in a second axis (Y-axis) direction orthogonal to the first axis (x-axis). When the resonant frequency of the driving portion is f1, the resonant frequency of the detecting portion is f2, the width of the driving spring portion is w1, and the width of the detecting spring portion is w2, Expression (1) below is satisfied. 0.87(f2/f1)?(w2/w1)?1.
    Type: Application
    Filed: October 24, 2012
    Publication date: May 9, 2013
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Seiko Epson Corporation
  • Patent number: 8435895
    Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: May 7, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: David Chen, Haruhiro Harry Goto, Martina Martina, Frank Greer, Shamsuddin Alokozai
  • Patent number: 8435415
    Abstract: A nanofabrication process for use with a photoresist that is disposed on a substrate includes the steps of exposing the photoresist to a grayscale radiation pattern, developing the photoresist to remove a irradiated portions and form a patterned topography having a plurality of nanoscale critical dimensions, and selectively etching the photoresist and the substrate to transfer a corresponding topography having a plurality of nanoscale critical dimensions into the substrate.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: May 7, 2013
    Assignees: The United States of America, as represented by the Secretary of Commerce, the National Institute of Standards and Technology, Cornell University—Cornell Center for Technology, Enterprise & Commercialization
    Inventors: Samuel Martin Stavis, Elizabeth Arlene Strychalski, Michael Gaitan
  • Patent number: 8435414
    Abstract: A nozzle plate manufacturing method that offers excellent protection against discharge liquid, and that enables a nozzle plate having high nozzle-hole accuracy to be manufactured with good yield. The invention also provides a nozzle plate, a droplet discharge head manufacturing method, and a droplet discharge head.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: May 7, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Junichi Takeuchi
  • Publication number: 20130104362
    Abstract: The present invention provides an apparatus comprising a substrate and first and second disks. The disks are rotatably located over the substrate, each disk having an outer circumference with teeth thereon. The first disk is positioned to interleave one or more of its teeth with the teeth of the second disk. The substrate includes a channel with an exit port located near the teeth of one of the disks. Another apparatus comprises at least one disk rotatably located over a substrate and in a well of the substrate, the disk having an outer circumference with teeth thereon. The disk is positioned to provide a maximum distance of less than about 10 microns between each one the teeth and a nearest wall defining the well. The substrate includes a channel with an exit port located near the teeth of the disk.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 2, 2013
    Applicant: LUCENT TECHNOLOGIES INC.
    Inventor: Lucent Technologies Inc.
  • Patent number: 8425789
    Abstract: In anisotropic etching of the substrates, ultra-thin and conformable layers of materials can be used to passivate sidewalls of the etched features. Such a sidewall passivation layer may be a Self-assembled monolayer (SAM) material deposited in-situ etching process from a vapor phase. Alternatively, the sidewall passivation layer may be an inorganic-based material deposited using Atomic Layer Deposition (ALD) method. SAM or ALD s layer deposition can be carried out in a pulsing regime alternating with sputtering and/or etching processes using process gasses with or without plasma. Alternatively, SAM deposition is carried out continuously, while etch or sputtering turns on in a pulsing regime. Alternatively, SAM deposition and etch or sputtering may be carried out continuously.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: April 23, 2013
    Assignee: Rolith, Inc.
    Inventor: Boris Kobrin
  • Patent number: 8425982
    Abstract: Methods for fabricating arrays of nanoscaled alternating lamellar or cylinders in a polymer matrix having improved long range order utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: April 23, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Jennifer Kahl Regner
  • Patent number: 8425972
    Abstract: An antimicrobial material is provided for use in forming textiles, medical devices, packaging materials, and the like, or coatings thereon. In some embodiments, the antimicrobial material may be utilized for bulk modification of an article. The antimicrobial material includes a furanone possessing vinyl and/or acrylate functional groups, optionally in combination with another monomer possessing vinyl and/or acrylate groups.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: April 23, 2013
    Assignee: Covidien LP
    Inventor: Joshua B. Stopek
  • Patent number: 8426316
    Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: John Michael Cotte, Nils Deneke Hoivik, Christopher Vincent Jahnes, Robert Luke Wisnieff
  • Publication number: 20130095574
    Abstract: Silicon microcarriers suitable for fluorescent assays as a well as a method of producing such microcarriers are provided. The method includes the steps of providing a SOI wafer having a bottom layer of monocristalline silicone, an insulator layer and a bottom layer of monocristalline silicon, delineating microparticles, etching away the insulator layer and then depositing an oxide layer on the wafer still holding the microparticles before finally lifting-off the microparticles.
    Type: Application
    Filed: April 13, 2012
    Publication date: April 18, 2013
    Applicant: BIOCARTIS SA
    Inventors: Nicolas DEMIERRE, Stephan GAMPER
  • Patent number: 8420547
    Abstract: A plasma processing method performed in a plasma processing apparatus including a processing chamber accommodating a substrate in which a plasma is generated; a mounting table mounting the substrate, which is provided in the processing chamber and to which a plasma attraction high frequency voltage is applied; and a facing electrode provided to face the mounting table in the processing chamber, to which a negative DC voltage is applied, the method including: applying a plasma attraction high frequency voltage to the mounting table for a predetermined period of time; and stopping the application of the plasma attraction high frequency voltage to the mounting table. In the plasma processing method, the application of the plasma attraction high frequency voltage and stopping thereof are alternately repeated.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: April 16, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Yoshinobu Ooya
  • Patent number: 8419952
    Abstract: According to one embodiment, a method of manufacturing a patterned medium includes forming an implantation depth-adjusting layer above a magnetic recording layer, the magnetic recording layer being made of a material that is deactivated when implanted with a chemical species, and the implantation depth-adjusting layer being made of a material that is etched when irradiated with an ion beam of the chemical species and irradiating the implantation depth-adjusting layer with the ion beam to implant the chemical species into a part of the magnetic recording layer through the implantation depth-adjusting layer while etching the implantation depth-adjusting layer by an action of the ion beam to decrease a thickness of the implantation depth-adjusting layer.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Sakurai, Kaori Kimura, Hiroyuki Hyodo, Takeshi Iwasaki
  • Patent number: 8404600
    Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej Sandhu
  • Patent number: 8404135
    Abstract: A method for cleaning and refurbishing a chamber component includes placing a chamber component having process deposits on an exterior surface in a plasma vapor deposition chamber. The chamber component is bombarded with a plasma comprising Argon for a period of time sufficient to remove the process deposits from the exterior surface of the chamber component.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Bin Chiou, Wen-Cheng Cheng, Wen-Sheng Wu
  • Patent number: 8404136
    Abstract: There is provided a method for manufacturing a diffractive optical element that can suppress the generation of heat from the inside of an insulative substrate and stabilize an etching rate. A method for manufacturing a diffractive optical element composed of an insulative substrate whose surface has a bumpy structure includes a selecting step of selecting an insulative substrate having an electrical resistivity equal to or higher than a certain value by measuring electrical resistivity of insulative substrates; and an etching step of forming a bumpy structure by dry etching in a surface of the insulative substrate selected in the selecting step.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: March 26, 2013
    Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Hardmetal Corp.
    Inventors: Kenichi Kurisu, Hideaki Imamura
  • Patent number: 8404595
    Abstract: A plasma processing method for processing a target substrate uses a plasma processing apparatus which includes a vacuum evacuable processing vessel for accommodating the target substrate therein, a first electrode disposed in the processing vessel and connected to a first RF power supply for plasma generation and a second electrode disposed to face the first electrode. The method includes exciting a processing gas containing fluorocarbon in the processing vessel to generate a plasma while applying a negative DC voltage having an absolute value ranging from about 100 V to 1500 V or an RF power of a frequency lower than about 4 MHz to the second electrode. The target layer is etched by the plasma, thus forming recesses on the etching target layer based on the pattern of the resist layer.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: March 26, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Masanobu Honda, Manabu Sato, Yoshiki Igarashi
  • Patent number: 8398872
    Abstract: A novel method of forming large atomically flat areas is described in which a crystalline substrate having a stepped surface is exposed to a vapor of another material to deposit a material onto the substrate, which material under appropriate conditions self arranges to form 3D islands across the substrate surface. These islands are atomically flat at their top surface, and conform to the stepped surface of the substrate below at the island-substrate interface. Thereafter, the deposited materials are etched away, in the etch process the atomically flat surface areas of the islands transferred to the underlying substrate. Thereafter the substrate may be cleaned and annealed to remove any remaining unwanted contaminants, and eliminate any residual defects that may have remained in the substrate surface as a result of pre-existing imperfections of the substrate.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: March 19, 2013
    Assignee: The Regents of the University of California
    Inventors: Farid El Gabaly, Andreas K. Schmid
  • Patent number: 8398876
    Abstract: A method for chemical modification of graphene includes dry etching graphene to provide an etched graphene; and introducing a functional group at an edge of the etched graphene. Also disclosed is graphene, including an etched edge portion, the etched portion including a functional group.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: March 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Mook Choi, Byung Hee Hong, Jaeyoung Choi
  • Patent number: 8398875
    Abstract: Methods for orienting an upper electrode relative to a lower electrode are provided. The lower electrode is configured to have a desired existing orientation in a process chamber to define active and inactive process zones in the process chamber for processing a wafer. The method includes configuring each electrode with a reference surface, where a lower electrode reference surface is in the desired existing orientation and an upper electrode reference surface to be oriented parallel to the lower electrode reference surface. Then, temporarily holding the upper electrode reference surface oriented parallel to the lower electrode reference surface, and securing the upper electrode to a drive to mount the upper electrode reference surface parallel to the lower electrode reference surface. Other method configurations are also disclosed and illustrated.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: March 19, 2013
    Assignee: Lam Research Corporation
    Inventors: Gregory S. Sexton, Andrew D. Bailey, III, Alan M. Schoepp, John D. Boniface
  • Patent number: 8388853
    Abstract: Embodiments of the present invention provide apparatus and methods for supporting, positioning or rotating a semiconductor substrate during processing. One embodiment of the present invention provides a method for processing a substrate comprising positioning the substrate on a substrate receiving surface of a susceptor, and rotating the susceptor and the substrate by delivering flow of fluid from one or more rotating ports.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: March 5, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Blake Koelmel, Nyi O. Myo
  • Patent number: 8382999
    Abstract: Radial distribution of etch rate is controlled by controlling the respective duty cycles of pulsed VHF source power applied to the ceiling and pulsed HF or MF bias power on the workpiece. Net average electrical charging of the workpiece is controlled by providing an electronegative process gas and controlling the voltage of a positive DC pulse on the workpiece applied during pulse off times of the pulsed VHF source power.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: February 26, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Ankur Agarwal, Kenneth S. Collins, Shahid Rauf, Kartik Ramaswamy, Thorsten B. Lill
  • Patent number: 8377829
    Abstract: A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: February 19, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Ta-Chuan Yeh, Ni-Min Chung, Kao-Su Huang, Yung-Chang Lin, Ruey-Chyr Lee, Chien-Kuo Wang
  • Patent number: 8377319
    Abstract: Techniques are provided for forming nozzles in a microelectromechanical device. The nozzles are formed in a layer prior to the layer being bonded onto another portion of the device. Forming the nozzles in the layer prior to bonding enables forming nozzles that have a desired depth and a desired geometry. Selecting a particular geometry for the nozzles can reduce the resistance to ink flow as well as improve the uniformity of the nozzles across the microelectromechanical device.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: February 19, 2013
    Assignee: FUJIFILM Dimatix, Inc.
    Inventors: Zhenfang Chen, Andreas Bibl, Paul A. Hoisington
  • Patent number: 8377321
    Abstract: A method of forming a nozzle and an ink chamber of an ink jet device, includes forming a nozzle passage by subjecting a substrate to a directional first etch process from one side of the substrate; applying a second etch process from the same side of the substrate for widening an internal part of the nozzle passage, to form a cavity forming at least a portion of the ink chamber adjacent to the nozzle; and controlling the shape of the cavity by providing, on the opposite side of the substrate, an etch accelerating layer buried under an etch stop layer and by allowing the second etch process to proceed into the etch accelerating layer. The following steps precede the first etch process: forming an annular trench in the substrate on the side of the substrate where the nozzle is to be formed; and passivating the walls of the trench so as to become resistant against the second etch process. The material surrounded by the trench is removed in the first etch process.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: February 19, 2013
    Assignee: Oce Technologies B.V.
    Inventors: Henricus Johannes Adrianus Van De Sande, Willem Maurits Hijmans, Gerardus Johannes Burger, Dionysius Antionius Petrus Oudejans
  • Patent number: 8372295
    Abstract: Methods for fabricating sublithographic, nanoscale arrays of openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Embodiments of the invention use a self-templating or multilayer approach to induce ordering of a self-assembling block copolymer film to an underlying base film to produce a multilayered film having an ordered array of nanostructures that can be removed to provide openings in the film which, in some embodiments, can be used as a template or mask to etch openings in an underlying material layer.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Patent number: 8366944
    Abstract: A method of fabricating an image drum includes preparing a hollow drum body having a slot extending in a longitudinal direction, preparing a printed circuit board (PCB) having a plurality of board terminals, mounting the PCB inside the hollow drum body with a fixing member such that the board terminals of the PCB are placed in the slot of the hollow drum body, coating a first insulating layer on an outer circumference of the hollow drum body, forming a plurality of ring electrodes on the first insulating layer corresponding to the board terminals of the PCB, in which a portion of ring electrodes which corresponds to the board terminals of the PCB is non-continuous, exposing the board terminals below non-continuous area of the ring electrodes by etching the first insulating layer with the ring electrodes as an etching mask, and forming a connecting electrode to electrically connect the board terminals to the ring electrodes.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: February 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seung Choi, Eung-yeoul Yoon, Kyu-ho Shin
  • Publication number: 20130026135
    Abstract: Provided is an apparatus, system and method for treating a substrate, and more particularly, a substrate treating apparatus having a cluster structure, a substrate treating system, and a substrate treating method using the substrate treating system. The substrate treating apparatus includes a load port on which a container containing a substrate is installed, a plurality of process modules treating the substrate, a transfer module disposed between the load port and the process modules, and transferring the substrate between the container and the process modules, and a buffer chamber disposed between neighboring ones of the process modules, and providing a space for carrying the substrate between the neighboring process modules.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 31, 2013
    Applicant: SEMES CO., LTD.
    Inventor: Hyung Joon KIM
  • Patent number: 8361338
    Abstract: The embodiments of methods described in this disclosure for removing a hard mask layer(s) over a polysilicon layer of a gate stack after the gate stack is etched allows the complete removal of the hard mask layer without the assistance of photolithography. A dielectric material is deposited over the substrate with the gate stacks. The topography of the substrate is removed by chemical mechanical polishing first. Afterwards, an etching gas (or vapor) is used to etch a portion of the remaining dielectric layer and the hard mask layer. The etching gas forms an etch byproduct that deposits on the substrate surface and can be subsequently removed by heating. The etching and heating to remove etch byproduct are repeated until the hard mask layer is completed removed. Afterwards, the remaining dielectric layer is removed by wet etch. The methods described are simpler and cheaper to use than conventional methods for hard mask removal.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shiang-Bau Wang
  • Patent number: 8361339
    Abstract: The present invention provides such a formation method that an antireflection structure having excellent antireflection functions can be formed in a large area and at small cost. Further, the present invention also provides an antireflection structure formed by that method. In the formation method, a base layer and particles placed thereon are subjected to an etching process. The particles on the base layer serve as an etching mask in the process, and hence they are more durable against etching than the base layer. The etching rate ratio of the base layer to the particles is more than 1 but not more than 5. The etching process is stopped before the particles disappear. It is also possible to produce an antireflection structure by nanoimprinting method employing a stamper. The stamper is formed by use of a master plate produced according to the above formation method.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: January 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Nakanishi, Akira Fujimoto, Koji Asakawa, Takeshi Okino, Shinobu Sugimura
  • Patent number: 8361275
    Abstract: When a substrate is etched by using a processing gas including a first gas containing halogen and carbon and having a carbon number of two or less per molecule, while supplying the processing gas toward the substrate independently from a central and a peripheral portion of a gas supply unit, which face the central and the periphery part of the substrate respectively, the processing gas is supplied such that a gas flow rate is greater in the central portion than in the peripheral portion. When the substrate is etched by using a processing gas including a second gas containing halogen and carbon and having a carbon number of three or more per molecule, the processing gas is supplied such that a gas flow rate is greater in the peripheral portion than in the central portion.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: January 29, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Shigeru Tahara, Masaru Nishino
  • Patent number: 8361331
    Abstract: A MEMS mirror for a laser printing application includes providing a CMOS substrate including a pair of electrodes, and providing a reflecting mirror moveable over the substrate and the electrodes. Voltages applied to the electrodes create an electrostatic force causing an end of the mirror to be attracted to the substrate. A precise position of the mirror can be detected and controlled by sensing a change in capacitance between the mirror ends and the underlying electrodes.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: January 29, 2013
    Assignee: Miradia Inc.
    Inventors: Xiao Yang, William Spencer Worley, III, Dongmin Chen, Ye Wang
  • Patent number: 8357615
    Abstract: The present invention is an apparatus for manufacturing a semiconductor device comprising: a process vessel including a stage on which a substrate is placed, the substrate having a low dielectric constant film with a resist pattern being formed in an upper layer of the low dielectric constant film; an etching-gas supply unit that supplies an etching gas into the process vessel so as to etch the low dielectric constant film; an ashing-gas unit means that supplies an ashing gas into the process vessel so as to ash the resist pattern formed in the upper layer of the low dielectric constant film after the low dielectric constant film has been subjected to an etching process; a plasma generating means that generates a plasma by supplying an energy to the etching gas and the ashing gas in the process vessel; a unit that supplies a dipivaloylmethane gas into the process vessel, after the low dielectric constant film has been subjected to an ashing process, in order to recover a damage layer of the low dielectric con
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: January 22, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Yuki Chiba, Eiichi Nishimura, Ryuichi Asako
  • Publication number: 20130015158
    Abstract: The present invention provides a dry etching method capable of readily providing rounded top edge portions, called top rounds, at trenches and vias formed by removal of a dummy material. The method of the present invention is a dry etching method for forming trenches or vias by removing a dummy material with its periphery surrounded by an interlayer oxide film, which method includes the steps of etching the dummy material to a predetermined depth, performing isotropic etching after the dummy material etching, and removing remaining part of the dummy material after the isotropic etching.
    Type: Application
    Filed: August 16, 2011
    Publication date: January 17, 2013
    Inventors: Tomoyoshi Ichimaru, Kenichi Kuwabara, Go Saito
  • Patent number: 8349195
    Abstract: A method and system provide a magnetoresistive structure from a magnetoresistive stack that includes a plurality of layers. The method and system include providing a mask that exposes a portion of the magnetoresistive stack. The mask has at least one side, a top, and a base at least as wide as the top. The method and system also include removing the portion of the magnetoresistive stack to define the magnetoresistive structure. The method and system further include providing an insulating layer. A portion of the insulating layer resides on the at least one side of the mask. The method and system further include removing the portion of the insulating layer on the at least one side of the mask and removing the mask.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: January 8, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Weimin Si, Liubo Hong, Honglin Zhu, Winnie Yu, Rowena Schmidt
  • Patent number: 8349083
    Abstract: A vapor-phase process apparatus and a vapor-phase process method capable of satisfactorily maintaining quality of processes even when different types of processes are performed are obtained. A vapor-phase process apparatus includes a process chamber, gas supply ports serving as a plurality of gas introduction portions, and a gas supply portion (a gas supply member, a pipe, a flow rate control device, a pipe, and a buffer chamber). The process chamber allows flow of a reaction gas therein. The plurality of gas supply ports are formed in a wall surface (upper wall) of the process chamber along a direction of flow of the reaction gas. The gas supply portion can supply a gas into the process chamber at a different flow rate from each of one gas supply port and another gas supply port different from that one gas supply port among the plurality of gas supply ports.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: January 8, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Eiryo Takasuka, Toshio Ueda, Toshiyuki Kuramoto, Masaki Ueno
  • Patent number: 8349199
    Abstract: An ink feedhole of an inkjet printhead and a method of forming the same includes an ink feedhole that penetrates a substrate and has a width that narrows in an upper direction of the substrate, wherein at least one internal wall of the ink feedhole has a plurality of steps and inclines with respect to a surface of the substrate.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: January 8, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Yong-won Jeong, Yong-seop Yoon, Moon-chul Lee, Dong-sik Shim, Jong-seok Kim
  • Patent number: 8349403
    Abstract: A vapor-phase process apparatus and a vapor-phase process method capable of satisfactorily maintaining quality of processes even when different types of processes are performed are obtained. A vapor-phase process apparatus includes a process chamber, gas supply ports serving as a plurality of gas introduction portions, and a gas supply portion (a gas supply member, a pipe, a flow rate control device, a pipe, and a buffer chamber). The process chamber allows flow of a reaction gas therein. The plurality of gas supply ports are formed in a wall surface (upper wall) of the process chamber along a direction of flow of the reaction gas. The gas supply portion can supply a gas into the process chamber at a different flow rate from each of one gas supply port and another gas supply port different from that one gas supply port among the plurality of gas supply ports.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: January 8, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Eiryo Takasuka, Toshio Ueda, Toshiyuki Kuramoto, Masaki Ueno
  • Patent number: 8349201
    Abstract: A method of processing a SOI substrate to form a groove in the SOI substrate in which a silicon layer is stacked on both sides of an oxide layer is disclosed. In accordance with an embodiment of the present invention, the method includes dividing a portion of the silicon layer, in which the groove is to be processed, into a plurality of unit portions, performing dry etching on certain portions of the plurality of divided unit portions such that the oxide layer is exposed and removing remaining portions of the plurality of divided unit portions by removing the oxide layer.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: January 8, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chung-Mo Yang, Jae-Woo Joung, Young-Seuck Yoo
  • Publication number: 20130001194
    Abstract: Provided is a substrate treating apparatus, which includes a process chamber providing a space in which a substrate is treated, an exhausting pipe connected to the process chamber, and providing a passage through which gas is discharged from the process chamber to an outside thereof, a pump installed on the exhausting pipe, and a valve installed on the exhausting pipe between the process chamber and the pump, and opening and closing the passage. The valve includes a first plate provided with exhausting holes, and a first driver moving the first plate such that the exhausting holes are located within the passage or outside the passage.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 3, 2013
    Inventor: Jaemin Roh
  • Publication number: 20130004763
    Abstract: The embodiments disclose a method of fabricating a stack, including replacing a metal layer of a stack imprint structure with an oxide layer, patterning the oxide layer stack using chemical etch processes to transfer the pattern image and cleaning etch residue from the stack imprint structure to substantially prevent contamination of the metal layers.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: SEAGATE TECHNOLOGY, LLC
    Inventors: Michael R. Feldbaum, Justin Jia-Jen Hwu, David S. Kuo, Gennady Gauzner, Kim Yang Lee, Li-Ping Wang
  • Patent number: 8343365
    Abstract: The invention provides a color filter producing method that is based on dry etching and makes it possible to produce a color filter which has fine and rectangular pixels and is excellent in flatness, and color filters produced by the method. The method is a color filter producing method of forming a first colorant-containing layer on a support, removing the first colorant-containing layer corresponding to a region where a second colorant-containing layer is to be formed by dry etching, forming the second colorant-containing layer so as to be embedded into the layer-removed region, removing the first and second colorant-containing layers corresponding to a region where a third colorant-containing layer is to be formed by dry etching, forming the third colorant-containing layer so as to be embedded into the layer-removed region, and removing the colorant-containing layers laminated on other colorant-containing layers.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: January 1, 2013
    Assignee: FUJIFILM Corporation
    Inventor: Mitsuji Yoshibayashi
  • Publication number: 20120325772
    Abstract: An ink-jet recording head includes a plurality of recording element substrates each having an ejection pressure generating element configured to generate pressure for ejecting ink from an ink discharge port. The plurality of recording element substrates each include a first surface on which the corresponding ejection pressure generating element is disposed and a second surface, serving as an end surface intersecting with the first surface, being at least partially formed by etching.
    Type: Application
    Filed: September 5, 2012
    Publication date: December 27, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Hirotaka Miyazaki
  • Patent number: 8329593
    Abstract: Polymer is removed from the backside of a wafer held on a support pedestal in a reactor using an arcuate side gas injection nozzle extending through the reactor side wall with a curvature matched to the wafer edge and supplied with plasma by-products from a remote plasma source.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: December 11, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Imad Yousif, Anchel Sheyner, Ajit Balakrishna, Nancy Fung, Ying Rui, Martin Jeffrey Salinas, Walter R. Merry, Shahid Rauf