Superlattice Patents (Class 257/15)
  • Patent number: 7906775
    Abstract: Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: March 15, 2011
    Assignee: California Institute of Technology
    Inventors: James R. Heath, Pierre M. Petroff, Nicholas A. Melosh
  • Patent number: 7903707
    Abstract: A nitride semiconductor light-emitting device wherein a substrate or nitride semiconductor layer has a defect concentration region and a low defect density region other than the defect concentration region. A portion including the defect concentration region of the nitride semiconductor layer or substrate has a trench region deeper than the low defect density region. Thus by digging the trench in the defect concentration region, the growth detection is uniformized, and the surface planarity is improved. The uniformity of the characteristic in the wafer surface leads to improvement of the yield.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: March 8, 2011
    Assignees: Sharp Kabushiki Kaisha, Sumitomo Electric Industries, Ltd.
    Inventors: Takeshi Kamikawa, Yoshika Kaneko, Kensaku Motoki
  • Patent number: 7902561
    Abstract: The present invention relates to a nitride semiconductor light emitting device including: a first nitride semiconductor layer having a super lattice structure of AlGaN/n-GaN or AlGaN/GaN/n-GaN; an active layer formed on the first nitride semiconductor layer to emit light; a second nitride semiconductor layer formed on the active layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. According to the present invention, the crystallinity of the active layer is enhanced, and optical power and reliability are also enhanced.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: March 8, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee
  • Patent number: 7903708
    Abstract: A nitride semiconductor laser device uses a substrate with low defect density, contains reduced strains inside a nitride semiconductor film, and thus offers a satisfactorily long useful life. On a GaN substrate (10) with a defect density as low as 106 cm?2 or less, a stripe-shaped depressed portion (16) is formed by etching. On this substrate (10), a nitride semiconductor film (11) is grown, and a laser stripe (12) is formed off the area right above the depressed portion (16). With this structure, the laser stripe (12) is free from strains, and the semiconductor laser device offers a long useful life. Moreover, the nitride semiconductor film (11) develops reduced cracks, resulting in a greatly increased yield rate.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: March 8, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Kamikawa, Eiji Yamada, Masahiro Araki, Yoshika Kaneko
  • Patent number: 7884351
    Abstract: In a nitride semiconductor light-emitting device (11), an emission region (17) has a quantum well structure (19), and lies between an n-type gallium nitride semiconductor region (13) and a p-type gallium nitride semiconductor region (15). The quantum well structure (19) includes a plurality of first well layers (21) composed of InxGa1-xN, one or a plurality of second well layers (23) composed of InyGa1-yN, and barrier layers (25). The first and second well layers (21) and (23) are arranged in alternation with the barrier layers (25). The second well layers (23) lie between the first well layers (21) and the p-type gallium nitride semiconductor region (15). The indium component y of the second well layers (23) is smaller than indium component x of the first well layers (21), and the thickness DW2 of the second well layers (23) is greater than the thickness DW1 of the first well layers (21).
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: February 8, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Katsushi Akita, Yusuke Yoshizumi
  • Patent number: 7884352
    Abstract: The invention relates to a single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: February 8, 2011
    Assignees: STMicroelectronics S.A., STMicroelectronics Crolles 2 SAS
    Inventors: Daniel Bensahel, Yves Campidelli, Oliver Kermarrec
  • Patent number: 7872253
    Abstract: A thermoelectric conversion material includes a superlattice structure produced by laminating a barrier layer containing insulating SrTiO3, and a quantum well layer containing SrTiO3 which has been converted into a semiconductor by doping an n-type impurity therein. The quantum well layer has a thickness 4 times or less the unit lattice thickness of SrTiO3 which has been converted into a semiconductor by doping an n-type impurity therein.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: January 18, 2011
    Assignee: National University Corporation Nagoya University
    Inventors: Hiromichi Ohta, Kunihito Koumoto, Yoriko Mune
  • Publication number: 20110006285
    Abstract: The invention relates to a core-alloyed shell semiconductor nanocrystal comprising: (i) a core of a semiconductor material having a selected band gap energy; (ii) a core-overcoating shell consisting of one or more layers comprised of an alloy of the said semiconductor of (i) and a second semiconductor; (iii) and an outer organic ligand layer, provided that the core semiconductor material is not HgTe. In certain embodiments, the core semiconductor material is PbSe and the alloy shell semiconductor material has the PbSexS1-x structure; or the core semiconductor material is CdTe and the alloy shell semiconductor material has either the CdTexSe1-x or CdTexS1-x structure.
    Type: Application
    Filed: May 14, 2010
    Publication date: January 13, 2011
    Applicant: Technion Research & Development Foundation Ltd.
    Inventors: Efrat LIFSHITZ, Ariel Kigel, Maya Brumer-Gilary, Aldona Sashchiuk, Lilac Amirav, Viktoria Kloper, Dima Cheskis, Ruth Osovsky
  • Patent number: 7868316
    Abstract: There is provided a nitride semiconductor device.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: January 11, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Suk Ho Yoon, Ki Ho Park, Joong Kon Son
  • Publication number: 20100308303
    Abstract: A method of making a quantum dot memory cell, the quantum dot memory cell including an array of quantum dots disposed between a first electrode and a second electrode, includes obtaining values for a tunneling current through the quantum dot memory cell as a function of a voltage applied to the quantum dot memory cell and selecting parameters of the quantum dot memory cell such that the tunneling current through the quantum dot memory cell exhibits a bistable current for at least some values of the voltage applied to the quantum dot memory cell. The values for the tunneling current are determined on the basis of a density of states of the array of quantum dots.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 9, 2010
    Applicant: Academia Sinica
    Inventors: Yia-Chung Chang, David M.T. Kuo
  • Patent number: 7842531
    Abstract: A gallium nitride-based device has a first GaN layer and a type II quantum well active region over the GaN layer. The type II quantum well active region comprises at least one InGaN layer and at least one GaNAs layer comprising 1.5 to 8% As concentration. The type II quantum well emits in the 400 to 700 nm region with reduced polarization affect.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: November 30, 2010
    Assignee: Lehigh University
    Inventors: Nelson Tansu, Ronald A. Arif, Yik Khoon Ee
  • Publication number: 20100289004
    Abstract: Provided are a ZnO-based thin film and a ZnO-based semiconductor device which allow: reduction in a burden on a manufacturing apparatus; improvement of controllability and reproducibility of doping; and obtaining p-type conduction without changing a crystalline structure. In order to be formed into a p-type ZnO-based thin film, a ZnO-based thin film is formed by employing as a basic structure a superlattice structure of a MgZnO/ZnO super lattice layer 3. This superlattice component is formed with a laminated structure which includes acceptor-doped MgZnO layers 3b and acceptor-doped ZnO layers 3a. Hence, it is possible to improve controllability and reproducibility of the doping, and to prevent a change in a crystalline structure due to a doping material.
    Type: Application
    Filed: June 13, 2008
    Publication date: November 18, 2010
    Applicant: ROHM CO., LTD.
    Inventors: Ken Nakahara, Shunsuke Akasaka, Masashi Kawasaki, Akira Ohtomo, Atsushi Tsukazaki
  • Publication number: 20100276664
    Abstract: Various embodiments provide thin-walled structures and methodologies for their formation. In one embodiment, the thin-walled structure can be formed by disposing a semiconductor material in a patterned aperture using a selective growth mask that includes a plurality of patterned apertures, followed by a continuous growth of the semiconductor material using a pulsed growth mode. The patterned aperture can include at least one lateral dimension that is small enough to allow a threading defect termination at sidewall(s) of the formed thin-walled structure. In addition, high-quality III-N substrate structures and core-shell MQW active structures can be formed from the thin-walled structures for use in devices like light emitting diodes (LEDs), lasers, or high electron mobility transistors (HEMTs).
    Type: Application
    Filed: September 25, 2008
    Publication date: November 4, 2010
    Inventor: Stephen D. Hersee
  • Publication number: 20100276665
    Abstract: A method of producing a layered semiconductor device comprises the steps of: (a) providing a base comprising a plurality of semiconductor nano-structures, (b) growing a semiconductor material onto the nano-structures using an epitaxial 5 growth process, and (c) growing a layer of the semiconductor material using an epitaxial growth process.
    Type: Application
    Filed: January 31, 2008
    Publication date: November 4, 2010
    Inventor: Wang Nang Wang
  • Publication number: 20100276666
    Abstract: The present disclosure generally relates to techniques for controlled quantum dot growth as well as a quantum dot structures. In some examples, a method is described that includes one or more of providing a substrate, forming a defect on the substrate, depositing a layer on the substrate and forming quantum dots along the defect.
    Type: Application
    Filed: May 4, 2009
    Publication date: November 4, 2010
    Inventor: Ezekiel Kruglick
  • Patent number: 7821807
    Abstract: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. An extraction region is disposed on a first side of the active region and extracts minority carriers from the active region. It also has majority carriers within the extraction region flowing toward the active region in a condition of reverse bias. An exclusion region is disposed on a second side of the active region and has minority carriers within the exclusion region flowing toward the active region. It receives majority carriers from the active region. At least one of the extraction and exclusion region provides a barrier for substantially reducing flow of one of the majority carriers or the minority carriers, whichever is flowing toward the active region, while permitting flow of the other minority carriers or majority carriers flowing out of the active region.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: October 26, 2010
    Assignee: EPIR Technologies, Inc.
    Inventors: Silviu Velicu, Christoph H. Grein, Sivalingam Sivananthan
  • Publication number: 20100258785
    Abstract: Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate.
    Type: Application
    Filed: December 4, 2006
    Publication date: October 14, 2010
    Applicant: California Institute of Technology
    Inventors: James R. Heath, Pierre M. Petroff, Nicholas A. Melosh
  • Patent number: 7812339
    Abstract: A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: October 12, 2010
    Assignee: Mears Technologies, Inc.
    Inventors: Robert J. Mears, Kalipatnam Vivek Rao
  • Publication number: 20100245987
    Abstract: It is desirable to provide a semiconductor optical amplifier from which it becomes able to obtain a higher output power. A semiconductor optical amplifier in comprises an active wave guiding layer which comprises a passive core region that is formed of a semiconductor, and active cladding regions that are located at both sides of the passive core region and each of that is comprised of an active layer which is formed of a semiconductor and which has an index of refraction to be lower than that of the passive core region, wherein a light is wave guided with being amplified in the active wave guiding layer. Moreover, it is desirable for the active wave guiding layer to be formed of a compound semiconductor, and to be formed by integrating the passive core region and the active cladding regions to be monolithic on to a substrate that is formed of a compound semiconductor by making use of a process of a butt joint growth.
    Type: Application
    Filed: February 18, 2010
    Publication date: September 30, 2010
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Hideaki Hasegawa, Masaki Funabashi, Noriyuki Yokouchi, Junji Yoshida
  • Publication number: 20100230656
    Abstract: A semiconductor structure having an electrically conducting silicon substrate and a GaN semiconductor device separated from the substrate by a buffer layer is provided. The buffer layer electrically connects the silicon substrate with the GaN semiconductor device. In addition, a GaN LED arranged in a flip chip orientation on the buffer layer on the substrate is provided.
    Type: Application
    Filed: February 15, 2010
    Publication date: September 16, 2010
    Applicant: RFMD (UK) LIMITED
    Inventor: Matthew F. O'Keefe
  • Patent number: 7795609
    Abstract: Embodiments provide a quantum dot active structure and a methodology for its fabrication. The quantum dot active structure includes a substrate, a plurality of alternating regions of a quantum dot active region and a strain-compensation region, and a cap layer. The strain-compensation region is formed to eliminate the compressive strain of an adjacent quantum dot active region, thus allowing quantum dot active regions to be densely-stacked. The densely-stacked quantum dot active region provides increased optical modal gain for semiconductor light emitting devices such as edge emitting lasers, vertical cavity lasers, detectors, micro-cavity emitters, optical amplifiers or modulators.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: September 14, 2010
    Assignee: STC.UNM
    Inventors: Diana L. Huffaker, Noppadon Nuntawong
  • Patent number: 7791062
    Abstract: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: September 7, 2010
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee
  • Publication number: 20100213436
    Abstract: An ultra-violet light-emitting device and method for fabricating an ultraviolet light emitting device, 12, (LED or an LD) with an AlInGaN multiple-quantum-well active region, 10, exhibiting stable cw-powers. The device includes a non c-plane template with an ultraviolet light-emitting structure thereon. The template includes a first buffer layer, 321, on a substrate, 100, then a second buffer layer, 421, on the first preferably with a strain-relieving layer, 302, in both buffer layers. Next there is a semi-conductor layer having a first type of conductivity, 500, followed by a layer providing a quantum-well region, 600. Another semi-conductor layer, 700, having a second type of conductivity is applied next. Two metal contacts, 980 and 990, are applied to this construction, one to the semiconductor layer having the first type of conductivity and the other to the semiconductor layer having the second type of conductivity, to complete the light emitting device.
    Type: Application
    Filed: May 8, 2008
    Publication date: August 26, 2010
    Inventor: Asif Khan
  • Patent number: 7781755
    Abstract: The main objective of present invention is to provide a manufacturing method of light emitting diode that utilizes metal diffusion bonding technology. AlInGaP light emitting diode epitaxial structure on a temporary substrate is bonded to a permanent substrate having a thermal expansion coefficient similar to that of the epitaxial structure, and then the temporary substrate is removed to produce an LED having a vertical structure and better performance. The other objective of the present invention is to provide a high performance LED that uses metal diffusion technology and wet chemical etching technology to roughen the LED surface in order to improve light extraction efficiency.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: August 24, 2010
    Assignee: Arima Optoelectronics Corp.
    Inventors: Ying-Che Sung, Chao-Hsin Wang, Yi-Hsiung Chen, Shih-Yu Chiu
  • Publication number: 20100207100
    Abstract: A radiation-emitting semiconductor body includes a contact layer and an active zone. The semiconductor body has a tunnel junction arranged between the contact layer and the active zone. The active zone has a multi-quantum well structure containing at least two active layers that emit electromagnetic radiation when an operating current is impressed into the semiconductor body.
    Type: Application
    Filed: June 20, 2008
    Publication date: August 19, 2010
    Applicant: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Martin Strassburg, Lutz Hocppel, Matthias Sabathil, Matthias Peter, Uwe Strauss
  • Patent number: 7759694
    Abstract: In a nitride semiconductor light-emitting device having an active layer between an n-type nitride semiconductor layer and a p-type nitride semiconductor layer, the active layer has a multiple quantum well structure including a plurality of InxGa1-xN (0<x?1) quantum well layers and a plurality of InyGa1-yN (0?y<1) barrier layers stacked alternately, and at least one of the plurality of barrier layers has a super-lattice structure in which a plurality of barrier sub-layers having mutually different In composition ratios are stacked periodically.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: July 20, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Satoshi Komada
  • Patent number: 7745816
    Abstract: A semiconductor photodetector for photon detection without the use of avalanche multiplication, and capable of operating at low bias voltage and without excess noise. In one embodiment, the photodetector comprises a plurality of InP/AlInGaAs/AlGaAsSb layers, capable of spatially separating the electron and the hole of an photo-generated electron-hole pair in one layer, transporting one of the electron and the hole of the photo-generated electron-hole pair into another layer, focalizing it into a desired volume and trapping it therein, the desired volume having a dimension in a scale of nanometers to reduce its capacitance and increase the change of potential for a trapped carrier, and a nano-injector, capable of injecting carriers into the plurality of InP/AlInGaAs/AlGaAsSb layers, where the carrier transit time in the nano-injector is much shorter than the carrier recombination time therein, thereby causing a very large carrier recycling effect.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: June 29, 2010
    Assignee: Northwestern University
    Inventor: Hooman Mohseni
  • Publication number: 20100155700
    Abstract: This invention discloses a thermoelectric structure for cooling an integrated circuit (IC) chip, the thermoelectric structure comprises a first type superlattice layer formed on top of the IC chip connected to a first voltage, and a second type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being different from the first voltage, wherein an power supply current flows through the first and second type superlattice layer for cooling the IC chip.
    Type: Application
    Filed: December 22, 2008
    Publication date: June 24, 2010
    Inventors: Shih Cheng Chang, Hsin-Yu Pan
  • Patent number: 7741654
    Abstract: The present invention provides a semiconductor laser excellent in the current injection efficiency. In an inner stripe type semiconductor laser according to the present invention, a p type cladding layer 309 has a superlattice structure composed of GaN layers and Al0.1Ga0.9N layers, which are alternately layered on each other. The p type cladding layer 309 has a portion of high dislocation density and a portion of low dislocation density. That is, the dislocation density is relatively low in a region directly above an opening of the current-confining region 308, whereas the dislocation density is relatively high in a region directly above a current-confining region 308.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: June 22, 2010
    Assignee: NEC Corporation
    Inventors: Kazuhisa Fukuda, Chiaki Sasaoka, Akitaka Kimura
  • Publication number: 20100148146
    Abstract: An embodiment is a method and apparatus for a white or full-color light-emitting diode. First single or multiple quantum wells (QWs) at a first wavelength are formed at an active region between a p-type layer and an n-type layer of a light-emitting diode. Multiple passive quantum wells (QWs) are formed within the p-type layer or the n-type layer. The multiple passive QWs are optically pumped by the first or single multiple QWs to generate a desired color.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: David P. Bour, Christopher L. Chua, Noble M. Johnson
  • Publication number: 20100132770
    Abstract: A device including semiconductor nanocrystals and a layer comprising a doped organic material disposed over the substrate and in electrical connection with at least one semiconductor nanocrystals is disclosed. Methods for making the device and for improving the efficiency of a device are also disclosed.
    Type: Application
    Filed: February 8, 2007
    Publication date: June 3, 2010
    Inventors: Paul H.J. Beatty, Seth Coe-Sullivan
  • Publication number: 20100126568
    Abstract: Disclosed is a nanostructure including a first set of nanowires formed from filling a plurality of voids of a template. The nanostructure also includes a second set of nanowires formed from filling a plurality of spaces created when the template is removed, such that the second set of nanowires encases the first set of nanowires. Several methods are also disclosed. In one embodiment, a method of fabricating a nanostructure including nanowires is disclosed. The method may include forming a first set of nanowires in a template, removing a first portion of the template, thereby creating spaces between the first set of nanowires, forming a second set of nanowires in the spaces between the first set of nanowires, and removing a second portion of the template.
    Type: Application
    Filed: January 14, 2010
    Publication date: May 27, 2010
    Inventors: Charles Elijah May, Vijay Pal Singh, Suresh KS Rajaputra
  • Patent number: 7723719
    Abstract: A method of fabricating a light emitting device includes modulating a crystal growth parameter to grow a quantum well layer that is inhomogeneous and that has a non-random composition fluctuation across the quantum well layer.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: May 25, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Christopher L. Chua, Zhihong Yang, John E. Northrup, Noble Marshall Johnson
  • Patent number: 7714317
    Abstract: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: May 11, 2010
    Assignee: Brookhaven Science Associates, LLC
    Inventors: Eli Anguelova Sutter, Peter Werner Sutter
  • Patent number: 7704770
    Abstract: The main objective of present invention is to provide a manufacturing method of light emitting diode that utilizes metal diffusion bonding technology. AlInGaP light emitting diode epitaxial structure on a temporary substrate is bonded to a permanent substrate having a thermal expansion coefficient similar to that of the epitaxial structure, and then the temporary substrate is removed to produce an LED having a vertical structure and better performance. The other objective of the present invention is to provide a high performance LED that uses metal diffusion technology and wet chemical etching technology to roughen the LED surface in order to improve light extraction efficiency.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: April 27, 2010
    Assignee: Arima Optoelectronics Corp.
    Inventors: Ying-Che Sung, Chao-Hsin Wang, Yi-Hsiung Chen, Shih-Yu Chiu
  • Patent number: 7705345
    Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: April 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Kevin K. Chan, Dureseti Chidambarrao, Silke H. Christianson, Jack O. Chu, Anthony G. Domenicucci, Kam-Leung Lee, Anda C. Mocuta, John A. Ott, Qiqing C. Ouyang
  • Patent number: 7700941
    Abstract: A surface-emitting semiconductor laser includes an active zone, the active zone having a p-n-junction and surrounded by a first n-doped semiconductor layer and at least one p-doped semiconductor layer; a tunnel contact layer on the p-side of the active zone; an n-doped current-carrying layer that covers the tunnel contact layer, the n-doped current-carrying layer comprising a raised portion; and a structured layer having an optical thickness at least equal to the optical thickness of the current-carrying layer in the region of the raised portion, wherein the structured layer is disposed on the current-carrying layer within a maximum distance of 2 ?m from the raised portion.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: April 20, 2010
    Assignee: Vertilas GmbH
    Inventor: Markus Ortsiefer
  • Patent number: 7701072
    Abstract: The semiconductor device according to an aspect of the invention includes: an internal circuit area having an internal circuit; an I/O circuit area positioned outside the internal circuit area; and an electrode pad placed across an outer edge of the I/O circuit area. In the electrode pad, an area outside the outer edge of the I/O circuit area is a bonding area, and an area inside the outer edge is a probe area.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: April 20, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takayuki Nishida
  • Publication number: 20100084630
    Abstract: A high speed and miniature detection system, especially for electromagnetic radiation in the GHz and THz range comprises a semiconductor structure having a 2D charge carrier layer or a quasi 2D charge carrier layer with incorporated single or multiple defects, at least first and second contacts to the charge carrier layer, and a device for measuring photovoltage between the first and second contacts. System operation in various embodiments relies on resonant excitation of plasma waves in the semiconductor structure.
    Type: Application
    Filed: October 7, 2008
    Publication date: April 8, 2010
    Inventors: Igor Kukushkin, Viacheslav Muravev
  • Patent number: 7692181
    Abstract: A number of light-emitting layer structures for the GaN-based LEDs that can increase the lighting efficiency of the GaN-based LEDs on one hand and facilitate the growth of epitaxial layer with better quality on the other hand are provided. The light-emitting layer structure provided is located between the n-type GaN contact layer and the p-type GaN contact layer. Sequentially stacked on top of the n-type GaN contact layer is the light-emitting layer containing a lower barrier layer, at least one intermediate layer, and an upper barrier layer. That is, the light-emitting layer contains at least one intermediate layer interposed between the upper and lower barrier layers. When there are multiple intermediate layers inside the light-emitting layer, there is an intermediate barrier layer interposed between every two immediately adjacent intermediate layers.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: April 6, 2010
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Cheng-Tsang Yu, Liang-Wen Wu, Tzu-Chi Wen, Fen-Ren Chien
  • Patent number: 7687798
    Abstract: The present invention relates a method for epitaxial growth of a second group III-V crystal having a second lattice constant over a first group III-V crystal having a first lattice constant, wherein strain relaxation associated with lattice-mismatched epitaxy is suppressed and thus dislocation defects do not form. In the first step, the surface of the first group III-V crystal (substrate) is cleansed by desorption of surface oxides. In the second step, a layer of condensed group-V species is condensed on the surface of the first group III-V crystal. In the third step, a mono-layer of constituent group-III atoms is deposited over the layer of condensed group-V species in order for the layer of constituent group-III atoms to retain the condensed group-V layer. Subsequently, the mono-layer of group-III atoms is annealed at a higher temperature.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: March 30, 2010
    Assignee: HRL Laboratories, LLC
    Inventor: Binqiang Shi
  • Patent number: 7679077
    Abstract: A nanodevice (1) for a desired function includes a substrate (11), a one-dimensional nanostructure (12), a functional layer (20) having a desired function, a conductive thin film electrode (30), and an insulating layer (40). The one-dimensional nanostructure is operatively extends from the substrate. The functional layer surrounds at least a portion of the one-dimensional nanostructure. The conducting thin film electrode surrounds/encompasses the functional layer. The insulating layer is positioned between the substrate and the conductive thin film electrode, thereby electrically insulating the one from the other. Further, the nanodevice can incorporate one or more functional units 50, each unit including a one-dimensional nanostructure and a respective functional layer. The units may or may not share the same conductive thin film electrode and/or insulating layer.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: March 16, 2010
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yuan Yao, Wei-Guo Chu, Shou-Shan Fan
  • Publication number: 20100059735
    Abstract: A light emitting diode (LED) having a barrier layer with a superlattice structure is disclosed. In an LED having an active region between an GaN-based N-type compound semiconductor layer and a GaN-based P-type compound semiconductor layer, the active region comprises a well layer and a barrier layer with a superlattice structure. As the barrier layer with the superlattice structure is employed, it is possible to reduce occurrence of defects caused by lattice mismatch between the well layer and the barrier layer.
    Type: Application
    Filed: November 21, 2007
    Publication date: March 11, 2010
    Applicant: Seoul Opto Device Co., Ltd.
    Inventors: Sang Joon Lee, Duck Hwan Oh, Kyung Hae Kim, Chang Seok Han
  • Publication number: 20100044600
    Abstract: A quantum computer includes a unit including thin films A, B and C each containing a physical-system group A, B and C formed of physical systems A, B and C, the films A, B and C being alternately stacked in an order of A, B, C, A, . . . , each of the systems A, B and C having three-different-energy states |0>X, |1>X, |e>x, a quantum bit being expressed by a quantum-mechanical-superposition state of |0>X and |1>X, a light source generating light beams having angular frequencies ?A(E), ye, g, ?A(E), ye, e, ?x, ye, gg, ?x, ye, ge, ?x, ye, eg and ?x, ye, ee, ?A(E), ye, g, a unit controlling frequencies and intensities of the beams, and a unit measuring intensity of light emitted from or transmitted through physical-system group A(E) contained in a lowest one of the thin films A to detect a quantum state of the group A(E).
    Type: Application
    Filed: August 19, 2009
    Publication date: February 25, 2010
    Inventors: Kouichi ICHIMURA, Hayato Goto
  • Patent number: 7663138
    Abstract: A n-type layer, a multiquantum well active layer comprising a plurality of pairs of an InGaN well layer/InGaN barrier layer, and a p-type layer are laminated on a substrate to provide a nitride semiconductor light emitting element. A composition of the InGaN barrier included in the multiquantum well active layer is expressed by InxGa1-xN (0.04?x?0.1), and a total thickness of InGaN layers comprising an In composition ratio within a range of 0.04 to 0.1 in the light emitting element including the InGaN barrier layers is not greater than 60 nm.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: February 16, 2010
    Assignee: Hitachi Cable, Ltd.
    Inventor: Hajime Fujikura
  • Publication number: 20100025657
    Abstract: A nitride semiconductor device including a light emitting device comprises a n-type region of one or more nitride semiconductor layers having n-type conductivity, a p-type region of one or more nitride semiconductor layers having p-type conductivity and an active layer between the n-type region and the p-type region. In such devices, there is provided with a super lattice layer comprising first layers and second layers which are nitride semiconductors having a different composition respectively. The super lattice structure makes working current and voltage of the device lowered, resulting in realization of more efficient devices.
    Type: Application
    Filed: September 30, 2009
    Publication date: February 4, 2010
    Inventors: Shinichi NAGAHAMA, Masayuki Senoh, Shuji Nakamura
  • Patent number: 7652288
    Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: January 26, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Basanth Jaqannathan, Alfred Grill, Bernard S. Meyerson, John A. Ott
  • Publication number: 20100012921
    Abstract: A nanowire according to the present invention includes: a nanowire body made of a first material; and a plurality of semiconductor particle made of a second material and being contained in at least a portion of the interior of the nanowire body.
    Type: Application
    Filed: November 29, 2007
    Publication date: January 21, 2010
    Inventors: Takahiro Kawashima, Tohru Saitoh
  • Patent number: 7638791
    Abstract: An improved photodiode and method of producing an improved photodiode comprising doping an InAs layer of an InAs/GaSb region situated on top of an InAs/GaSb:Be superlattice and below an InAs:Si/GaSb regions such that the quantum efficiency of the photodiode increases and dominant dark current mechanisms change from diffusion to band-to-band tunneling as the InAs layer is doped with Beryllium.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: December 29, 2009
    Assignee: MP Technologies, LLC
    Inventor: Manijeh Razeghi
  • Patent number: RE42008
    Abstract: An nitride semiconductor device for the improvement of lower operational voltage or increased emitting output, comprises an active layer comprising quantum well layer or layers and barrier layer or layers between n-type nitride, semiconductor layers and p-type nitride semiconductor layers, wherein said quantum layer in said active layer comprises InxGa1—xN (0<x<1) having a peak wavelength of 450 to 540 nm and said active layer comprises laminating layers of 9 to 13, in which at most 3 layers from the side of said n-type nitride semiconductor layers are doped with an n-type impurity selected from the group consisting of Si, Ge and Sn in a range of 5×1016 to 2×1018/cm3.
    Type: Grant
    Filed: June 7, 2000
    Date of Patent: December 28, 2010
    Assignee: Nichia Corporation
    Inventor: Koji Tanizawa