Abstract: A power semiconductor device includes a semiconductor body having first and second opposing sides and an edge termination region arranged between an active region and an outer rim. The semiconductor body further includes a first doping region in the active region and connected to a first electrode arranged on the first side of the semiconductor body, a second doping region in the active region and the edge termination region and connected to a second electrode arranged on the second side of the semiconductor body, a drift region between the first doping region and the second doping region, the drift region comprising a first portion adjacent to the first side of the semiconductor body and a second portion arranged between the first portion and the second doping region, and an insulating region arranged in the edge termination region between the second doping region and the first portion of the drift region.

Abstract: A high-voltage semiconductor device is provided. The device includes an epitaxial layer formed on a semiconductor substrate. The semiconductor substrate includes a first doping region having a first conductivity type. The epitaxial layer includes a body region that has a second conductivity type and a second doping region and a third doping region that have the first conductivity type. The second doping region and the third doping region are respectively on both opposite sides of the body region. A source region and a drain region are respectively in the body region and the second doping region. A gate structure is on the epitaxial layer. A fourth doping region having the second conductivity region is below the source region and adjacent to the bottom of the body region. The fourth doping region has a doping concentration greater than that of the body region.

Abstract: An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion of the transistors. Elevating the LDD regions is accomplished by a selective epitaxial process prior to LDD implant. Recessing the replacement gates is accomplished by etching substrate material after removal of sacrificial gate material and before formation of a replacement gate dielectric layer. Elevating the LDD regions and recessing the replacement gates may increase a channel length of the MOS transistors and thereby desirably increase threshold uniformity of the transistors.

Abstract: A semiconductor device comprises a transistor in a semiconductor body having a first main surface. The transistor comprises a source region of a first conductivity type, a drain region, a body region of a second conductivity type, different from the first conductivity type, and a gate electrode disposed in gate trenches extending in a first direction parallel to the first main surface. The source region, the body region and the drain region are arranged along the first direction. The body region comprises first ridges extending along the first direction, the first ridges being disposed between adjacent gate trenches in the semiconductor body. The body region further comprises a second ridge. A width of the second ridge is larger than a width of the first ridges, the widths being measured in a second direction perpendicular to the first direction.

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

Abstract: An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.

Abstract: An electronic circuit includes a first transistor device and a second transistor device of the same conductivity type. The first transistor device is integrated in a first semiconductor body and includes a first load pad at a first surface of the first semiconductor body and a second load pad at a second surface of the first semiconductor body. The second transistor device is integrated in a second semiconductor body and includes a first load pad at a first surface of the second semiconductor body, and a second load pad at a second surface. The first load pad of the second transistor device is mounted to the first load pad of the first transistor device and the second load pad of the first transistor device is mounted to an electrically conducting carrier.

Abstract: Aspects of the invention can include a semiconductor device, control IC for switching power supply and switching power supply unit, which allow input voltage detecting function to be realized without resistor-voltage dividing circuit. An npn-type element consisting of p-type region, collector region and emitter region is included inside of drain region of starting element. On a first interlayer insulating film, aspects of the invention can provide collector electrode wiring of npn-type element, emitter-drain electrode wiring serving as both emitter electrode wiring of npn-type electrode and drain electrode wiring of starting element, source electrode wiring of starting element, and gate electrode wiring of starting element. A first metal wiring can serve both as input terminal of starting element and input terminal of npn-type element is connected to collector electrode wiring. The npn-type element can function as input voltage detecting means for detecting input voltage drop applied to the first wiring.

Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

Abstract: The present invention relates to a lateral high-voltage device. The device includes a dielectric trench region. A doping-overlapping structure with different doping types alternating mode is provided at least below, on a left side of, or on a right side of the dielectric trench region. The device also includes a dielectric layer, a body field plate, a polysilicon gate, a gate oxide layer, a first N-type heavy doping region, a second N-type heavy doping region, a P-type heavy doping region, a P-well region, the first N-type doping pillar, the second N-type doping pillar, the third N-type doping pillar, the first P-type doping pillar, and the second P-type doping pillar. The invention adopts a dielectric trench region in the drift region to keep the breakdown voltage BV of the device while reducing the surface area of the device, and effectively reducing the device's specific On-Resistance RON,sp.

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Abstract: A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the drift region. The structure further includes an n-type source region contained in the p-type body region; an n-type drain region contained in the n-type drift region; a gate electrode disposed on a gate dielectric overlying a portion of the p-type body region and the n-type drift region and an electrically conductive field shield member disposed within the n-type drift region at least partially beneath the p-type body region and generally parallel to the gate electrode. The electrically conductive buried field shield member is contained within and surrounded by a layer of buried field shield oxide and is common to both a first LD MOSFET and a second LD MOSFET that are connected in parallel. Methods to fabricate the structure are also disclosed.

Abstract: VDMOS transistors, Bipolar-CMOS-DMOS (BCD) devices including VDMOS transistors, and methods for fabricating integrated circuits with such devices are provided. In an example, a BCD device having a VDMOS transistor includes a buried layer over a substrate and an epitaxial layer over the buried layer and having an upper surface. Deep trench isolation regions extend from the upper surface of the epitaxial layer, into the substrate, and isolate a VDMOS region from a device region. In the VDMOS region, a source region is adjacent the upper surface, a vertical gate structure extends into the epitaxial layer, a body region is located adjacent the vertical gate structure and forms a channel, and a VDMOS conductive structure extends through the epitaxial layer and into the buried layer, which is a drain for the VDMOS transistor. The VDMOS conductive structure is a drain contact to the buried layer.

Abstract: A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. The trench MOSFET device comprises a semiconductor substrate of a first conductivity type. The semiconductor substrate has a plurality of first trenches arranged side by side in a first preset area of the semiconductor substrate extending along a first direction and a plurality of second trenches arranged side by side in a second preset area of the semiconductor substrate extending along a second direction perpendicular to the first direction. A control gate is formed in each of the pluralities of first and second trenches. A body region of a second conductivity type is formed at a top portion of the semiconductor substrate near sidewalls of the pluralities of first and second trenches. A source region of the first conductivity type is formed on a top portion of the body region.

Abstract: The semiconductor device including a device isolation layer disposed in a substrate and defining an active region, a first conductive pattern on the active region, an impurity region in the active region on a side of the first conductive pattern, a second conductive pattern on the active region between the impurity region and the first conductive pattern, a first spacer between the first conductive pattern and the second conductive pattern, and a contact plug disposed on and electrically connected to the first conductive pattern may be provided. The second conductive pattern may have a width less than a width of the contact plug.

Abstract: A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, and a first well region disposed in the semiconductor substrate, wherein the first well region has a second conductivity type opposite to the first conductivity type. The semiconductor device also includes a buried layer disposed in the semiconductor substrate and under the first well region, wherein the buried layer has the first conductivity type and is in contact with the first well region. The semiconductor device further includes a source electrode, a drain electrode and a gate structure disposed on the semiconductor substrate, wherein the gate structure is located between the source electrode and the drain electrode.

Abstract: A semiconductor device includes a well region of a first conductivity type, having a first depth, formed in a substrate. A source contact region of a second conductivity type is formed in the well region. A drift region of the second conductivity type, having a second depth greater than 50% of the first depth, is formed in the substrate adjacent to the well region. A drain contact region of the second conductivity type is formed in the drift region. A gate electrode is formed on the substrate between the source contact region and the drain contact region. The drain contact region is spaced apart from the gate electrode and the source contact region is adjacent to the gate electrode. Furthermore, a method of fabricating a semiconductor device is also provided. The method includes performing a multi-step implantation process to form a drift region.

Abstract: In one embodiment, a method of forming an MOS transistor includes forming a threshold voltage (Vth) of the MOS transistor to have a first value at interior portions of the MOS transistor and a second value at other locations within the MOS transistor that are distal from the interior portion wherein the second value is less than the first value.

Abstract: A method of manufacturing a semiconductor device, including implanting hydrogen atoms from a second principal surface of a semiconductor substrate, forming a plurality of second semiconductor layers that each have a carrier concentration higher than that of the first semiconductor layer and that have carrier concentration peak values at different depths from the second principal surface of the semiconductor substrate, applying a heat treatment process to promote generation of donors from the hydrogen atoms, implanting an impurity from the second principal surface of the semiconductor substrate, forming a third semiconductor layer in the semiconductor substrate at the second principal surface thereof, and applying another heat treatment process to locally heat the semiconductor substrate, so as to reduce the carrier concentration at an interface between the third semiconductor layer and the second semiconductor layer adjacent to the third semiconductor layer.

Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.

Abstract: Provided is a method for manufacturing a highly reliable display device.

Abstract: Disclosed are an ambipolar transistor and a leakage current cutoff device using the same. The ambipolar transistor includes: a substrate; a gate formed on the substrate; a gate insulating film formed of an SiOC thin film and disposed on the substrate and the gate; and a source portion and a drain portion formed on the gate insulating film and spaced apart from each other, wherein the source portion and the drain portion comprise: a main source terminal and a main drain terminal disposed on the gate insulating film at right and left sides of the gate, respectively; and a plurality of source sub-terminals and a plurality of drain sub-terminals alternately arranged between the main source terminal and the main drain terminal, respectively.

Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Abstract: Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions.

Abstract: A bidirectional Metal-Oxide-Semiconductor (MOS) device, including a P-type substrate, and an active region. The active region includes a drift region, a first MOS structure and a second MOS structure; the first MOS structure includes a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure includes a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; and the drift region includes a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region. The active region is disposed on the upper surface of the P-type substrate. The first MOS structure and the second MOS structure are symmetrically disposed on two ends of the upper layer of the drift region.

Abstract: An embodiment of an integrated circuit includes a minimum lateral dimension of a semiconductor well at a first surface of a semiconductor body. The integrated circuit further includes a first lateral DMOSFET having a load path electrically coupled to a load pin. The first lateral DMOSFET is configured to control a load current through a load element electrically coupled to the load pin. A minimum lateral dimension of a drain region of the first lateral DMOSFET at the first surface of the semiconductor body is more than 50% greater than the minimum lateral dimension.

Abstract: This disclosure provides a package substrate, a flip-chip package circuit, and their fabrication methods. The package substrate includes: a first wiring layer having a first dielectric material layer and a first metal wire protruding from the first dielectric material layer; a conductive pillar layer formed on the first wiring layer and including a molding compound layer, a second dielectric material layer formed on the molding compound layer, and a metal pillar connected to the first metal wire; a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the metal pillar; and a protection layer formed on the second wiring layer.

Abstract: A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abuts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion.

Abstract: The present disclosure relates to a semiconductor device in which a trench termination structure is applied. There is disclosed a semiconductor device of which structure is partially improved so that a P body area is not formed in an adjacent area of a gate pad. The semiconductor device includes a gate pad formed on a substrate, an active area formed in the substrate and comprising trenches, an isolation area to isolates the gate pad and the active area, and a section of the active area adjacent to the gate pad where a P-body is not formed. According to such the semiconductor device, it is possible to minimize a drain-source leakage current and to stably secure a drain-source breakdown voltage.

Abstract: A LDMOS transistor includes a semiconductor substrate with a first doping type; a plurality of first trenches formed in the semiconductor substrate; a wave-shaped drift region with an increased conductive path and a second doping type formed on the semiconductor substrate between adjacent first trenches and the semiconductor substrate exposed by side and bottom surfaces of the first trenches; a first shallow trench isolation (STI) structure formed in each of the first trenches; a body region with the first doping type formed in semiconductor substrate at one side of the drift region; a gate structure formed over portions of the body region, the drift region and the first STI structure most close to the body region; a source region formed in the body region; and a drain region formed in the drift region at one side of the first STI structure most far away from the body region.

Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

Abstract: High-voltage semiconductor devices are provided. The high-voltage semiconductor device includes a substrate and an isolation structure in the substrate. The high-voltage semiconductor device includes a gate structure disposed on the substrate, wherein the gate structure is separated from the isolation structure by a distance. The high-voltage semiconductor device also includes a metal electrode disposed on the gate structure, wherein the metal electrode extends to directly above the isolation structure. The high-voltage semiconductor device further includes an interconnection structure including the lowest metal layer, wherein the metal electrode is between the lowest metal layer and the gate structure. Methods of manufacturing the high-voltage semiconductor device are also provided.

Abstract: A semiconductor device includes a gate structure that extends from a first surface into a semiconductor portion and that surrounds a transistor section of the semiconductor portion. A field plate structure includes a field electrode and extends from the first surface into the transistor section. A mesa section of the semiconductor portion separates the field plate structure and the gate structure. A contact structure includes a first portion directly adjoining the mesa section and a second portion directly adjoining the field electrode. The first and second portions include stripes and are directly connected to each other.

Abstract: A polycrystalline silicon thin-film transistor includes a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

Abstract: A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a MOSFET region, as dummy gate structures in a JFET region of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments, thereby forming an accurately dimensioned transistor channel.

Abstract: A monolithic three-dimensional memory device includes a plurality of memory stack structures arranged in a hexagonal lattice and located over a substrate. The hexagonal lattice structure is defined by hexagons each having a pair of sides that are parallel to a first horizontal direction and perpendicular to a second horizontal direction, the memory stack structures are located at vertices of the hexagonal lattice, and each memory stack structure includes vertically spaced memory elements and a vertical semiconductor channel. Source contact via structures are located at each center of a subset of the hexagons that forms a one-dimensional array that extends along the second horizontal direction, each source contact via structure being electrically shorted to a respective source region over, or within, the substrate.

Abstract: A micro electro-mechanical system (MEMS) device is provided. The MEMS device includes: a substrate having a first surface and a second surface and wherein the first surface is exposed to an environment outside the MEMS device; and a MEMS microphone disposed at a first location on the second surface of the substrate and having a diaphragm positioned such that acoustic waves received at the MEMS microphone are incident on the diaphragm. The MEMS device also includes: a first integrated circuit disposed at a second location of the substrate, wherein the first integrated circuit is electrically coupled to the MEMS microphone; and a MEMS measurement device at a third location, wherein the MEMS measurement device comprises a motion sensor and a pressure sensor.

Abstract: A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.

Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.

Abstract: A power integrated device includes a semiconductor layer having first conductivity, a source region and a drain region each having second conductivity and disposed in the semiconductor layer, wherein the source region and the drain region are spaced apart from each other, a first drift region having the second conductivity, disposed in the semiconductor layer, and surrounding the drain region, a second drift region having the second conductivity, disposed in the semiconductor layer, contacting a sidewall of the first drift region, and having an impurity concentration lower than an impurity concentration of the first drift region, a gate insulation layer disposed over a channel region between the source region and the second drift region and extending over the second drift region, a field insulation plate disposed over the second drift region and the first drift region, contacting a sidewall of the gate insulation layer, and having a planar structure, and a gate conductive pattern disposed over the gate insula

Abstract: The present invention provides a display substrate and a manufacturing method thereof. The display substrate of the present invention comprises a first structure and a second structure; wherein, the second structure is provided with a lap portion disposed on the first structure and a main body portion connected with the lap portion and outside the first structure; the first structure has a thinned region connected to an edge thereof, and a thickness of the first structure in the thinned region is smaller than that outside the thinned region; and at least part of the lap portion is located on the thinned region, and at least part of the main body portion outside the thinned region is in direct connection with the part of the lap portion on the thinned region.

Abstract: A light-emitting element includes a light-emitting section and a driving circuit that drives the light-emitting section. The driving circuit includes at least (A) a drive transistor that is a p-channel field effect transistor, (B) an image-signal writing transistor that is a p-channel field effect transistor, (C) a light-emission control transistor that is a p-channel field effect transistor, and (D) a capacitor. Each of the drive transistor, image-signal writing transistor, and light-emission control transistor is provided in an n-type well formed in a p-type silicon semiconductor substrate. A first source/drain region of the drive transistor is electrically connected to the n-type well in which the drive transistor is formed.

Abstract: Hydrogen atoms and crystal defects are introduced into an n? semiconductor substrate by proton implantation. The crystal defects are generated in the n? semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

Abstract: New, distinct, and useful architectures for single-legged SOI-MOS were established and fabricated for the very first time. They incorporated into their architectures an innovative new configuration to wire the device Body to the Body-Tied-Source. This new configuration drastically increased the conductance between the Body and the Body-Tied-Source. This consequently allowed these devices to effectively support much higher operating biases. Same configuration also functioned on structures with very large peripheries. These gave proportional increase in this same conductivity, and for same area-efficiency, with the increase of their peripheries to accommodate higher currents. The functional model that governs this proportional scaling in these new architectures for single-legged SOI-MOS devices was established and is being claimed through this patent for the very first time.

Abstract: A transistor structure including a substrate, a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on the substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.

Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.

Abstract: A lateral double diffused metal oxide semiconductor field-effect transistor includes semiconductor substrates, body regions positioned in the semiconductor substrates, drift regions positioned in the semiconductor substrates, source regions and a body leading-out region which are positioned in the body regions and spaced from the drift regions, a field region and drain regions which are positioned in the drift regions, and gates positioned on the surfaces of the semiconductor substrates to partially cover the body regions, the drift regions and the field region, wherein the field region is of a finger-like structure and comprises a plurality of strip field regions which extend from the source regions to the drain regions and are isolated by the active regions; and the strip field regions provided with strip gate extending regions extending from the gates.