Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes a semiconductor substrate and a temperature sensing diode that is disposed on a surface part of the semiconductor substrate. A relation between a forward current flowing through the temperature sensing diode and a corresponding voltage drop across the temperature sensing diode varies with temperature. The semiconductor apparatus further includes a capacitor that is coupled with the temperature sensing diode, configured to reduce noise to act on the temperature sensing diode, and disposed such that the capacitor and the temperature sensing diode have a layered structure in a thickness direction of the semiconductor substrate.

Abstract: Provided is a method and apparatus for fabricating a polycrystalline silicon film using a transparent substrate. The method includes forming a light absorption layer on a surface of the transparent substrate; and heating the light absorption layer using irradiation of Rapid Thermal Process (RTP) light source, while depositing the polycrystalline silicon film on the light absorption layer.

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD?V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.

Abstract: The present invention provides a production method of a semiconductor device, which can improve characteristics of a semiconductor element including a single crystal semiconductor layer formed by transferring on an insulating substrate. The present invention is a production method of a semiconductor device comprising a single crystal semiconductor layer formed on an insulating substrate, the production method comprising the steps of: implanting a substance for separation into a single crystal semiconductor substrate, thereby forming a separation layer; transferring a part of the single crystal semiconductor substrate, separated at the separation layer, onto the insulating substrate, thereby forming the single crystal semiconductor layer; forming a hydrogen-containing layer on at least one side of the single crystal semiconductor layer; and diffusing hydrogen from the hydrogen-containing layer to the single crystal semiconductor layer.

Abstract: A memory device is described an active material configured to be placed in a more or less conductive state by means of appropriate switching processes. The active material is positioned between a material having low thermal conductivity or material layers having low thermal conductivity.

Abstract: Disclosed herewith is a semiconductor device comprising a trench gate electrode and a zener diode, as well as a method for manufacturing the same. The trench gate electrode is formed in a semiconductor body and includes a first polycrystalline silicon layer doped with impurities of a first conductivity type at a first concentration. An extended gate electrode is elongated over the semiconductor body in contact with the trench gate electrode, and includes a second polycrystalline silicon layer doped with impurities of the first conductivity type at a second concentration that is lower than the first concentration. The zener diode is formed over the semiconductor body and includes a third polycrystalline silicon layer of a first conductivity type and a fourth polycrystalline silicon layer of a second conductivity type.

Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and ac active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of silicon film to a crystalline silicon film.

Abstract: Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotataing element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points.

Abstract: A thin-film transistor, a thin-film transistor sheet, an electric circuit, and a manufacturing method thereof are disclosed, the method comprising the steps of forming a semiconductor layer by providing a semiconductive material on a substrate, b) forming an isolating area, which is electrode material-repellent, by providing an electrode material-repellent material on the substrate, and c) forming a source electrode on one end of the insulating area and a drain electrode on the other end of the insulating area, by providing an electrode material.

Abstract: A method of manufacturing a thin-film semiconductor device substrate includes a step of forming a non-single crystalline semiconductor thin film on a base layer, and an annealing step of irradiating the non-single crystalline semiconductor thin film with an energy beam to enhance crystallinity of a non-single crystalline semiconductor constituting the non-single crystalline semiconductor thin film. The annealing step includes simultaneously irradiating the non-single crystalline semiconductor thin film with a plurality of energy beams to form a plurality of unit regions each including at least one irradiated region irradiated with the energy beam and at least one non-irradiated region that is not irradiated with the energy beam.

Abstract: The present invention is related to a polycrystalline silicon film containing Ni which is formed by crystallizing an amorphous silicon layer containing nickel. The present invention includes a polycrystalline silicon film wherein the polycrystalline film contains Ni atoms of which density ranges from 2×1017 to 5×1019 atoms/cm3 on average and comprises a plurality of needle-shaped silicon crystallites. In another aspect, the present invention includes a polycrystalline silicon film wherein the polycrystalline film contains Ni atoms of which density ranges from 2×1017 to 5×1019 atoms/cm3, comprises a plurality of needle-shaped silicon crystallites and is formed on an insulating substrate. Such a polysilicon film according to the present invention avoids metal contamination usually generated in a conventional method of metal induced crystallization.

Abstract: The invention relates to a method for producing a TFA image sensor in which a multi-layer arrangement comprising a photo diode matrix is arranged on an ASIC switching circuit provided with electronic circuits for operating the TFA image sensor, such as pixel electronics, peripheral electronics and system electronics, for the pixel-wise conversion of electromagnetic radiation into an intensity-dependent photocurrent, the pixels being connected to contacts of the underlying pixel electronics of the ASIC switching circuit. The method enables conventionally produced ASIC switching circuits to be used without impairing the topography of the photoactive sensor surface. The CMOS passivation layer in the photoactive region and then the upper CMOS metallization are removed and replaced by a metallic layer which is structured in the pixel raster, for the formation of back electrodes.

Abstract: Provided herein, according to some embodiments of the invention, are organosilane polymers prepared by reacting organosilane compounds including (a) at least one compound of Formula I Si(OR1)(OR2)(OR3)R4 ??(I) wherein R1, R2 and R3 may each independently be an alkyl group, and R4 may be —(CH2)nR5, wherein R5 may be an aryl or a substituted aryl, and n may be 0 or a positive integer; and (b) at least one compound of Formula II Si(OR6)(OR7)(OR8)R9 ??(II) wherein R6, R7 and R8 may each independently an alkyl group or an aryl group; and R9 may be an alkyl group. Also provided are hardmask compositions including an organosilane compound according to an embodiment of the invention, or a hydrolysis product thereof. Methods of producing semiconductor devices using a hardmask compostion according to an embodiment of the invention, and semiconductor devices produced therefrom, are also provided.

Abstract: A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or more active regions, wherein the extended active region has at least a length twice as much as a distance between gates of two neighboring operational devices.

Abstract: An organic electronic device of the present invention includes a substrate, at least two electrodes formed on the substrate, a conductive organic thin film that is formed on the substrate and electrically connects the electrodes, and a coating film for coating at least a portion of the electrodes. The conductive organic thin film is a polymer of organic molecules containing a conjugated-bondable group, and one end of each of the organic molecules is chemically bonded to the surface of the substrate and the conjugated-bondable groups in the organic molecules are polymerized with other conjugated-bondable groups to form a conjugated bond chain. The coating film electrically connects the electrodes to the conductive organic thin film and achieves a smaller connection resistance than that in the case where the electrodes and the conductive organic thin film are connected directly.

Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.

Abstract: In a silicon crystallization mask that may be used to enhance electrical characteristics of silicon, an apparatus for crystallizing silicon having the mask and a method for crystallizing silicon using the apparatus, the mask includes first slits and second slits. The first slits are configured to transmit light and are arranged substantially parallel to one another along a first direction. The second slits transmit light, are separated by a predetermined distance along a second direction, and are arranged substantially parallel to one another along the first direction. Imaginary central lines of the first slits are offset from imaginary central lines of the second slits. Therefore, nuclei originated from a center portion of an area irradiated by the laser beam may be removed, and thus the electrical characteristics of silicon can be enhanced.

Abstract: An organic light-emitting display including a substrate, at least one thin film transistor, a pixel electrode and at least one pad electrode. The substrate is provided with a display area and a pad area spaced apart from the display area. The thin film transistor is disposed on the display area of the substrate, and includes an active layer, a gate electrode and source/drain electrodes. The pixel electrode is adjacent to the thin film transistor, and is electrically connected to the thin film transistor. The pad electrode is disposed on the pad area of the substrate, is formed of the same layer as the gate electrode or the source/drain electrodes, and is coupled with an external module.

Abstract: A semiconductor device for being mounted on the display panel board of a display apparatus includes a substrate; a plurality of circuit units disposed on the substrate and including thin-film transistors, the circuit units having respective output terminals; at least one bus interconnect for supplying a voltage to the circuit units; and a power supply feed point for supplying a voltage from an external source to the bus interconnect. The pitch L (m) of the circuit units, the number N of the circuit units, and the resistance R (?/m) per unit length of the at least one bus interconnect are related to each other as follows: R×N2×L?4×103.

Abstract: (1) A metal oxide dispersion for a dye-sensitized solar cell, which contains metal oxide fine particles, a binder composed of a polymer compound having an action to bind to the fine particles and a solvent; (2) a method for producing a photoactive electrode for a dye-sensitized solar cell by coating a dispersion containing the above-mentioned binder and metal oxide fine particles on a sheet-shaped electrode; (3) a photoactive electrode for a dye-sensitized solar cell, obtained by the method, which electrode has metal oxide containing the above-mentioned binder and metal oxide fine particles; and (4) a dye-sensitized solar cell with the above-mentioned photoactive electrode.

Abstract: A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

Abstract: A structure, for testing relative to an MOS transistor, closely resembles the MOS transistor of interest. For example, certain dimensions and a number of dopant concentrations typically are substantially the same in the test structure as found in corresponding elements of the MOS transistor of interest. However, the regions of the test structure corresponding to the source and drain of the transistor have no halos or extensions that might cause gate overlap; and in the test structure, these regions are of a semiconductor type opposite the type found in the source and drain of the transistor. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for direct electrical measurement of gate length.

Abstract: The reliability of a light-emitting device constituted by a combination of a TFT and a light-emitting element is to be improved. A light-emitting element is formed between a first substrate and a second substrate. The light-emitting device is formed over a first insulating layer made of an organic compound and a second insulating layer made of an inorganic insulating material containing nitrogen formed on the surface of the first insulating layer. In an outer circumferential part of a display area formed by the light-emitting element, a shield pattern surrounding the display area is formed by metal wiring on the second insulating layer, and the first substrate and the second substrate are fixed to each other with an adhesive resin formed in contact with the shield pattern.

Abstract: A p well serving as a channel region of a MOSFET is formed on one side of an n? layer and an n+ drain region is formed on the other side. Above the n? layer, a plurality of first floating field plates are formed with a first insulating film interposed therebetween. A plurality of second floating field plates are formed thereon with a second insulating film interposed therebetween. Assuming that the thickness of the first insulating film is “a” and the distance between the first floating field plates and the second floating field plates in a direction of thickness of the second insulating film is “b”, a relation a>b is held.

Abstract: An EL element and an interface between a channel and an impurity diffusion area of a thin film transistor provided in the vicinity of the EL element are spaced apart. A light shielding film is provided between the EL element and the interface. By providing such a space and/or the light shielding film, generation of a leak current, which would otherwise be caused by light emitted from the self-emissive EL element entering the TFT, is reliably prevented, thereby ensuring that emitted light is not brighter than a predetermined luminance.

Abstract: A thin-film transistor is formed on a transparent substrate and has a gate electrode film layer and a source and drain regions, and further has an alignment mark made of one and the same constituent material as a constituent material of at least one of the gate electrode film layer and source and drain regions and formed at one and the same position as the gate electrode film layer or source and drain region.

Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and ac active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of silicon film to a crystalline silicon film.

Abstract: A method of manufacturing a thin-film semiconductor device substrate includes a step of forming a non-single crystalline semiconductor thin film on a base layer, and an annealing step of irradiating the non-single crystalline semiconductor thin film with an energy beam to enhance crystallinity of a non-single crystalline semiconductor constituting the non-single crystalline semiconductor thin film. The annealing step includes simultaneously irradiating the non-single crystalline semiconductor thin film with a plurality of energy beams to form a plurality of unit regions each including at least one irradiated region irradiated with the energy beam and at least one non-irradiated region that is not irradiated with the energy beam.

Abstract: A method of manufacturing a thin-film solar cell, comprising the steps of: forming an amorphous silicon film on a substrate; placing a metal element that accelerates the crystallization of silicon in contact with the surface of the amorphous silicon film; subjecting the amorphous silicon film to a heat treatment to obtain a crystalline silicon film; depositing a silicon film to which phosphorus has been added in contact with the crystalline silicon film; and subjecting the crystalline silicon film and the silicon film to which phosphorus has been added to a heat treatment to getter the metal element from the crystalline film.

Abstract: A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a “transferable” device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer.

Abstract: A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the metal to a thickness of no greater than 500 Angstroms and subsequently exposing the actinic energy blocking material layer to said quanta of actinic energy. In one implementation, an homogenous actinic energy blocking material layer is formed over the metal and subsequently exposed to said quanta of actinic energy. A method of forming a non-volatile resistance variable device includes providing conductive electrode material over chalcogenide material having metal ions diffused therein.

Abstract: A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first minimum processing dimension is formed on a substrate, a memory portion (second semiconductor portion) formed by a second minimum processing dimension smaller than the first minimum processing dimension is stacked above it, and the memory portion (second semiconductor portion) is stacked with respect to the peripheral circuit portion (first semiconductor portion) with an alignment precision rougher than the second minimum processing dimension or wherein memory cells configured by 2-terminal devices are formed in regions where word lines and bit lines intersect in the memory portion, and contact portions connecting the word lines and bit lines and the peripheral circuit portions are arranged in at least two columns in directions in which the word lines

Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.

Abstract: A semiconductor optical device includes a waveguide layer and a reflecting multi-layer film. The waveguide layer includes two cladding layers and an active layer sandwiched between the two cladding layers. The reflecting multi-layer film including multiple layers is on at least one of a pair of opposing end faces of the waveguide layer. A summation ?nidi of products nidi of refractive indexes ni and thicknesses di of the layers denoted i in the reflecting multi-layer film, and a wavelength ?0 of light guided through the waveguide layer satisfies a relationship, ?nidi>?0/4. A first wavelength bandwidth ?? is wider than a second wavelength bandwidth ??. ?? is a wavelength range including the wavelength ?0 in which a reflectance R of the reflecting multi-layer film is not higher than +2.0% from reflectance R at the wavelength ?0. ?? is a wavelength range including the wavelength ?0 in which a reflectance R? of a hypothetical layer is not higher than +2.

Abstract: The present invention describes a plurality of scatterometry test structures for use in process control during fabrication of a semiconductor wafer having multilevel integrated circuit chips, many of said levels having a feature size of a critical dimension. The scatterometry test structures on the wafer are at each level, suitable to measure critical dimensions. The second level and each subsequent level of the test structures are located to fit into the same footprint area as the first level.

Abstract: A radiation detector is of the type, which by use of electric signals, which indicates the position of an irradiated point on a detector surface of the detector. The detector includes a semiconductor wafer having at least two barrier layers, which are arranged in such manner that when applying an electric bias across the layers, one layer is reversely biased and the other if forwardly biased, the extension of the reversely biased barrier layer substantially coinciding with the detector surface. The detector further includes at least two conductive layers provided with at least one current collecting electrode, the conductive layers being arranged so as to allow a transistor amplification between the forwardly and reversely biased layer by use of charge currents generated by the radiation in the irradiated point and separated by the reversely biased barrier layer.

Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.

Abstract: A photovoltaic device including a plurality of unit devices stacked, each unit device comprising a silicon-based non-single-crystal semiconductor material and having a pn or pin structure, in which an oxygen atom concentration and/or a carbon atom concentration has a maximum peak in the vicinity of a p/n interface between the plurality of unit devices.

Abstract: There is disclosed a semiconductor device and a method of fabricating the semiconductor device in which a heat treatment time required for crystal growth is shortened and a process is simplified. Two catalytic element introduction regions are arranged at both sides of one active layer and crystallization is made. A boundary portion where crystal growth from one catalytic element introduction region meets crystal growth from the other catalytic element introduction region is formed in a region which becomes a source region or drain region.

Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.

Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

Abstract: The present invention provides a package for hermetically sealing optical fibers such that they optically communicate with other optical elements/devices. First and second substrates include one or more grooves formed in a surface for retaining individual optical fibers in opposing grooves. The substrate/fiber assembly is coated with at least one layer of material to assist in providing a substantially hermetic seal between substrate/fiber assembly and a housing bonding material. This material layer(s) is/are typically selected to minimize the material differences between the substrate/fiber assembly and the housing. The housing surrounds at least a portion of the fiber/substrate assembly and may contain one or more optical elements/devices for optically communicating with optical fibers positioned in the first and second substrate grooves.

Abstract: The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing latchup sensitivity by a step to be performed after the IC has been manufactured, rather than being a step in the normal production process. The process involves exposing silicon, either in wafer or die form, to energetic ions, such as protons (hydrogen nuclei) or heavier nuclei (e.g. argon, copper, gold, etc.), having energy sufficient to penetrate the silicon from the back of the wafer or die to within a well-defined distance from the surface of the silicon on which the integrated circuit has been formed (the front surface).

Abstract: There are disclosed techniques for providing a simplified process sequence for fabricating a semiconductor device. The sequence starts with forming an amorphous film containing silicon. Then, an insulating film having openings is formed on the amorphous film. A catalytic element is introduced through the openings to effect crystallization. Thereafter, a window is formed in the insulating film, and P ions are implanted. This process step forms two kinds of regions simultaneously (i.e., gettering regions for gettering the catalytic element and regions that will become the lower electrode of each auxiliary capacitor later).

Abstract: The present invention provides a simple method for forming the poly-Si and single crystalline Si TFT, which includes forming a line peninsular layer extending from an a-Si island layer at the active region. Then, a laser annealing process is performed, so that the re-crystallization will occur starting from an end of the line peninsular layer and then form the silicon island layer, serving as the active region for the TFT.

Abstract: An electronic device includes a die further having a first major surface, and a second major surface. The electronic device also includes a plurality of connectors associated with the first major surface of the die, and an integrated heat spreader in thermally conductive relation with the second major surface of the die. The integrated heat spreader also has a layer of silicon, and a layer of diamond attached to the layer of silicon. The first major surface of the die attached to a printed circuit board. A method for forming a heat dissipating device includes placing a layer of diamond on a silicon substrate, and thinning the silicon substrate. The substrate is diced to form a plurality of heat dissipating devices sized to form a thermally conductive connection to a die. A surface of the silicon substrate is placed in thermal communication with a source of heat.

Abstract: A selective and parallel growth method of carbon nanotube for electronic-spintronic device applications which directly grows a carbon nanotube on a wanted position toward a horizontal direction comprises the steps of: forming an insulating film on a board; forming fine patterns of catalyst metal layer including a contact electrode pad on the insulating film, forming a growth barrier layer for preventing vertical growth on upper part of the catalyst metal layer; and directly growing the carbon nanotube between the catalyst patterns.

Abstract: A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the metal to a thickness of no greater than 500 Angstroms and subsequently exposing the actinic energy blocking material layer to said quanta of actinic energy. In one implementation, an homogenous actinic energy blocking material layer is formed over the metal and subsequently exposed to said quanta of actinic energy. A method of forming a non-volatile resistance variable device includes providing conductive electrode material over chalcogenide material having metal ions diffused therein.

Abstract: A solution-based method for attaching metal contacts to molecular films is described. The metal contacts are attached to functional groups on individual molecules in the molecular film. The chemical state of the functional group is controlled to induce electroless metal deposition preferentially at the functional group site. The functionalized molecules may also be patterned on a surface to give spatial control over the location of the metal contacts in a more complex structure. Spatial control is limited only by the ability to pattern the molecular film. To demonstrate the feasibility of this concept, self-assembled monolayers of model, molecular-electronic compounds have been prepared on gold surfaces, and these surfaces were subsequently exposed to electroless deposition plating baths. These samples exhibited selective metal contact attachment, even on patterned surfaces.

Abstract: A stretchable electronic apparatus and method of producing the apparatus. The apparatus has a central longitudinal axis and the apparatus is stretchable in a longitudinal direction generally aligned with the central longitudinal axis. The apparatus comprises a stretchable polymer body, and at least one circuit line operatively connected to the stretchable polymer body, the at least one circuit line extending in the longitudinal direction and having a longitudinal component that extends in the longitudinal direction and having an offset component that is at an angle to the longitudinal direction, the longitudinal component and the offset component allowing the apparatus to stretch in the longitudinal direction while maintaining the integrity of the at least one circuit line.