Abstract: Accompanying the miniaturization of a gate electrode of a trench gate power MOSFET, the curvature of the bottom part of the trench increases, and thereby, electric fields concentrate on the part and deterioration of a gate oxide film (insulating film) occurs. The deterioration of the gate insulating film is more likely to occur when the gate side bias is negative in the case of an N-channel type power MOSFET and when the gate side bias is positive in the case of a P-channel type power MOSFET. The present invention is a semiconductor device including an insulating gate power transistor etc. in a chip, wherein a gate protection element includes a bidirectional Zener diode and the bidirectional Zener diode has a plurality of P-type impurity regions (or a P-type impurity region) having different concentrations so that the withstand voltage with its gate side negatively biased and the withstand voltage with the gate side positively biased are different from each other.

Abstract: The present invention provides a semiconductor device capable of suppressing a contact failure due to an increase in contact resistance, a production method of the semiconductor device, and a display device.

Abstract: A fabrication method of an active device array substrate is disclosed. A first metal material layer, a gate insulation material layer, a channel material layer, a second metal material layer, and a first photoresist layer are formed over a substrate sequentially. The first photoresist layer is patterned with a multi-tone mask to form a first patterned photoresist layer with two thicknesses. A first and second removing processes are performed sequentially using the first patterned photoresist layer as a mask to form a gate, a gate insulation layer, a channel layer, and a source/drain. The first patterned photoresist layer is removed. A passivation layer and a second patterned photoresist layer are formed over the substrate. A third removing process is performed to form a plurality of contact holes. A pixel electrode material layer is formed over the substrate. The second patterned photoresist layer is lifted off to form a pixel electrode.

Abstract: A non-single-crystal semiconductor layer is formed over a substrate, and then a single crystal semiconductor layer is formed over part of the non-single-crystal semiconductor layer. Thus, a semiconductor element of a region which requires a large area (e.g. a pixel region in a display device) can be formed using the non-single-crystal semiconductor layer, and a semiconductor element of a region which requires high speed operation (e.g. a driver circuit region in a display device) can be formed using the single crystal semiconductor layer.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: A photonic device (200) and method (100) of making the photonic device (200) employs preferential etching of grain boundaries of a polycrystalline semiconductor material layer (210). The method (100) includes growing (110) the polycrystalline layer (210) on a substrate (201). The polycrystalline layer includes a transition region (212) of variously oriented grains and a region (214) of columnar grain boundaries (215) adjacent to the transition region. The method further includes preferentially etching (120) the colunmar grain boundaries to provide tapered structures (220) of the semiconductor material that are continuous (217) with respective aligned grains (213) of the transition region. The tapered structures are predominantly single crystal. The method further includes forming (140) a conformal semiconductor junction (240) on the tapered structures and providing (160) first and second electrodes.

Abstract: The present invention relates to a solar power generation device which includes an electric double-layer capacitor and a solar cell. The electric double-layer capacitor includes a pair of current collectors formed using a light-transmitting conductive material; active materials which are dispersed on the pair of current collectors; a light-transmitting electrolyte layer which is provided between the pair of current collectors; and a terminal portion which is electrically connected to the current collector. The solar cell includes, over a light-transmitting substrate, a first light-transmitting conductive film; a photoelectric conversion layer which is provided in contact with the first light-transmitting conductive film; and a second light-transmitting conductive film which is provided in contact with the photoelectric conversion layer.

Abstract: A thin-film device includes a plurality of circuit components defining an operational region of the thin-film device, an unpatterned channel portion (108, 340) disposed on the plurality of circuit components, and a patterned passivation dielectric (380,385) selectively disposed on the unpatterned channel portion (108, 340) to electrically pattern an active region of the unpatterned channel portion (108,340).

Abstract: A first shape of semiconductor region having on its one side a plurality of sharp convex top-end portions is formed first and a continuous wave laser beam is used for radiation from the above region so as to crystallize the first shape of semiconductor region. A continuous wave laser beam condensed in one or plural lines is used for the laser beam. The first shape of semiconductor region is etched to form a second shape of semiconductor region in which a channel forming region and a source and drain region are formed. The second shape of semiconductor region is disposed so that a channel forming range would be formed on respective crystal regions extending from the plurality of convex end portions. A semiconductor region adjacent to the channel forming region is eliminated.

Abstract: A self emission silicon emission display is provided at a low price, which contains silicon and oxygen which exist in abundance on the earth as the main component and which can be easily formed by conventional silicon process. A light emission element includes a first electrode for injecting electrons, a second electrode for injecting holes, and a light emission part electrically connected to the first electrode and the second electrode, where the light emission part includes amorphous or polycrystalline silicon consisting of a single layer or plural layers and where the dimension of the silicon in at least one direction is controlled to be several nanometers.

Abstract: A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system.

Abstract: A method of forming an organic thin film transistor comprising: providing a structure comprising source and drain electrodes with a channel region therebetween, a gate electrode, and a dielectric layer disposed between the source and drain electrodes and the gate electrode; and patterning the dielectric layer using the source and drain electrodes as a mask to form a region of dielectric material in the channel region which is thinner than regions of dielectric material adjacent the channel region.

Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.

Abstract: In one embodiment, a thin-film transistor (TFT) includes a gate electrode, a semiconductor pattern, first and second electrodes and a protective layer. The semiconductor pattern is formed on the gate electrode, and includes a first semiconductor layer deposited at a first deposition speed and a second semiconductor layer deposited at a second deposition speed faster than the first deposition speed. The first and second electrodes are spaced apart from each other on the semiconductor pattern. The protective layer is formed on the semiconductor pattern to cover the first and second electrodes, and makes contact with a channel region of the first semiconductor layer to form an interface with the first semiconductor layer. Thus, electrical characteristics of the TFT may be improved.

Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.

Abstract: An improved piezoresistive-based sensor (78) can include a cavity (66) in a substantially solid substrate (68). A reactive agent can optionally be present in the cavity (66). A flexible machined membrane can form a wall of the cavity (66). The flexible machined membrane can include an array of channels (76) configured to permit selective passage of a target material into and out of the cavity. Additionally, the flexible machined membrane can include a piezoresistive features (74) associated with the membrane. The reactive agent included in the cavity (66) can be volumetrically responsive to the presence of the target material or fluid. These sensors can be configured as pressure sensors, chemical sensors, flow sensors, and the like.

Abstract: A display substrate is provided that can prevent the opening of an upper conduction layer. The display substrate comprises a semiconductor layer pattern formed on a substrate, a data interconnection pattern formed on the semiconductor layer pattern, a protection layer formed on the substrate and the data interconnection pattern, contact holes formed on the substrate to expose at least a portion of an upper surface of the semiconductor pattern and at least a portion of an upper surface of the data interconnection pattern, and contact electrodes formed in the contact holes to be in contact with the exposed upper surfaces of the data interconnection pattern and the semiconductor layer pattern.

Abstract: Epitaxial structures, methods of making epitaxial structures, and devices incorporating such epitaxial structures are disclosed. The methods and the structures employ a liquid-phase Group IVA semiconductor element precursor ink (e.g., including a cyclo- and/or polysilane) and have a relatively good film quality (e.g., texture, density and/or purity). The Group IVA semiconductor element precursor ink forms an epitaxial film or feature when deposited on a (poly)crystalline substrate surface and heated sufficiently for the Group IVA semiconductor precursor film or feature to adopt the (poly)crystalline structure of the substrate surface. Devices incorporating a selective emitter that includes the present epitaxial structure may exhibit improved power conversion efficiency relative to a device having a selective emitter made without such a structure due to the improved film quality and/or the perfect interface formed in regions between the epitaxial film and contacts formed on the film.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: In a first aspect, a method of forming a memory cell is provided that includes: (a) forming a layer of dielectric material above a substrate; (b) forming an opening in the dielectric layer; (c) depositing a solution that includes a carbon-based switching material on the substrate; (d) rotating the substrate to cause the solution to flow into the opening and to form a carbon-based switching material layer within the opening; and (e) forming a memory element using the carbon-based switching material layer. Numerous other aspects are provided.

Abstract: A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance.

Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Abstract: A vehicle has a display device which widens the field of view (visible area) reflected by a side mirror or a back mirror mounted on the vehicle. To enable a driver driving the vehicle to confirm safety even when it is difficult for the driver to visually recognize some of objects surrounding the vehicle, a liquid crystal display device or an EL display device is provided in the side mirror (door mirror), the back mirror (room mirror) or in an interior portion of the vehicle. A camera is mounted on the vehicle and an image from the camera is displayed on the display device. Further, information read from a sensor (distance measuring sensor) having the function of measuring the distance to another vehicle, and a sensor (impact sensor) having the function of sensing an externally applied impact force larger than a predetermined value is displayed on the display device.

Abstract: In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided.

Abstract: A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon.

Abstract: The invention relates to a method for producing a MEMS/NEMS structure from a substrate made in a monocrystalline semiconductor material, the structure comprising a flexible mechanical element connected to the substrate by at least one anchoring zone, the method comprising the following steps: the formation of a protection layer on one face of the substrate, the protection layer being made in a monocrystalline material different from the material of the substrate, etching of the protection layer and the substrate in order to produce at least one cavity, the etching being done so as to leave an overhang made in the material of the protection layer on the edges of the cavity, filling in of the cavity with an electrically insulating material in order to obtain an insulating anchoring portion, epitaxy of a semiconductor material from the protection layer and the electrically insulating material in order to obtain a layer designed to produce the flexible mechanical element, liberation of the flexible mechanical

Abstract: A midwave infrared lead salt photodetector manufactured by a process comprising the step of employing molecular beam epitaxy (MBE) to grow a heterostructure photoconductive detector with a wide-gap surface layer that creates a surface channel for minority carriers.

Abstract: Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.

Abstract: An array substrate of a display device, the array substrate: a substrate having a first region and a second region spaced apart from the first region; a blocking layer located on the substrate; a first electrode located on the blocking layer in the second region; an insulating film located on the blocking layer to cover the first electrode; a second electrode located on the insulating film to overlap the first electrode; and a third electrode overlapping the first electrode between the substrate and the blocking layer. Accordingly, it is possible to reduce an area that is occupied by a storage capacitor in a pixel region and to achieve high luminance by increasing the aperture ratio, by providing a structure and method of increasing a storage capacitance of the same area.

Abstract: The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing with diffusive scattering and with a smooth front surface of the solar cell results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy.

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Abstract: A thin film transistor and method of fabricating the same are provided. The thin film transistor includes: a metal catalyst layer formed on a substrate, and a first capping layer and a second capping layer pattern sequentially formed on the metal catalyst layer. The method includes: forming a first capping layer on a metal catalyst layer; forming and patterning a second capping layer on the first capping layer; forming an amorphous silicon layer on the patterned second capping layer; diffusing the metal catalyst; and crystallizing the amorphous silicon layer to form a polysilicon layer. The crystallization catalyst diffuses at a uniform low concentration to control a position of a seed formed of the catalyst such that a channel region in the polysilicon layer is close to a single crystal. Therefore, the characteristics of the thin film transistor device may be improved and uniformed.

Abstract: An electro-mechanical transducer contains a vibrating electrode (15b), a vibrating-electrode-insulating film (15a) disposed at a bottom surface of the vibrating electrode (15b), an electret layer (13) facing to the vibrating electrode (15b), an electret-insulating layer (14e) joined to a top surface of the electret layer (13), and a back electrode 17 in contact with a bottom surface of the electret layer (13). A microgap between ten nanometers and 100 micrometers is established between the vibrating-electrode-insulating film (15a) and electret-insulating layer (14e). A central line average roughness Ra of the vibrating electrode (15b), including a bending, is 1/10 or less of a gap width measured between the bottom surface of the vibrating electrode (15b) and the top surface of the electret layer (13).

Abstract: A semiconductor device which comprises a channel layer formed from a semiconductor channel component material in the form of crystalline micro particles, micro rods, crystalline nano particles, or nano rods, and doped with a semiconductor dopant.

Abstract: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.

Abstract: A phase change memory may transition between two crystalline states. In one embodiment, the phase change material is a chalcogenide which transitions between face centered cubic and hexagonal states. Because these states are more stable, they are less prone to drift than the amorphous state conventionally utilized in phase change memories.

Abstract: The method for fabricating a flat panel display includes performing a first crystallization process to re-crystallize an amorphous silicon layer on a glass substrate to make the amorphous silicon layer become a polysilicon layer, forming a patterned absorbing layer to cover an active area pattern of a driving TFT and to expose portions of the polysilicon layer, performing a second crystallization process to re-crystallization the exposed portions of the polysilicon layer so that the exposed portions of the polysilicon layer has a different grain structure from the grain structure of the driving TFT, removing the patterned absorbing layer, and removing portions of the polysilicon layer to form an active area of the driving TFT and an active area of a switching TFT area in the exposed portions of the polysilicon layer of each sub-pixel.

Abstract: A photoelectric conversion device comprising: a pin-type photoelectric conversion layer constituted of a p-type semiconductor layer, an i-type semiconductor layer and an n-type semiconductor layer, wherein the p-type semiconductor layer contains silicon atoms and nitrogen atoms, which is possible to improve photoelectric conversion efficiency.

Abstract: A liquid crystal apparatus is provided wherein the liquid crystal layer comprises a section formed by polymerizing a polymerizable compound in the presence of a liquid crystal by selectively irradiating active energy rays onto the substrate surface when no voltage is applied, or alignment control layers and bumps are formed by polymerizing a polymerizable compound which is added to said liquid crystal, or first electrodes with a vertical alignment control film and a second electrode with a horizontal alignment control film face each other and alignment control of the liquid crystal is performed by irradiating light from a direction tilted from the normal line direction on said liquid crystal display apparatus. A liquid crystal display apparatus which can implement high transmittance, high-speed response and a wide viewing angle can be provided.

Abstract: Disclosed is a semiconductor light emitting device comprising a seed layer, a first conductive semiconductor layer into which the seed layer is partially inserted, a first electrode electrically connected to the first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, and a second electrode layer under the second conductive semiconductor layer.

Abstract: Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotataing element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points.

Abstract: For avoiding the metallic inner surface of a PECVD reactor to influence thickness uniformity and quality uniformity of a ?c-Si layer (19) deposited on a large-surface substrate, (15) before each substrate is single treated at least parts of the addressed wall are precoated with a dielectric layer (13).

Abstract: Thin, smooth silicon-containing films are prepared by deposition methods that utilize a silicon containing precursor. In preferred embodiments, the methods result in Si-containing films that are continuous and have a thickness of about 150 ? or less, a surface roughness of about 5 ? rms or less, and a thickness non-uniformity of about 20% or less. Preferred silicon-containing films display a high degree of compositional uniformity when doped or alloyed with other elements. Preferred deposition methods provide improved manufacturing efficiency and can be used to make various useful structures such as wetting layers, HSG silicon, quantum dots, dielectric layers, anti-reflective coatings (ARC's), gate electrodes and diffusion sources.

Abstract: The semiconductor device of the present invention includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.

Abstract: A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.

Abstract: Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to the second wafer to form at least one CMOS device. Another embodiment includes a number of DRAM capacitors formed on a first wafer and support circuitry associated with the DRAM capacitors formed on a second wafer, with the first wafer being bonded and electrically coupled to the second wafer to form a number of DRAM cells. Another embodiment includes a first wafer having a number of vertical transistors coupled to a data line and a second wafer having amplifier circuitry associated with the number of vertical transistors, with the first wafer being bonded and electrically coupled to the second wafer.

Abstract: A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.

Abstract: The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.

Abstract: This invention provides a selfsupporting substrate which consists of a n-type conductive aluminum nitride semiconductor crystal and is useful for manufacturing the vertical conductive type AlN semiconductor device. The n-type conductive aluminum nitride semiconductor crystal, by which the selfsupporting substrate is made up, contains Si atom at a concentration of 1×1018 to 5×1020 cm?3, is substantially free from halogen atoms, and substantially does not absorb the light having the energy of not more than 5.9 eV. The selfsupporting substrate can be obtained by a method comprising the steps of forming an AlN crystal layer on a single crystal substrate such as a sapphire by the HVPE method, preheating the obtained substrate having the AlN crystal layer to a temperature of 1,200° C. or more, forming a second layer consisting of the n-type conductive aluminum nitride semiconductor crystal is formed on the AlN crystal layer in high rate by the HVPE method and separating the second layer from the obtained laminate.

Abstract: Methods of manufacturing resistors, methods of manufacturing semiconductor devices, and structures thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a transistor material stack over a workpiece and patterning the transistor material stack, forming a gate of a transistor in a first region of the workpiece and leaving a portion of the transistor material stack in a second region of the workpiece. A top portion of the transistor material stack is removed in the second region, and a top portion of the workpiece is removed in the first region proximate the gate of the transistor, forming recessed regions in the workpiece in the first region. A semiconductive material is formed in the recessed regions of the workpiece in the first region and over a portion of the transistor material stack in the second region, forming a resistor in the second region.