Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.

Abstract: High power insulated gate bipolar junction transistors are provided that include a wide band gap semiconductor bipolar junction transistor (“BJT”) and a wide band gap semiconductor MOSFET that is configured to provide a current to the base of the BJT. These devices further include a minority carrier diversion semiconductor layer on the base of the BJT and coupled to the emitter of the BJT, the minority carrier diversion semiconductor layer having a conductivity type opposite the conductivity type of the base of the BJT and forming a heterojunction with the base of the BJT.

Abstract: An original wafer, typically silicon, has the form of a desired end PV wafer. The original may be made by rapid solidification or CVD. It has small grains. It is encapsulated in a clean thin film, which contains and protects the silicon when recrystallized to create a larger grain structure. The capsule can be made by heating a wafer in the presence of oxygen, or steam, resulting in silicon dioxide on the outer surface, typically 1-2 microns. Further heating creates a molten zone in space, through which the wafer travels, resulting in recrystallization with a larger grain size. The capsule contains the molten material during recrystallization, and protects against impurities. Recrystallization may be in air. Thermal transfer through backing plates minimizes stresses and defects. After recrystallization, the capsule is removed.

Abstract: A thin film transistor array panel, in which a middle storage electrode and a storage electrode overlapping a drain electrode of a thin film transistor thereby forming a storage capacitance are formed. Accordingly, sufficient storage capacitance may be formed without a decrease of the aperture ratio and fight transmittance of a liquid crystal display. Also, the capacitance may be sufficiently formed through the connecting member connected to a gate metal layer.

Abstract: In embodiments of the invention, a method of forming a monolithic three-dimensional memory array is provided, the method including forming a first memory level that includes a plurality of memory cells, each memory cell comprising a plurality of conductors comprising aluminum or copper, and forming a silicon diode in each memory cell, wherein the silicon diode is formed at temperatures compatible with the conductors. The silicon diode may be formed using a hot wire chemical vapor deposition technique, for example. Other aspects are also described.

Abstract: A photoconductive device (2) comprises a plurality of photoconductive layers (6, 8, 10, 12), each photoconductive layer comprising photoconductive material (4) and a respective plurality of electrodes (16, 18), wherein the photoconductive layers (6, 8, 10, 12) are electrically connected together.

Abstract: A semiconductor device has an integrated passive device (IPD) formed over a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed over the first side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed over the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed over the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed over the substrate and electrically connects the conductive layer to a ground point.

Abstract: A bipolar transistor at least includes a semiconductor substrate including an N? epitaxial growth layer and a P? silicon substrate, an N+ polysilicon layer, a tungsten layer, two silicide layers, a base electrode, an emitter electrode, and a collector electrode. The N+ polysilicon layer formed on the semiconductor substrate is covered with one of the silicide layers. The tungsten layer that is formed on the silicide layer is covered with the other silicide layer.

Abstract: A switching element for a memory device includes a base layer including a plurality of line-type trenches. First insulation patterns are formed on the base layer excluding the trenches. First diode portions are formed on the bottoms of the trenches in the form of a thin film. Second insulation patterns are formed on the first diode portions and are spaced apart from each other to form holes in the trenches having the first diode portions provided therein. Square pillar-shaped second diode portions are formed in the holes over the first diode portions.

Abstract: A rectifier is formed by forming a first electrode layer, a semiconductor layer and a second electrode layer. A third electrode layer is formed between the first electrode layer and the semiconductor layer, or between the second electrode layer and the semiconductor layer. The semiconductor layer and the third electrode layer are formed as follows. First, a first layer made from amorphous silicon and including a p-type first semiconductor region and an n-type second semiconductor region is deposited. Next, a second layer made from a metal is deposited on an upper or lower layer of the first layer. The third electrode layer including a metal silicide as a material lattice-matched to polysilicon is formed by siliciding the second layer. Next, the first layer is crystallized. Subsequently, the semiconductor layer is formed by activating an impurity included in the first layer and restoring crystal imperfections included in the first layer.

Abstract: A diode structure includes: a lower electrode and an insulating layer disposed on the lower electrode. The insulating layer includes aperture exposing a portion of the lower electrode. The diode structure further includes: a first layer and a second layer. The first layer is disposed in the aperture and having a depressed portion. The second layer is disposed in the depressed portion of the first layer. A resistive random access memory (RRAM) device includes the above-described diode structure.

Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes a semiconductor substrate and a temperature sensing diode that is disposed on a surface part of the semiconductor substrate. A relation between a forward current flowing through the temperature sensing diode and a corresponding voltage drop across the temperature sensing diode varies with temperature. The semiconductor apparatus further includes a capacitor that is coupled with the temperature sensing diode, configured to reduce noise to act on the temperature sensing diode, and disposed such that the capacitor and the temperature sensing diode have a layered structure in a thickness direction of the semiconductor substrate.

Abstract: The invention relates to a semiconductor fuse structure comprising a substrate (1) having a surface, the substrate (1) having a field oxide region (3) at the surface, the fuse structure further comprising a fuse body (FB), the fuse body (FB) comprising polysilicon (PLY), the fuse body (FB) lying over the field oxide region (3) and extending into a current-flow direction (CF), wherein the fuse structure is programmable by means of leading a current through the fuse body (FB), wherein the fuse body (FB) has a tensile strain in the current-flow direction (CF) and a compressive strain in a direction (Z) perpendicular to said surface of the substrate (1). The invention further relates to methods of manufacturing such a semiconductor fuse.

Abstract: Deep via trenches and deep marker trenches are formed in a bulk substrate and filled with a conductive material to form deep conductive vias and deep marker vias. At least one first semiconductor device is formed on the first surface of the bulk substrate. A disposable dielectric capping layer and a disposable material layer are formed over the first surface of the bulk substrate. The second surface, located on the opposite side of the first surface, of the bulk substrate is polished to expose and planarize the deep conductive vias and deep marker vias, which become through-substrate vias and through-substrate alignment markers, respectively. At least one second semiconductor device and second metal interconnect structures are formed on the second surface of the bulk substrate. The disposable material layer and the disposable dielectric capping layer are removed and first metal interconnect structures are formed on the first surface.

Abstract: The present invention relates to multicrystalline p-type silicon wafers with high lifetime. The silicon wafers contain 0.2-2.8 ppma boron and 0.06-2.8 ppma phosphorous and/or arsenic and have been subjected to phosphorous diffusion and phosphorous gettering at a temperature of above 925° C. The invention further relates to a method for production of such multicrystalline silicon wafers and to solar cells comprising such silicon wafers.

Abstract: A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while baring the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line.

Abstract: A polycrystalline silicon thin film to be used in display devices, the thin film comprising adjacent primary grain boundaries that are not parallel to each other and do not contact each other, wherein an area surrounded by the primary grain boundaries is larger than 1 ?m2, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.

Abstract: A method for reclaiming a surface of a substrate, wherein the surface, in particular a silicon surface, comprises a protruding residual topography, comprising at least the layer of a first material. By providing a filling material in the non-protruding areas of the surface of the substrate and the subsequent polishing, the reclaiming can be carried out such that the material consuming double-sided polishing step used in the prior art is no longer necessary.

Abstract: A transparent organic thin film transistor, which contains a p-type organic semiconductor material employed in a semiconductor active layer of the transparent organic thin film transistor, wherein the p-type organic semiconductor material has a maximum absorbance of 0.2 or less in a visible range of 400 to 700 nm, in which the maximum absorbance is determined in the case where the thin film is made to have a film thickness of 30 nm.

Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor including a gate electrode, an active layer, an ohmic contact layer, a buffer metallic layer, a source electrode and a drain electrode, the thin film transistor being electrically connected to the gate line and the data line and a pixel electrode in the pixel region and connected to the thin film transistor, wherein the active layer is disposed over and within the gate electrode.

Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.

Abstract: An electronic device of the present invention includes a first substrate provided with a thin film active element, having a thickness of 200 ?m or lower, and a second substrate formed with a high thermal conductivity portion. The second substrate is applied to one surface of the two surfaces of the first substrate, i.e., the surface being the side other than the side that formed with the thin film active element. The thin film active element has a maximum power consumption of 0.01 to 1 mW. The high thermal conductivity portion is a region that corresponds to the position of the thin film active element and whose thermal conductivity falls within the range from 0.1 to 4 W/cm·deg.

Abstract: A semiconductor device has an IC chip with a thickness of equal to or less than 100 ?m and includes a semiconductor substrate. A device forming region is within the depth of approximately equal to or less than 5 ?m from a surface of the semiconductor substrate, and a total thickness of the semiconductor substrate is from 5 ?m to 100 ?m. A BMD layer for carrying out gettering of metal impurities is provided immediately under the device forming region. Since a gettering site is provided immediately under the device forming region, in a device or the like of which extreme thinness is required, degradation of device characteristics and reliability due to contamination of metal impurities can be prevented, and stabilize and improve the device yield.

Abstract: In a vertical diode, an N+-type layer, an N?-type layer, and a P+-type layer are stacked in this order on a lower electrode film, and an upper electrode film is provided thereon. The effective impurity concentration of the N?-type layer is lower than the effective impurity concentrations of the N+-type layer and the P+-type layer. At least one of the N+-type layer, the N?-type layer, and the P+-type layer is formed from a small grain size polycrystalline semiconductor whose each crystal grain does not penetrate each layer through its thickness.

Abstract: A bipolar junction transistor and a method of manufacturing a bipolar junction transistor are disclosed. An exemplary bipolar junction transistor includes a second conductivity type base region in a first conductivity type substrate, step-shaped recesses in the base region, a polysilicon layer doped with a first conductivity type impurity in the step-shaped recesses, and a step-shaped emitter region between the polysilicon layer and the base region.

Abstract: To provide a semiconductor device with high performance and low cost and a manufacturing method thereof. A first region including a separated (cleavage) single-crystal semiconductor layer and a second region including a non-single-crystal semiconductor layer are provided over a substrate. It is preferable that laser beam irradiation be performed to the separated (cleavage) single-crystal semiconductor layer in an inert atmosphere, and laser beam irradiation be performed to the non-single-crystal semiconductor layer in an air atmosphere at least once.

Abstract: The present invention relates to a method for obtaining enlarged Cu grains in small trenches. More specifically it related to a method for creating enlarged copper grains or inducing super secondary grain growth in electrochemically deposited copper in narrow trenches and/or vias to be used in semiconductor devices.

Abstract: A TFT and the like capable of realizing performances such as a low threshold voltage value, high carrier mobility and a low leak current easily. A TFT consists of a polycrystalline Si film having a small heat capacity part and a large heat capacity part, and the small heat capacity part is used at least as a channel part. The polycrystalline Si film is formed of a crystal grain film through laser annealing of an energy density with which the small heat capacity part melts completely but the large heat capacity part does not melt completely. Since the channel part is formed of large crystal grains grown from the boundaries between the small heat capacity part and the large heat capacity parts, it is possible to realize performances such as a low threshold voltage value, high carrier mobility and a low leak current by using a typical laser annealing device.

Abstract: A two-terminal memory cell including a Schottky metal-semiconductor contact as a non-ohmic device (NOD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The NOD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The NOD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.

Abstract: An epitaxial wafer and method for fabricating the same can prevent a bowing phenomenon of the epitaxial wafer. The epitaxial wafer includes a substrate configured to be doped in a first doping concentration; an epitaxial layer configured to be formed over a first side of the substrate and doped in a second doping concentration lower than the first doping concentration; and a back seal layer configured to be formed over a second side of the substrate and include a layer having a tensile stress, wherein the second side is opposite to the first side, of the substrate.

Abstract: A three-dimensional thin-film semiconductor substrate having a plurality of ridges on the surface of the semiconductor substrate which define a base opening of an inverted pyramidal cavity and walls defining the inverted pyramidal cavity is provided. And a fabrication method for a 3-D TFSS by forming a porous silicon layer on a silicon template having a top surface aligned along a (100) crystallographic orientation plane of the silicon template and a plurality of walls each aligned along a (111) crystallographic orientation plane of the silicon template and forming an inverted pyramidal cavity. The porous silicon layer forms substantially conformal on the silicon template. Then forming a substantially conformal epitaxial silicon layer on the porous silicon layer and releasing the epitaxial silicon layer from the silicon template.

Abstract: Affords GaN epitaxial wafers designed to improve production yields, as well as semiconductor devices utilizing such GaN epitaxial wafers, and methods of manufacturing such GaN epitaxial wafers and semiconductor devices. A GaN epitaxial wafer manufacturing method involving the present invention includes a first GaN layer formation step of epitaxially growing a first GaN layer onto a substrate, a pit formation step, following the first GaN layer formation step, of forming pits in the front side of the substrate, and a second GaN layer formation step, following the pit-formation step, of epitaxially growing a second GaN layer onto the first GaN layer, and therefore controls cracking to a minimum and improves production yields.

Abstract: Provided are nanocrystal silicon layer structures formed using a plasma deposition technique, methods of forming the same, nonvolatile memory devices including the nanocrystal silicon layer structures, and methods of fabricating the nonvolatile memory devices. A method of forming a nanocrystal silicon layer structure includes forming a buffer layer on a substrate and forming a nanocrystal silicon layer on the buffer layer by a plasma deposition technique using silicon (Si)-containing gas and hydrogen (H2)-containing gas. In this method, the nanocrystal silicon layer can be directly deposited on a glass substrate using plasma vapor deposition without performing a post-processing process so that the fabrication of a nonvolatile memory device can be simplified, thereby reducing fabrication cost.

Abstract: A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer insulating layer covering the data line and the drain electrode on the gate insulating layer, forming a first opening in the interlayer insulating layer, forming an organic semiconductor in the first opening, forming a passivation layer on the organic semiconductor and the interlayer insulating layer, and forming a second opening in the interlayer insulating layer to expose the pixel electrode.

Abstract: A sensor includes at least one micro-patterned diode pixel that has a diode implemented in, on, or under a diaphragm, and the diaphragm in turn being implemented above a cavity. The diode is contacted via supply leads that are implemented at least in part in, on, or under the diaphragm, and the diode is implemented in a polycrystalline semiconductor layer. The diode is implemented by way of two low-doped diode regions or at least one low-doped diode region. At least parts of the supply leads are implemented by way of highly doped supply lead regions of the shared polycrystalline semiconductor layer.

Abstract: A semiconductor device includes an organic semiconductor layer 10 and an oxide semiconductor layer 11, and emits light.

Abstract: Provided is a 2-terminal semiconductor device that uses an abrupt MIT semiconductor material layer. The 2-terminal semiconductor device includes a first electrode layer, an abrupt MIT semiconductor organic or inorganic material layer having an energy gap less than 2eV and holes in a hole level disposed on the first electrode layer, and a second electrode layer disposed on the abrupt MIT semiconductor organic or inorganic material layer. An abrupt MIT is generated in the abrupt MIT semiconductor material layer by a field applied between the first electrode layer and the second electrode layer.

Abstract: A semiconductor device has a MOS transistor that has a gate connected to a first terminal, a source connected to a second terminal and a drain connected to a third terminal, a first polysilicon diode that has an anode connected to the first terminal, a first single-crystalline silicon diode that is connected to a cathode of the first polysilicon diode at a cathode thereof and to the second terminal at an anode thereof, has a reverse breakdown voltage lower than a reverse breakdown voltage of the first polysilicon diode, a second polysilicon diode that has a cathode connected to the first terminal and a second single-crystalline silicon diode that is connected to an anode of the second polysilicon diode at an anode thereof and to the third terminal at a cathode thereof, has a reverse breakdown voltage lower than a reverse breakdown voltage of the second polysilicon.

Abstract: To improve a transmission rate of an antireflection film, the antireflection film includes: a first silicon oxide film (2), which is formed on a silicon substrate (1); a polysilicon film (3), which is formed on the first silicon oxide film (2) to a thickness of 6 nm through 14 nm; and a second silicon oxide film (4), which is formed on the polysilicon film (3). The transmission rate of the antireflection film is further improved if a thickness of the first silicon oxide film (2) is set to 14 nm through 35 nm. When used in a photoelectric conversion element for such as a solid state image sensor and a photovoltaic generator, the antireflection film may enhance efficiency of photoelectric conversion.

Abstract: Provided are a transistor and a method of manufacturing the transistor, and more particularly, a vacuum channel transistor emitting thermal cathode electrons and a method of manufacturing the vacuum channel transistor. The vacuum channel transistor includes: a motherboard; a micro heater member having a thin-film structure formed on the motherboard; a cathode member having a thin-film structure spaced apart from a center part of the micro heater member by a first interval and formed on the micro heater member; a gate member formed on both outer walls of upper parts of the cathode member; and an anode member spaced apart from the cathode member by a second interval through spacers disposed on the gate member, wherein a vacuum electron passing area is interposed between the cathode member and the anode member by the second interval.

Abstract: A metallic element is effectively removed from a semiconductor film crystallized by using the metallic element. The concentration distribution of phosphorous or antimony in the depth direction of at least one of a source and a drain of a TFT semiconductor film has: a region in which the concentration is 1×1020 atoms/cm3 or less is 5 nm or greater in thickness, and 5×1019 atoms/cm3 or greater in the maximum value. By creating this concentration distribution, and by thermal annealing at about between 500 and 650° C., the metallic element within a channel forming region diffuses to the source or the drain, and at the same time as gettering is accomplished, the region in which the concentration is 1×1020 atoms/cm3 or less is made into a nucleus and the source region/drain region is recrystallized.

Abstract: A method of fabrication of a semiconductor device having low resistance in an interconnection line and the same coefficient of thermal expansion as a semiconductor substrate is disclosed. The method includes forming a nitride film over a semiconductor substrate including a bottom metal line and a top metal line connected to each other through a plurality of vias, forming a trench at a through-silicon via (TSV) region of the semiconductor substrate, filling the trench with a predetermined material to form a silicon film, exposing the silicon film using a photoresist pattern, ion-implanting a dopant into the exposed silicon film, and selectively performing laser annealing to the silicon film to diffuse only the dopant implanted into the silicon film.

Abstract: A nonvolatile memory device includes: a substrate; a stacked structure member including a plurality of dielectric films and a plurality of electrode films alternately stacked on the substrate and including a through-hole penetrating through the plurality of the dielectric films and the plurality of the electrode films in a stacking direction of the plurality of the dielectric films and the plurality of the electrode films; a semiconductor pillar provided in the through-hole; and a charge storage layer provided between the semiconductor pillar and each of the plurality of the electrode films. At least one of the dielectric films includes a film generating one of a compressive stress and a tensile stress, and at least one of the electrode films includes a film generating the other of the compressive stress and the tensile stress.

Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved.

Abstract: A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0×1017 atoms/cm3 and with a diameter of a COP occurring region not more than a diameter of a crystal, slicing a wafer from the silicon ingot after doping the silicon ingot with phosphorus, forming a polysilicon layer or a strained layer on one main surface of the wafer, and mirror polishing the other main surface of the wafer.

Abstract: A thin film transistor array substrate having a high charge mobility and that can raise a threshold voltage, and a method of fabricating the thin film transistor array substrate are provided. The thin film transistor array substrate includes: an insulating substrate; a gate electrode formed on the insulating substrate; an oxide semiconductor layer comprising a lower oxide layer formed on the gate electrode and an upper oxide layer formed on the lower oxide layer, such that the oxygen concentration of the upper oxide layer is higher than the oxygen concentration of the lower oxide layer; and a source electrode and a drain electrode formed on the oxide semiconductor layer and separated from each other.

Abstract: A poly-emitter type bipolar transistor includes a buried layer formed over an upper portion of a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a collector area formed on the epitaxial layer and connected to the buried layer, a base area formed at a part of an upper portion of the epitaxial layer, and a poly-emitter area formed on a surface of the semiconductor substrate in the base area and including a polysilicon material. A BCD device includes a poly-emitter type bipolar transistor having a poly-emitter area including a polysilicon material and at least one of a CMOS and a DMOS formed on a single wafer together with the poly-emitter type bipolar transistor.

Abstract: A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

Abstract: A nitride-based semiconductor device is provided. The nitride-base semiconductor device includes a substrate comprising one or more locally etched regions and a buffer layer comprising one or multiple InAlGaN layers on the substrate. A channel layer includes GaN on the buffer layer. A barrier layer includes one or multiple AlGaN layers on the channel layer.

Abstract: A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.