Abstract: The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relative to one another. The invention also includes methods of patterning photoresist in which a saturable absorption layer is provided between the photoresist and a topography with surfaces of differing reflectivity, and in which the differences in reflectivity are utilized to enhance the accuracy with which an image is photolithographically formed in the photoresist.

Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

Abstract: Described herein are methods of forming dielectric films comprising silicon, oxide, and optionally nitrogen, carbon, hydrogen, and boron. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer.

Abstract: A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package.

Abstract: Method for producing semiconductor components with a contact structure having a high aspect ratio comprising the following steps: providing an essentially plane semiconductor substrate having a first side and a second side, applying a mask onto at least a first partial area on at least one of the sides of the semiconductor substrate and applying a contact structure onto at least a second partial area, which is different from first partial area, on at least one of the sides of semiconductor substrate.

Abstract: A component for an information display device has a transparent substrate having a surface that has a first refractive index. The surface is selectively coated in a pattern comprising a transparent electrically conductive layer disposed at least at a first region of the surface and at a second region of the surface. The first region of the surface is separated from the second region by a third region that is devoid of the transparent conductive layer. The transparent conductive layer has a second refractive index that is higher than the first refractive index. The first, second and third regions are commonly overcoated with a transparent layer comprising non-conductive nanoparticles, the overcoating layer being disposed over the transparent conductive layer at the first and second regions and also disposed over the third region that is devoid of the transparent conductive layer. The refractive index of the layer comprising nanoparticles is higher than the first refractive index.

Abstract: According one embodiment, a film forming apparatus includes a stage, a coating section, a vapor supply section, a blower section, and a controller. On the stage, an coating target is placed. The coating section applies a material to a predetermined region on the coating target placed on the stage to form a coating film. The vapor supply section generates solvent vapor capable of dissolving the coating film. The blower section blows the solvent vapor generated by the vapor supply section onto the coating film on the coating target placed on the stage. The controller controls an amount of the solvent vapor to be blown by the blower section so that: the coating film is dissolved; viscosity in a part of the coating film on a surface layer side is lower than that in a part thereof on the coating target side; and the viscosity in the part on the surface layer side and the viscosity of the coating target side take such values that prevent the coating film on the coating target from spreading.

Abstract: A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile film. The ILD layer further includes a low-k dielectric layer, and the single tensile film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer.

Abstract: The present invention is a process for spin-on deposition of a silicon dioxide-containing film under oxidative conditions for gap-filling in high aspect ratio features for shallow trench isolation used in memory and logic circuit-containing semiconductor substrates, such as silicon wafers having one or more integrated circuit structures contained thereon, comprising the steps of: providing a semiconductor substrate having high aspect ratio features; contacting the semiconductor substrate with a liquid formulation comprising a low molecular weight aminosilane; forming a film by spreading the liquid formulation over the semiconductor substrate; heating the film at elevated temperatures under oxidative conditions. Compositions for this process are also set forth.

Abstract: According to one aspect of the present invention, there is provided a composition for film formation, comprising a compound represented by general formula (I) or a hydrolyzed-dehydrocondensation product thereof: X13-mR1mSiR2SiR3nX23-n??(I) wherein R1 and R3 represent a hydrogen atom or a monovalent substituent; R2 represents a divalent group having an alicyclic structure with four carbon atoms or a derivative of the divalent group; X1 and X2 represent a hydrolysable group; and m and n are an integer of from 0 to 2.

Abstract: Apparatus and methods are disclosed herein for fabricating semiconductor device features with a half-pitch node of 22 nm and beyond using single exposure and single etch (1P1E) photolithography techniques. The method includes exposing in a single exposure a photoresist layer to the exposure source through a photolithography mask where the photolithography mask has on it an island pattern of a material having high percentage transmission. The photoresist layer is developed using a negative tone developer to form a hole pattern in the photoresist layer. The 1P1E does not require the second photo exposure of the double patterning method. Furthermore, the method circumvents the island pattern collapsing issues and the need for strong illumination associated with exiting single 1P1E processes.

Abstract: A metal substrate with an insulation layer has a metallic substrate having at least an aluminum base, and an insulation layer formed on the aluminum base of the metallic substrate. The insulation layer is a anodized film of aluminum that has a porous structure having plural pores and a Martens hardness of 1000 N/mm2 to 3500 N/mm2. A ratio of an average pore size of the plural pores to an average wall thickness of the plural pores ranges from 0.2 to 0.5.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: An oxide film formation method comprises steps of: generating a plasma from a gas mixture containing an inert gas and an oxidizing gas whose mixing ratio to the inert gas is higher than 0, and is 0.007 or lower; and forming an oxide film on a surface of a silicon substrate by using the plasma.

Abstract: The invention relates to a method for producing metal oxide layers from oxides of rare earth metals on silicon-containing surfaces, to the device used to carry out the coating method, and to the use of the starting materials used in the method according to the invention for the coating method.

Abstract: It is an object of the present invention to provide a high-performance and high reliable semiconductor device and to provide a technique of manufacturing the semiconductor device at low cost with high yield. The semiconductor device is manufactured by steps of forming a first conductive layer, forming a first liquid-repellent layer over the first conductive layer, discharging a composition containing a material for a mask layer over the first liquid-repellent layer to form a mask layer, processing the first liquid-repellent layer with the use of the mask layer, forming a second liquid-repellent layer, forming an insulating layer over the first conductive layer and the second conductive layer, and forming a second conductive layer over the insulating layer.

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor as a first precursor and a hydrocarbon gas as a second precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film doped with carbon and having Si—N bonds on the substrate.

Abstract: A modifier for lowering relative dielectric constant of a low dielectric constant film used in semiconductor devices, the modifier of the low dielectric constant film being characterized in that it contains as an effective component a silicon compound represented by formula (1) R3-nHnSiN3??(1) in which R is a C1-C4 alkyl group, and n is an integer from 0 to 3.

Abstract: The invention relates to a method for producing passivation layers on crystalline silicon by a) coating the silicon with a solution containing at least one polysilazane of the general formula (1): —(SiR?R?—NR??)-n, wherein R?, R?, R?? are the same or different and stand independently of each other for hydrogen or a possibly substituted alkyl, aryl, vinyl, or (trialkoxysilyl)alkyl group, wherein n is an integer and n is chosen such that the polysilazane has a number average molecular weight of 150 to 150,000 g/mol, b) subsequently removing the solvent by evaporation, whereby polysilazane layers of 50-500 nm thickness remain on the silicon wafer, and c) heating the polysilazane layer at normal pressure to 200-1000° C. in the presence of air or nitrogen, wherein upon tempering the ceramic layers release hydrogen for bulk passivation of the silicon.

Abstract: The present disclosure is related to a dielectric layer comprising a rare-earth aluminate (RExAl2-xO3 with 0<x<2) and having a perovskite crystalline structure, wherein the rare-earth aluminate comprises a rare-earth element having an atomic number higher than or equal to 63 and lower than or equal to 71. The disclosure also relates to method of manufacturing of a dielectric stack and a dielectric stack comprising said rare-earth aluminate dielectric layer and further comprising a template stack comprising at least an upper template layer, wherein the upper template layer has a perovskite structure, and wherein the upper template layer is underlying and in contact with the rare-earth aluminate dielectric layer. In a preferred embodiment the dielectric stack further comprises a lower template layer having a crystalline structure, wherein the lower template layer is underlying and in contact with the upper template layer.

Abstract: A semiconductor device includes a plurality of first MIS transistors and a plurality of second MIS transistors formed on a semiconductor substrate and a liner insulating film applying stress along the gate length direction. Each of the first MIS transistors includes first L-shaped sidewalls each having an L-shaped cross-sectional shape, and each of the second MIS transistors includes second L-shaped sidewalls each having an L-shaped cross-sectional shape and outer sidewalls. The minimum thickness of a part of the liner insulating film located on each of second source/drain regions of the second MIS transistor is larger than the minimum thickness of a part thereof located on each of first source/drain regions of the first MIS transistor.

Abstract: A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane surface. An atomically stable two dimensional crystalline film resides on the epitaxial insulating layer with a coincident lattice match to the insulating interlayer. Methods of fabrication are disclosed. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: Polymers for extreme ultraviolet and 193 nm photoresists are disclosed. The polymers comprise a photoacid generator (PAG) residue, an acid cleavable residue and a diacid joined by ester linkages. The polymers include a photoacid generating diol, a diacid and an acid table diol.

Abstract: A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.

Abstract: A photosensitive adhesive composition that comprises (A) a resin with a carboxyl and/or hydroxyl group, (B) a thermosetting resin, (C) a radiation-polymerizable compound and (D) a photoinitiator, wherein the 3% weight reduction temperature of the entire photoinitiator mixture in the composition is 200° C. or greater.

Abstract: A structure for memorizing tensile stress in a semiconductor device includes a gate electrode of the semiconductor device; a silicon spacer adjacent to the gate electrode; and a capping layer encapsulating the gate electrode and the silicon spacer, wherein the silicon spacer and capping layer are configured to cause a tensile stress to be memorized in the gate electrode during an annealing process. A method for memorizing tensile stress in a semiconductor device includes forming a silicon spacer adjacent to a gate electrode of the semiconductor device; forming a capping layer over the silicon spacer and the gate electrode; and annealing the semiconductor device, wherein the silicon spacer and capping layer cause a tensile stress to be memorized in the gate electrode during annealing. A disposable silicon spacer is configured to induce a tensile stress in a semiconductor device during a stress memorization technique process.

Abstract: A resist pattern thickening material containing a resin, a cyclic compound expressed by the general formula 1, at least one of compounds expressed by the general formulae 2 to 3, respectively, and water:

Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.

Abstract: Techniques for obtaining a wiring layer with a high TDDB resistance and little leakage current, and accordingly, for manufacturing a highly reliable semiconductor device with a small electric power consumption are provided, in which an interfacial roughness reducing film is formed which is in contact with an insulator film and also in contact with a wiring line on the other side surface thereof, and has an interfacial roughness between the wiring line and the interfacial roughness reducing film smaller than that between the insulator film and the interfacial roughness reducing film.

Abstract: A method of producing an epitaxial wafer, comprising: implanting oxygen ions from a surface of a silicon wafer, thereby forming an ion implanted layer in a surface layer of the silicon wafer; after forming the ion implanted layer, implanting boron ions from the surface of the silicon wafer to the whole area in the ion implanted layer; performing heat treatment of the silicon wafer after implanting boron ions, thereby forming a thinning-stopper layer including a mixture of silicon particles, silicon oxides, and boron, and forming an active layer in the silicon wafer on the surface side of the thinning-stopper layer; and forming an epitaxial layer on the surface of the silicon wafer after the heat treatment.

Abstract: A wiring structure of a semiconductor device or the like includes an interlayer insulating film having a fluorocarbon film formed on an underlayer, and a conductor buried in the interlayer insulating film. The fluorocarbon film contains nitrogen and is low in dielectric constant, excellent in reproducibility and stable.

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.

Abstract: The present invention provides a semiconductor device having a low-k film including an interconnect layer and a highly-reliable through-substrate contact plug. The semiconductor device includes: a semiconductor substrate having a first surface and a second surface facing each other; a first insulating film formed on the first surface of the semiconductor substrate and having a specific permittivity of 4 or higher; a circuit constituent element formed on the first surface of the semiconductor substrate and covered with the first insulating film); a contact plug formed in the first insulating film and electrically connected to the circuit constituent element; a through-substrate contact plug penetrating through the semiconductor substrate and the first insulating film; a second insulating film formed on the first insulating film and having a specific permittivity of 3.

Abstract: Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.

Abstract: A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile hydrophobic film. The ILD layer further includes a low-k dielectric layer, and the single tensile hydrophobic film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer.

Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.

Abstract: This invention provides a silver thick film paste composition comprising a silver powder comprising silver particles, each said silver particle comprising silver components 100-2000 nm long, 20-100 nm wide and 20-100 nm thick assembled to form a spherically-shaped, open-structured particle, wherein the d50 particle size is from about 2.5 ?m to about 6 ?m. There is also provided a method of making a semiconductor device, and in particular a solar cell, using the silver thick film paste composition to form a front side electrode.

Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

Abstract: A chemical vapor deposition material includes an organosilane compound shown by the following general formula (1). wherein R1 and R2 individually represent a hydrogen atom, an alkyl group having 1 to 4 carbon atoms, a vinyl group, or a phenyl group, R3 and R4 individually represent an alkyl group having 1 to 4 carbon atoms, an acetyl group, or a phenyl group, m is an integer from 0 to 2, and n is an integer from 1 to 3.

Abstract: A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.

Abstract: There are provided a method of manufacturing a semiconductor device, a substrate processing apparatus, and a semiconductor device. The method allows rapid formation of a conductive film, which has a low concentration of impurities permeated from a source owing to its dense structure, and a low resistivity. The method is performed by simultaneously supplying two or more kinds of sources into a processing chamber to form a film on a substrate placed in the processing chamber. The method comprises: performing a first source supply process by supplying at least one kind of source into the processing chamber at a first supply flow rate; and performing a second source supply process by supplying the at least one kind of source into the processing chamber at a second supply flow rate different from the first supply flow rate.

Abstract: The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration.

Abstract: Disclosed is a composition comprising a hydrolysate of an alkoxysilane compound, a hydrolysate of a siloxane compound represented by Formula (1), a surfactant, and an element having an electronegativity of 2.5 or less. In Formula (1), RA and RB independently represent a hydrogen atom, a phenyl group, —CaH2a+1, —(CH2)b(CF2)cCF3 or —CdH2d?1, RA and RB are not both hydrogen atoms simultaneously, RC and RD independently represent a single bond that links a silicon atom and an oxygen atom to form a cyclic siloxane structure, or each independently represent a hydrogen atom, a phenyl group, —CaH2a+1, —(CH2)b(CF2)cCF3, or —CdH2d?1, a represents an integer of 1 to 6, b represents an integer of 0 to 4, c represents an integer of 0 to 10, d represents an integer of 2 to 4, and n represents an integer of 3 or greater.

Abstract: A method is provided for producing a porogen-residue-free ultra low-k film with porosity higher than 50% and a high elastic modulus above 5 GPa. The method starts with depositing a SiCOH film using Plasma Enhanced Chemical Vapor Deposition (PE-CVD) or Chemical Vapor Deposition (CVD) onto a substrate and then first Performing an atomic hydrogen treatment at elevated wafer temperature in the range of 200° C. up to 350° C. to remove all the porogens and then performing a UV assisted thermal curing step.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

Abstract: A dielectric layer is provided. The dielectric layer includes a photo-sensitive polymer or a non-photo-sensitive polymer and an amorphous metal oxide disposed in the photo-sensitive polymer or a non-photo-sensitive polymer.

Abstract: A dense boron-based or phosphorus-based dielectric material is provided. Specifically, the present invention provides a dense boron-based dielectric material comprised of boron and at least one of carbon, nitrogen, and hydrogen or a dense phosphorus-based dielectric comprised of phosphorus and nitrogen. The present invention also provides electronic structures containing the dense boron-based or phosphorus-based dielectric as an etch stop, a dielectric Cu capping material, a CMP stop layer, and/or a reactive ion etching mask in a ULSI back-end-of-the-line (BEOL) interconnect structure. A method of forming the inventive boron-based or phosphorus-based dielectric as well as the electronic structure containing the same are also described in the present invention.

Abstract: A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.