Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

Abstract: Stacked devices and circuits formed by stacked devices are described. In accordance with some embodiments, a semiconductor post extends vertically from a substrate. A first source/drain region is in the semiconductor post. A first gate electrode layer laterally surrounds the semiconductor post and is vertically above the first source/drain region. A first gate dielectric layer is interposed between the first gate electrode layer and the semiconductor post. A second source/drain region is in the semiconductor post and is vertically above the first gate electrode layer. The second source/drain region is connected to a power supply node. A second gate electrode layer laterally surrounds the semiconductor post and is vertically above the second source/drain region. A second gate dielectric layer is interposed between the second gate electrode layer and the semiconductor post. A third source/drain region is in the semiconductor post and is vertically above the second gate electrode layer.

Abstract: Provided is a method for increasing a driving current of a junctionless transistor that includes: a substrate; a source region and a drain region which are formed on the substrate and are doped with the same type of dopant; a nanowire channel region which connects the source region and the drain source and is doped with the same type dopant as that of the source region and the drain region; a gate insulation layer which is formed to surround the nanowire channel region; and a gate electrode which is formed on the gate insulation layer and is formed to surround the nanowire channel region. An amount of current flowing through the nanowire channel region is increased by joule heat generated by applying a voltage to the source region and the drain region.

Abstract: A plasmon-enhanced terahertz graphene-based photodetector exhibits an increased absorption efficiency attained by utilizing a tunable plasmonic resonance in sub-wavelengths graphene micro-ribbons formed on SiC substrate in contact with an array of bi-metallic electrode lines. The orientation of the graphene micro-ribbons is tailored with respect to the array of sub-wavelengths bi-metallic electrode lines. The graphene micro-ribbons extend at the angle of approximately 45 degrees with respect to the electrode lines in the bi-metal electrodes array. The plasmonic mode is efficiently excited by an incident wave polarized perpendicular to the electrode lines, and/or to the graphene micro-ribbons. The absorption of radiation by graphene is enhanced through tunable geometric parameters (such as, for example, the width of the graphene micro-ribbons) and control of a carrier density in graphene achieved through tuning the gate voltage applied to the photodetector.

Abstract: A method is presented for forming a nanosheet structure having a uniform threshold voltage (Vt). The method includes forming a conductive barrier surrounding a nanosheet, forming a first work function conducting layer over the conductive barrier layer, and forming a conducting layer adjacent the first work function conducting layer, the conducting layer defining a first region and a second region. The method further includes forming a second work function conducting layer over the second region of the conducting layer to compensate for threshold voltage offset between the first and second regions of the conducting layer.

Abstract: A method for fabricating a semiconductor nanowire device includes forming a base including a plurality of PMOS regions, forming a plurality of first openings in the base of the PMOS regions, forming a plurality of first epitaxial wires by filling the first openings with a germanium-containing material, and forming a plurality of second openings in the base by etching a portion of the base under each first epitaxial wire. Each first epitaxial wire is connected to both sidewalls of a corresponding second opening and is hung above a bottom surface of the corresponding second opening. The method also includes performing a thermal oxidation treatment process on the plurality of first epitaxial wires to form an oxide layer on each first epitaxial wire, forming a plurality of first nanowires by removing the oxide layer from each first epitaxial wire, and forming a first wrap-gate structure to surround each first nanowire.

Abstract: A method of making a device comprises forming a layer comprising quantum dots over a substrate including a first electrode, fixing the layer comprising quantum dots formed over the substrate, and exposing at least a portion of, and preferably all, exposed surfaces of the fixed layer comprising quantum dots to small molecules. The layer comprising quantum dots can be preferably fixed in the absence or substantial absence of oxygen. Also disclosed is a method of making a device comprises forming a layer comprising quantum dots over a substrate including a first electrode, exposing the layer comprising quantum dots to small molecules and light flux.

Abstract: The present invention provides a method and a system for forming wires (1) that enables a large scale process combined with a high structural complexity and material quality comparable to wires formed using substrate-based synthesis. The wires (1) are grown from catalytic seed particles (2) suspended in a gas within a reactor. Due to a modular approach wires (1) of different configuration can be formed in a continuous process. In-situ analysis to monitor and/or to sort particles and/or wires formed enables efficient process control.

Abstract: An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (Vg) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.

Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.

Abstract: A method of manufacturing a flexible electronic device is provided. The method includes a) filtering a mixture including an electrically conducting nanostructured material through a membrane such that the electrically conducting nanostructured material is deposited on the membrane; b) depositing an elastomeric polymerizable material on the electrically conducting nanostructured material and curing the elastomeric polymerizable material thereby embedding the electrically conducting nanostructured material in an elastomeric polymer thus formed; and c) separating the elastomeric polymer with the embedded electrically conducting nanostructured material from the membrane to obtain the flexible electronic device. Flexible electronic device manufactured by the method, and use of the flexible electronic device are also provided.

Abstract: A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.

Abstract: A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.

Abstract: Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.

Abstract: This disclosure teaches a method for producing a nano metal mesh. A brittle layer can be deposited onto a flexible substrate, the brittle layer having a thickness on the flexible substrate. The flexible substrate can be bent to produce a plurality of gaps on the brittle material. A material can be deposited at the surface of the flexible substrate filling the gaps of the brittle layer. Then, the brittle layer can be etched from the flexible substrate using an etchant, a nano metal mesh formed by the material previously in the gaps. The disclosure also teaches a nano metal mesh made using this method.

Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first top OD region, a first bottom OD region, and a first nanowire. A second GAA transistor includes: a second top OD region, a second bottom OD region, and a second nanowire. The first top OD region, the first bottom OD region, and the first nanowire are symmetrical with the second top OD region, the second bottom OD region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow from the first top OD region to the first bottom OD region, and the second GAA transistor is arranged to provide a second current to flow from the second top OD region to the second bottom OD region.

Abstract: A method for developing a coating having a high light transmission and/or a low light reflection is provided. The method relates to a process for developing a coating with a high light transmission and/or a low light reflection, where the coating is deposited on a substrate. The coating is deposited as a mixed coating comprising a material A and a material B, where the coating is developed to have a coating thickness profile in which the lowest proportion of the material B is on the substrate surface and the highest proportion of coating material is on the coating surface. The material B is at least partially removed from the coating after deposition of the coating on the substrate.

Abstract: An apparatus and method wherein the apparatus comprises: a sensing material configured to produce a non-random distribution of free charges in response to a parameter; an electric field sensor; a first conductive electrode comprising a first area overlapping the sensing material; an insulator provided between the first conductive electrode and the sensing material; a second electrode comprising a second area adjacent the electric field sensor; and a conductive interconnection between the first conductive electrode and the second conductive electrode.

Abstract: A method of forming a semiconductor device having a horizontal gate all around structure on a bulk substrate is provided. The method comprises forming a plurality of fins on a bulk substrate wherein each fin comprises a vertical slice of substrate material and a plurality of channel layers above the vertical slice of substrate material. The plurality of channel layers includes a top channel layer above a bottom channel layer. Each channel layer comprises a first sublayer of removable semiconductor material overlaid by a second sublayer of semiconductor material. The method further comprises providing shallow trench isolation (STI) material between the vertical slices of the bulk substrate in the plurality of fins, depositing poly material around a central portion of the plurality of fins, forming source and drain regions, and forming an interlayer dielectric layer (ILD0).

Abstract: A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-Type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistor includes a germanium nanowire, a III-V compound layer surrounding around the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.

Abstract: Device structures for a field-effect transistor and methods of forming such device structures using a device layer of a silicon-on-insulator substrate. A channel and an isolation region are formed in the device layer. The channel is located beneath a gate structure is formed on the device layer and is comprised of a semiconductor material under strain. A portion of the device layer is located between the first isolation region and the channel. The portion of the device layer is under a strain that is less than the strain in the semiconductor material of the channel.

Abstract: The present invention relates to atomically-thin channel materials with crystallographically uniform interfaces to atomically-thin commensurate graphene electrodes and/or nanoribbons separated by nanogaps that allow for nanoelectronics based on quantum transport effects and having significantly improved contact resistances.

Abstract: Provided is a thermoelectric material satisfying (MX)1+a(TX2)n and having a superlattice structure, wherein M is at least one element selected from the group consisting of Group 13, Group 14, and Group 15, T is at least one element selected from Group 5, X is a chalcogenide element, a is a real number satisfying 0<a<1, and n is a natural number of 1 to 3.

Abstract: A method of forming a semiconductor device and resulting structures having stacked nanosheets with a wrap-around inner spacer by forming a nanosheet stack disposed above a substrate; forming a top sacrificial layer on a top surface of the nanosheet stack; forming a sidewall sacrificial layer on two opposite sidewalls of the nanosheet stack, such that a first and a second end of a first vertically-stacked nanosheet are exposed; removing the sidewall sacrificial layer, a portion of a first and a second end of a first sacrificial layer, and a portion of a first and a second end of a top sacrificial layer to expose portions of the first vertically-stacked nanosheet; and forming an inner spacer region on the first vertically-stacked nanosheet to replace the removed sidewall sacrificial layer, the removed portions of the first sacrificial layer, and the removed portions of the top sacrificial layer.

Abstract: A QD glass cell includes a glass cell and QD fluorescent powder material. The glass cell includes a receiving chamber, and the QD fluorescent powder being encapsulated within the receiving chamber. A manufacturing method of the QD glass cell includes: S101: manufacturing a glass cell comprising a receiving chamber, and the glass cell comprising an injection port transmitting fluid into the receiving chamber; S102: manufacturing fluid QD fluorescent powder material; S103: filling the fluid QD fluorescent powder material into the receiving chamber via the injection port; S104: applying a curing process to the fluid QD fluorescent powder material within the receiving chamber; and S105: sealing the injection port by hot melting to obtain the QD glass cell. In addition, the above QD glass cell may be applied to LED light source.

Abstract: The present invention discloses a method for preparing a multilayer metal oxide nano-porous thin film gas sensitive material, in which the microsphere aqueous solution is self-assembled on a substrate covered with an insulating layer, to form a compact single-layer array template; the surface of these microspheres are etched by using a plasma etching method to reduce the pitches between the microspheres; the metal oxide thin film is deposited by a physical deposition method; the template is removed by ultrasonic treatment with a solvent to prepare a porous array metal oxide thin film; and annealing is performed in air atmosphere to obtain the metal oxide porous thin film gas sensitive material. The present invention can be used for preparing a regular porous array thin film gas sensitive material; the pore size of the prepared porous thin film material is uniform and controllable; and the combination of these materials is controllable.

Abstract: Topological insulators can be utilized in a new type of infrared photodetector that is intrinsically sensitive to the polarization of incident light and static magnetic fields. The detector isolates single topological insulator surfaces and allows light collection and exposure to static magnetic fields. The wavelength range of interest is between 750 nm and about 100 microns. This detector eliminates the need for external polarization selective optics. Polarization sensitive infrared photodetectors are useful for optoelectronics applications, such as light detection in environments with low visibility in the visible wavelength regime.

Abstract: A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.

Abstract: A method of forming a semiconductor device includes forming a fin extending from a substrate. The fin has a source/drain (S/D) region and a channel region. The fin includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer has a first composition, and the second semiconductor layer has a second composition different from the first composition. The method further includes removing the first semiconductor layer from the S/D region of the fin such that a first portion of the second semiconductor layer in the S/D region is suspended in a space. The method further includes epitaxially growing a third semiconductor layer in the S/D region, the third semiconductor layer wrapping around the first portion of the second semiconductor layer.

Abstract: A tunable quantum qubit circuit comprising: a plurality of interconnected Josephson tunneling junctions sculpted in-situ on-chip, wherein each Josephson tunneling junction comprises a pair of high temperature superconductors separated by an active region having a controlled charge density; a capacitive-coupled control gate operatively coupled to the Josephson tunneling junctions and configured to simultaneously modulate energy levels of the Josephson tunneling junctions; and independent control gates operatively coupled to the Josephson tunneling junctions, wherein the independent control gates are reconfigurable on-the-fly by an operator.

Abstract: The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel field-effect transistor (TFET) and a conventional field effect transistor (FET). Embodiments of the present invention include a hybrid amplifier which features a TFET common-source feeding a common-gate conventional FET (e.g. a MOSFET). A TFET gate may be electrically isolated from an output from a conventional FET. Thus, a high impedance input may be received by a TFET with a high-isolation output (i.e. low capacitance) at a conventional FET. A hybrid circuit amplifier including a TFET and a conventional FET may have a very high input impedance and a low miller capacitance.

Abstract: A method of making a novel STT-MRAM is disclosed, wherein the STT-MRAM comprises a novel apparatus along with a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory elements having spin-transfer torques acting on a recording layer from a MTJ stack and a novel magnetoresistance with a spin-valve layer. The spin-valve layer is field-reversible between two stable magnetization states either parallel or anti-parallel to the fixed reference layer magnetization through a set/reset current pulse along a conductive line provided by a control circuitry, accordingly, the magetoresistive element is pre-configured into a reading mode having canceled spin-transfer torques or a recording mode having additive spin-transfer torques.

Abstract: A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

Abstract: A composite comprising a conducting polymer and a graphene-based material is provided. The composite includes a graphene-based material doped with nitrogen or having a nitrogen-containing species grafted thereon, and a conducting polymer arranged on the graphene-based material. Methods of preparing the composite, and electrodes formed from the composite are also provided.

Abstract: A memory system according to an embodiment includes a plurality of magnetic nanowires, a read unit that reads data from the magnetic nanowires, a shift control unit that shifts domain walls in the magnetic nanowires, and a read control unit. The read control unit is configured to control the read unit to read the data from the magnetic nanowires in parallel, store two or more of the data read in parallel, and when the data corresponding to a first magnetic nanowire of the magnetic nanowires are delayed or advanced as compared to the data corresponding to a second magnetic nanowire of the magnetic nanowires, determines a misalignment in the data and correct the data based on the misalignment.

Abstract: A QD glass cell includes a glass cell and QD fluorescent powder material. The glass cell includes a receiving chamber, and the QD fluorescent powder being encapsulated within the receiving chamber. A manufacturing method of the QD glass cell includes: S101: manufacturing a glass cell comprising a receiving chamber, and the glass cell comprising an injection port transmitting fluid into the receiving chamber; S102: manufacturing fluid QD fluorescent powder material; S103: filling the fluid QD fluorescent powder material into the receiving chamber via the injection port; S104: applying a curing process to the fluid QD fluorescent powder material within the receiving chamber; and S105: sealing the injection port by hot melting to obtain the QD glass cell. In addition, the above QD glass cell may be applied to LED light source.

Abstract: A memristor device with a thermally-insulating cladding includes a first electrode, a second electrode, a memristor, and a thermally-insulating cladding. The memristor is coupled in electrical series between the first electrode and the second electrode. The thermally-insulating cladding surrounds at least a portion of the memristor.

Abstract: A photovoltaic solar cell comprises a nano-patterned substrate layer. A plurality of nano-windows are etched into an intermediate substrate layer to form the nano-patterned substrate layer. The nano-patterned substrate layer is positioned between an n-type semiconductor layer composed of an n-type semiconductor material and a p-type semiconductor layer composed of a p-type semiconductor material. Semiconductor material accumulates in the plurality of nano-windows, causing a plurality of heterojunctions to form between the n-type semiconductor layer and the p-type semiconductor layer.

Abstract: The disclosure provides a field-effect transistor (FET)-based biosensor and uses thereof. In particular, to FET-based biosensors using thermally reduced graphene-based sheets as a conducting channel decorated with nanoparticle-biomolecule conjugates. The present disclosure also relates to FET-based biosensors using metal nitride/graphene hybrid sheets. The disclosure provides a method for detecting a target biomolecule in a sample using the FET-based biosensor described herein.

Abstract: A quantum information processor can include a control system and a system of processor nodes. Each of the processor nodes can include multiple qubits and an actuator. The control system can manipulate the qubits of multiple processor nodes based on cross-node quantum interactions between the qubits. In some instances, the control system may perform multi-qubit quantum gates on qubits of different processor nodes based on the cross-node quantum interactions. Within each processor node, the qubits interact with the actuator by an intra-node quantum coupling. Between processor nodes, the actuators interact with each other by an inter-node quantum coupling. The cross-node quantum interaction can be produced by non-commutivity of the intra-node quantum couplings and the inter-node quantum couplings. In some instances, the qubits can be manipulated by applying a control sequence that produces an interaction frame where the cross-node quantum interaction dominates the time evolution of the system.

Abstract: A graphene layer, a method of forming the graphene layer, a device including the graphene layer, and a method of manufacturing the device are provided. The method of forming the graphene layer may include forming a first graphene at a first temperature using a first source gas and forming a second graphene at a second temperature using a second source gas. One of the first and second graphenes may be a P-type graphene, and the other one of the first and second graphenes may be an N-type graphene. The first graphene and the second graphene together form a P—N junction.

Abstract: Stacked devices and circuits formed by stacked devices are described. In accordance with some embodiments, a semiconductor post extends vertically from a substrate. A first source/drain region is in the semiconductor post. A first gate electrode layer laterally surrounds the semiconductor post and is vertically above the first source/drain region. A first gate dielectric layer is interposed between the first gate electrode layer and the semiconductor post. A second source/drain region is in the semiconductor post and is vertically above the first gate electrode layer. The second source/drain region is connected to a power supply node. A second gate electrode layer laterally surrounds the semiconductor post and is vertically above the second source/drain region. A second gate dielectric layer is interposed between the second gate electrode layer and the semiconductor post. A third source/drain region is in the semiconductor post and is vertically above the second gate electrode layer.

Abstract: The present disclosure provides methods for removing defects nanotube application solutions and providing low defect, highly uniform nanotube fabrics. In one aspect, a degassing process is performed on a suspension of nanotubes to remove air bubbles present in the solution. In another aspect, a continuous flow centrifugation (CFC) process is used to remove small scale defects from the solution. In another aspect, a depth filter is used to remove large scale defects from the solution. According to the present disclosure, these three methods can be used alone or combined to realize a low defect nanotube application solutions and fabrics.

Abstract: This disclosure provides an array substrate and manufacturing method thereof, as well as a display device, the array substrate comprising: a substrate and a pattern comprising a source and a drain located on the substrate, further comprising: a tunnel junction structure located between the substrate and the pattern comprising the source and the drain, the tunnel junction structure forming an active layer of the array substrate and resulting in tunneling effect. The above array substrate and the manufacturing method thereof, as well as the display device have one or more beneficial effects as follows: a relatively high current carrier mobility, a higher switching speed of TFT; the threshold voltage of the TFT is not easily drifted, and has a relatively high uniformity; each pixel can use less TFTs, the switching speed of the pixel is higher; and the fabricating process is simpler and more practicable.

Abstract: The present invention is directed to a multiwire nanowire field effect transistor (nwFET) device for the measurement. The device includes a sensing nanowire having a first end and a second end and a nanowire FET having a first end and a second end, wherein the first end of the sensing nanowire is connected to the nanowire FET to form a node. Additionally, the first end of the nanowire FET is connected to a source electrode, the second end of the nanowire FET is connected to a drain electrode, and the second end of the sensing nanowire is connected to a base electrode. The sensing nanowire is derivatized with a plurality of immobilized capture probes that are specific for a target(s) of interest. The device is used to detect biomolecules or to detect the change in the ionic environment of a sample. In a further embodiment, the sensing nanowire is derivatized with amino, carboxyl or hydroxyl groups.

Abstract: An electricity storage device includes a first electrode, a second electrode, an electricity storage layer, and a p-type semiconductor layer. The electricity storage layer is placed between the first electrode and the second electrode. The electricity storage layer contains a mixture of an insulating material and n-type semiconductor particles. The p-type semiconductor layer is placed between the electricity storage layer and the second electrode. The n-type semiconductor particles contain at least one of a titanium-niobium composite oxide and a titanium-tantalum composite oxide.

Abstract: The present invention concerns electrically conductive nanocomposites. More specifically the electrical conductance of graphitic material can be improved significantly by a molecular coating that has well defined repeating structure. Even superconductivity of these materials may be possible at technologically meaningful temperatures.

Abstract: An apparatus comprises a nanowire having a channel region, a gate structure surrounding a lower portion of the channel region, wherein the gate structure comprises a first dielectric layer comprising a vertical portion and a horizontal portion, a first workfunction metal layer over the first dielectric layer comprising a vertical portion and a horizontal portion and a low-resistivity metal layer over the first workfunction metal layer, wherein an edge of the low-resistivity metal layer and an edge of the vertical portion of the first workfunction metal layer are separated by a dielectric region and the low-resistivity metal layer is electrically coupled to the vertical portion of the first workfunction metal layer through the horizontal portion of the first workfunction metal layer.

Abstract: A field effect transistor includes a trench in a field dielectric material on a crystalline silicon substrate and source/drain features inside the trench. The field effect transistor further includes a channel feature comprising a III-V material in the trench and spanning between the source/drain features, and gate dielectric layers and a gate feature surrounding a portion of the channel feature.

Abstract: A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active layer pattern including silicon and graphene; a gate insulating layer disposed on the active layer pattern; a gate electrode disposed on the gate insulating layer; an insulating interlayer covering the active layer pattern and the gate electrode; and a source electrode and a drain electrode in contact with the active layer pattern.