Abstract: A quantum dot (QD) light emitting diode comprising first and second electrodes facing each other; a QD emitting material layer between the first and second electrodes; and a semiconducting member acting as a hole transporting path in the QD emitting material layer is provided.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Abstract: Methods, systems, and apparatus for operating a system of qubits. In one aspect, a method includes operating a first qubit from a first plurality of qubits at a first qubit frequency from a first qubit frequency region, and operating a second qubit from the first plurality of qubits at a second qubit frequency from a second first qubit frequency region, the second qubit frequency and the second first qubit frequency region being different to the first qubit frequency and the first qubit frequency region, respectively, wherein the second qubit is diagonal to the first qubit in a two-dimensional grid of qubits.

Abstract: Techniques for forming gate last VFET devices are provided. In one aspect, a method of forming a VFET device includes: forming a stack on a wafer including: i) a doped bottom source/drain, ii) sacrificial layers having layers of a first sacrificial material with a layer of a second sacrificial material therebetween, and iii) a doped top source/drain; patterning trenches in the stack to form individual gate regions; filling the trenches with a channel material to form vertical fin channels; selectively removing the layers of the first sacrificial material forming first cavities in the gate regions; forming gate spacers in the first cavities; selectively removing the layer of the second sacrificial material forming second cavities in the gate regions; and forming replacement metal gates in the second cavities. A VFET device is also provided.

Abstract: A method of fabricating a device includes providing a first fin in a first device type region and a second fin in a second device type region. Each of the first and second fins include a plurality of semiconductor channel layers. A two-step recess of an STI region on opposing sides of each of the first and second fins is performed to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region and a second gate structure is formed in the second device type region. The first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.

Abstract: A nanowire structure includes a substrate, a patterned mask layer on the substrate, and a nanowire. The patterned mask layer is on the substrate and includes an opening through which the substrate is exposed. The nanowire is on the substrate in the opening of the patterned mask layer. The nanowire includes a buffer layer on the substrate, a defect filtering layer on the buffer layer, and an active layer on the defect filtering layer. The defect filtering layer is a strained layer. By providing the defect filtering layer between the buffer layer and the active layer of the nanowire, defects present in the buffer layer can be prevented from propagating into the active layer. Accordingly, defects in the active layer of the nanowire are reduced, thereby improving the performance of the nanowire structure.

Abstract: A TFT structure based on a flexible multi-layer graphene quantum carbon substrate material and a method for manufacturing the same. The TFT structure includes a multi-layer graphene quantum carbon substrate, a first source, a first drain, a first gate insulating layer, and a first gate. The multi-layer graphene quantum carbon substrate includes a first channel area, and a first drain area and a first source area that are located at corresponding recessed positions on the multi-layer graphene quantum carbon substrate that are separated from each other. The first channel area is located between the first drain area and the first source area, the first source is filled in the first source area, the first drain is filled in the first drain area, the first gate insulating layer is disposed on the first channel area, and the first gate is disposed on the first gate insulating layer.

Abstract: An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract: A system for transmission of quantum information for quantum error correction includes an ancilla qubit chip including a plurality of ancilla qubits, and a data qubit chip spaced apart from the ancilla qubit chip, the data qubit chip including a plurality of data qubits. The system includes an interposer coupled to the ancilla qubit chip and the data qubit chip, the interposer including a dielectric material and a plurality of superconducting structures formed in the dielectric material. The superconducting structures enable transmission of quantum information between the plurality of data qubits on the data qubit chip and the plurality of ancilla qubits on the ancilla qubit chip via virtual photons for quantum error correction.

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The method includes forming a first layer of metal lines of a first back end of line (BEOL) interconnect structure and forming a semiconductor nanowire structure on a first metal line of the first layer of metal lines. The BEOL interconnect structure is formed on a front end of line (FEOL) device layer having multiple active devices. The method further includes forming a first dielectric layer wrapped around the semiconductor nanowire structure, forming a metal layer on the dielectric layer and on a second metal line of the first layer of metal lines, and forming a second layer of metal lines of a second BEOL interconnect structure on the semiconductor nanowire structure. The first and second metal lines are electrically isolated from each other.

Abstract: A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.

Abstract: Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

Abstract: Gated organic light-emitting diodes or vertical light emitting transistors are disclosed based on the modulation of charge carrier injection from electrodes into light-emitting materials by applying external gate potential. This gate modulation were achieved in two disclosed methods: 1) a porous electrode allowing mobile ions to stabilize electrochemically doped semiconducting materials that can form ohmic contact with electrodes: 2) an electrode with gate-tunable work function such as Al:LiF composite electrodes.

Abstract: A tunable resonator is formed by shunting a set of asymmetric DC-SQUIDs with a capacitive device. An asymmetric DC-SQUID includes a first Josephson junction and a second Josephson junction, where the critical currents of the first and second Josephson junctions are different. A coupling is formed between the tunable resonator and a qubit such that the capacitively-shunted asymmetric DC-SQUIDs can dispersively read a quantum state of the qubit. An external magnetic flux is set to a first value and applied to the tunable resonator. A first value of the external magnetic flux causes the tunable resonator to tune to a first frequency within a first frequency difference from a resonance frequency of the qubit, the tunable resonator tuning to the first frequency causes active reset of the qubit.

Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.

Abstract: A method of forming a micro-structure involves forming a multi-layered structure including i) an oxidizable material layer on a substrate and ii) another oxidizable material layer on the oxidizable material layer. The oxidizable material layer is formed of an oxidizable material having an expansion coefficient, during oxidation, that is more than 1. The method further involves forming a template, including a plurality of pores, from the other oxidizable material layer, and growing a nano-pillar inside each pore. The nano-pillar has a predefined length that terminates at an end. A portion of the template is selectively removed to form a substantially even plane that is oriented in a position opposed to the substrate. A material is deposited on at least a portion of the plane to form a film layer thereon, and the remaining portion of the template is selectively removed to expose the nano-pillars.

Abstract: A method of forming a three-dimensional transistor device. The method may include providing a fin array on a substrate, the fin array comprising a plurality of fin structures, formed from a monocrystalline semiconductor, and disposed subjacent to a hard mask layer. The method may include directing angled ions at the fin array, wherein the angled ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate. The angled ions may etch the plurality of fin structures to form a stack of isolated nanowires, within a given fin structure.

Abstract: An apparatus comprising a channel member, first and second electrodes configured to enable a flow of electrical current from the first electrode through the channel member to the second electrode, and a supporting substrate configured to support the channel member and the first and second electrodes, wherein one or more of the supporting substrate and electrodes are configured such that a portion of the channel member is suspended to expose opposing surfaces of the portion, the exposed opposing surfaces comprising respective functional coatings thereon configured to facilitate variation of the flow of electrical current through the channel member.

Abstract: Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps: measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets NW, width WW,i, of the nanowire/nanosheet number i, i being an integer from 1 to NW, thickness of the nanowire/nanosheet HW,i, number i, i being an integer from 1 to NW, corner radius RW,i of the nanowire/nanosheet number i, i being an integer from 1 to NW, RW,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ?T given by ?T=kBT/q; measuring the total gate capacitance for a plurality of gate voltages; determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowire

Abstract: Embodiments are directed to a microwave-to-optical transducer device. The device includes an anchorage structure that includes a bar extending in a plane and laterally delimiting two voids on each longitudinal side of the bar. That is, the two voids are arranged side-by-side in said plane. The device further includes a piezoelectric beam structured as an optical cavity (e.g., as a 1D photonic crystal cavity), where the beam extends transversally to the bar, parallel to said plane, and is anchored on a resting point on the bar. The beam extends outwardly, beyond the resting point and on each side thereof, so as to overhang each of the two voids. Embodiments are further directed to related microwave circuits, including a microwave-to-optical transducer such as described above and, in particular, to superconducting microwave circuits configured as quantum information processing devices.

Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.

Abstract: A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer. The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively.

Abstract: The present disclosure advances the art by providing a method and system for forming electronic devices. In particular, and by example only, methods are described for forming devices for harvesting energy in the terahertz frequency range on flexible substrates, wherein the methods provide favorable accuracy in registration of the various device elements and facilitate low-cost R2R manufacturing.

Abstract: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming a counter doped semiconductor layer on a physically exposed and recessed surface of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The presence of the counter doped semiconductor layer isolates the source/drain regions from the semiconductor substrate and eliminates parasitic transistor formation.

Abstract: A display apparatus includes a display substrate including a first electrode member; and a light-emitting diode (“LED”) on the display substrate and connected to the first electrode member of the display substrate. The first electrode member includes: a first electrode, and a protruding portion which protrudes from an upper surface of the first electrode. The LED includes a p-n diode, a first contact electrode disposed at a side of the p-n diode, and an insulating member surrounding the first contact electrode and in which an opening is defined which exposes a surface of the first contact electrode. The protruding portion of the first electrode member extends into the opening of the light-emitting diode and is in contact with the exposed surface of the first contact electrode.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a first recess in a substrate. The method includes forming a first semiconductor layer into the first recess. The first semiconductor layer and the substrate are made of different materials, and a first top surface of the first semiconductor layer is lower than a second top surface of the substrate. The method includes forming a second semiconductor layer over the first top surface and the second top surface, wherein a third top surface of the second semiconductor layer over the first top surface is substantially level with the second top surface of the substrate, and the second semiconductor layer and the substrate are made of different materials. The method includes forming a third semiconductor layer over the second semiconductor layer. The third semiconductor layer and the second semiconductor layer are made of different materials.

Abstract: Provided is a coated optical element that includes: an optical element; and a coating disposed on the optical element. The coating includes at least one layer of a topological insulator.

Abstract: A quantum dot light-emitting diode and a display apparatus comprising the quantum dot light-emitting diode are provided. The quantum dot light-emitting diode comprises an anode, a hole injecting layer, a hole transporting layer, a quantum dot light-emitting layer, an electron transporting layer and a cathode from bottom to top, wherein the materials of the quantum dot light-emitting layer contain quantum dots and CuSCN nano-particles. By blending quantum dots and CuSCN nano-particles into a membrane to prepare a quantum dot light-emitting layer, a hole trap state on the surface of the quantum dots is passivated, and the transporting effect of a hole is improved, so that the injection of holes in the quantum dot light-emitting diode and that of electrons achieve balance, and thus the light-emitting efficiency and stability are improved.

Abstract: A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to graphene detectors integrated with optical waveguide structures and methods of manufacture. The structure includes a plurality of non-planar fin structures composed of substrate material, and a non-planar sheet of graphene material extending entirely over each of the plurality of non-planar fin structures.

Abstract: An efficiency-enhanced, three-terminal, bi-junction thermoelectric device driven by independently-adjustable parameters of temperature and voltage.

Abstract: Example embodiments relate to an electrode structure, a triboelectric generator including the electrode structure, and a method of manufacturing the electrode structure. The electrode structure includes a flexible layer configured to be bendable by an external force and an electrode, at least some regions thereof being embedded in the flexible layer.

Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

Abstract: Embodiments of the present invention are directed to a method that incorporates a germanium pull-out process to form semiconductor structures having stacked silicon nanotubes. In a non-limiting embodiment of the invention, a sacrificial layer is formed over a substrate. The sacrificial layer includes a first type of semiconductor material. A pull-out layer is formed on the sacrificial layer. The first type of semiconductor material from the sacrificial layer is removed to form a silicon-rich layer on a surface of the sacrificial layer. The sacrificial layer can be removed such that the silicon-rich layer defines a silicon nanotube.

Abstract: Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction.

Abstract: Compact electro-optic modulator with integrated voltage-switched transparent conductive oxide capacitor with one-dimensional silicon photonic crystal nano-cavity.

Abstract: Strained nanosheet field effect transistors (FETs) using a phase change material are described herein. In some embodiments, a semiconductor device can comprise alternating layers of a channel material and a phase change material to produce strained nanosheet field effect transistors, wherein the layers of the phase change material cause a strain in the layers of the channel material. The phase change material comprises germanium antimony telluride. The germanium antimony telluride crystallizes into a crystalline germanium antimony telluride based on annealing above 300 degrees Celsius and a volume of the crystalline germanium antimony telluride is reduced up to six percent relative to an initial volume the germanium antimony telluride to cause the strain in the layers of the channel material. The semiconductor device can also comprise source and drain epitaxial growths on both ends of the layers of the channel material that lock the strain in the layers of the channel material.

Abstract: A semiconductor device comprises a substrate having an N-type field effect transistor (NFET) region and a P-type field effect transistor (PFET) region, a plurality of first nanowires in the PFET region and arranged in a first direction substantially perpendicular to the substrate and a plurality of second nanowires in the NFET region and arranged in the first direction. A composition of the first nanowires is different from a composition of the second nanowires, and one of the first nanowires is substantially aligned with one of the second nanowires in a second direction substantially perpendicular to the first direction.

Abstract: Disclosed is a method of manufacturing a junctionless transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels is exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels which is exposed though the hole.

Abstract: The spin-Hall effect can be used to modulate the linear polarization of light via the magneto-optical Kerr effect. A central area of an outer surface of an added layer atop a spin Hall material is illuminated while simultaneously passing a modulated electric current through the material, so that reflected light has a new linear polarization that differs from the initial linear polarization to a degree depending on the amplitude of the modulated electric current.

Abstract: An apparatus for performing quantum computing includes multiple qubits, each of at least a subset of the qubits comprising a loop formed of a Dirac or Weyl semimetal and having at least two stable quantum states. The apparatus further includes at least one terahertz cavity coupled with the qubits, the terahertz cavity being configured to detect the quantum states of the qubits. Each of at least the subset of qubits is configured to receive a circularly polarized radiation source. The radiation source is adapted to excite a chiral current in each of at least the subset of qubits, the quantum states of the plurality of qubits being a function of the chiral current.

Abstract: A quantum dot light-emitting device includes: a first electrode; a second electrode opposite to the first electrode; an emission layer between the first electrode and the second electrode, the emission layer including quantum dots; and an inorganic layer between the emission layer and the second electrode, the inorganic layer including a metal halide.

Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

Abstract: Provided are a novel method for manufacturing a stack of carbon nanotube and graphene that can improve a capacitor characteristic, an electrode material including the stack of carbon nanotube and graphene, and an electric double-layer capacitor using the same. A method for manufacturing a stack of graphene and carbon nanotube includes a step of dispersing the graphene in an aqueous MOH solution (M represents an element selected from a group consisting of Li, Na, and K) to adsorb MOH on the graphene, a step of heating the graphene with MOH adsorbed thereon that is obtained in the adsorption step in vacuum or in an inert atmosphere in a temperature range of 400° C. or more and 900° C. or less to form pores in the graphene, and a step of dispersing the carbon nanotube and the graphene with the pores that are obtained in the step of forming the pores in a dispersion medium to stack the carbon nanotube and the graphene with the pores.

Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

Abstract: Techniques for improving the performance of a quantum processor are described. The techniques include reading out a fraction of the qubits in a quantum processor and utilizing one or more post-processing operations to reconstruct qubits of the quantum processor that are not read. The reconstructed qubits may be determined using a perfect sampler to provide results that are strictly better than reading all of the qubits directly from the quantum processor. The composite sample that includes read qubits and reconstructed qubits may be obtained faster than if all qubits of the quantum processor are read directly.

Abstract: A semiconductor structure includes a substrate, an isolation layer disposed over the substrate, a plurality of nanosheet channels, interfacial layers surrounding each of the nanosheet channels, and dielectric layers surrounding each of the interfacial layers. The plurality of nanosheet channels includes first and second sets of two or more nanosheet channels for first and second NFETs and third and fourth sets of two or more nanosheet channels for first and second PFETs. The interfacial layers surrounding the first and third sets of nanosheet channels for the first NFET and the first PFET have a first thickness, and interfacial layers surrounding the second and fourth sets of nanosheets channels for the second NFET and the second PFET have a second thickness smaller than the first thickness. The first NFET has a higher threshold voltage than the second NFET, and the first PFET has a lower threshold voltage than the second PFET.

Abstract: A quantum device with spin qubits, comprising: a first semiconducting layer comprising a first matrix of data qubits and measurement qubits connected to each other through tunnel barriers; means of addressing qubits configured for controlling conduction of each tunnel barrier by the field effect and comprising: first and second conducting portions arranged in first and second superposed metallisation levels respectively; first and second conducting vias each comprising a first end connected to one of the first and second conducting portions respectively, and a second end located facing one of the tunnel barriers; a first dielectric layer interposed between the tunnel barriers and the second ends of the first and second conducting vias.

Abstract: The present disclosure relates to a tunneling field-effect transistor and a fabrication method. One example transistor includes a semiconductor substrate, a semiconductor nanosheet, a source region and a drain region, a dielectric layer, and a gate metal layer. The semiconductor nanosheet is vertically disposed on the semiconductor substrate. The source region and the drain region are connected using a channel. The drain region, the channel, and the source region are disposed on the semiconductor nanosheet in turn. The drain region is in contact with the semiconductor substrate. The source region is located at an end, of the semiconductor nanosheet, far away from the semiconductor substrate. The dielectric layer comprises at least a gate dielectric layer, is disposed on a surface of the semiconductor nanosheet, and surrounds the channel. The gate metal layer is disposed on a surface of the gate dielectric layer and surrounds the gate dielectric layer.