Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device) Patents (Class 257/9)
  • Patent number: 9997421
    Abstract: A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Zuoguang Liu, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9978678
    Abstract: Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: May 22, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin H. Chao, James J. Demarest, Nicolas J. Loubet
  • Patent number: 9915002
    Abstract: This disclosure teaches a method for producing a nano metal mesh. A brittle layer can be deposited onto a flexible substrate, the brittle layer having a thickness on the flexible substrate. The flexible substrate can be bent to produce a plurality of gaps on the brittle material. A material can be deposited at the surface of the flexible substrate filling the gaps of the brittle layer. Then, the brittle layer can be etched from the flexible substrate using an etchant, a nano metal mesh formed by the material previously in the gaps. The disclosure also teaches a nano metal mesh made using this method.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: March 13, 2018
    Inventor: Ethan Pfeiffer
  • Patent number: 9911819
    Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first top OD region, a first bottom OD region, and a first nanowire. A second GAA transistor includes: a second top OD region, a second bottom OD region, and a second nanowire. The first top OD region, the first bottom OD region, and the first nanowire are symmetrical with the second top OD region, the second bottom OD region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow from the first top OD region to the first bottom OD region, and the second GAA transistor is arranged to provide a second current to flow from the second top OD region to the second bottom OD region.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: March 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chung-Hui Chen
  • Patent number: 9909208
    Abstract: A method for developing a coating having a high light transmission and/or a low light reflection is provided. The method relates to a process for developing a coating with a high light transmission and/or a low light reflection, where the coating is deposited on a substrate. The coating is deposited as a mixed coating comprising a material A and a material B, where the coating is developed to have a coating thickness profile in which the lowest proportion of the material B is on the substrate surface and the highest proportion of coating material is on the coating surface. The material B is at least partially removed from the coating after deposition of the coating on the substrate.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 6, 2018
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Manuela Junghähnel, Thomas Preuβner, Ullrich Hartung
  • Patent number: 9905720
    Abstract: An apparatus and method wherein the apparatus comprises: a sensing material configured to produce a non-random distribution of free charges in response to a parameter; an electric field sensor; a first conductive electrode comprising a first area overlapping the sensing material; an insulator provided between the first conductive electrode and the sensing material; a second electrode comprising a second area adjacent the electric field sensor; and a conductive interconnection between the first conductive electrode and the second conductive electrode.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: February 27, 2018
    Assignee: EMBERION OY
    Inventors: Alan Colli, Stefano Borini
  • Patent number: 9881993
    Abstract: A method of forming a semiconductor device having a horizontal gate all around structure on a bulk substrate is provided. The method comprises forming a plurality of fins on a bulk substrate wherein each fin comprises a vertical slice of substrate material and a plurality of channel layers above the vertical slice of substrate material. The plurality of channel layers includes a top channel layer above a bottom channel layer. Each channel layer comprises a first sublayer of removable semiconductor material overlaid by a second sublayer of semiconductor material. The method further comprises providing shallow trench isolation (STI) material between the vertical slices of the bulk substrate in the plurality of fins, depositing poly material around a central portion of the plurality of fins, forming source and drain regions, and forming an interlayer dielectric layer (ILD0).
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 9875943
    Abstract: A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-Type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistor includes a germanium nanowire, a III-V compound layer surrounding around the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: January 23, 2018
    Assignee: ZING SEMICONDUCTOR CORPORATION
    Inventor: Deyuan Xiao
  • Patent number: 9871057
    Abstract: Device structures for a field-effect transistor and methods of forming such device structures using a device layer of a silicon-on-insulator substrate. A channel and an isolation region are formed in the device layer. The channel is located beneath a gate structure is formed on the device layer and is comprised of a semiconductor material under strain. A portion of the device layer is located between the first isolation region and the channel. The portion of the device layer is under a strain that is less than the strain in the semiconductor material of the channel.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 16, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Karen A. Nummy, Claude Ortolland
  • Patent number: 9859513
    Abstract: The present invention relates to atomically-thin channel materials with crystallographically uniform interfaces to atomically-thin commensurate graphene electrodes and/or nanoribbons separated by nanogaps that allow for nanoelectronics based on quantum transport effects and having significantly improved contact resistances.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: January 2, 2018
    Assignee: UNIVERSITY OF KENTUCKY RESEARCH FOUNDATION
    Inventors: Douglas Robert Strachan, David Patrick Hunley
  • Patent number: 9847469
    Abstract: Provided is a thermoelectric material satisfying (MX)1+a(TX2)n and having a superlattice structure, wherein M is at least one element selected from the group consisting of Group 13, Group 14, and Group 15, T is at least one element selected from Group 5, X is a chalcogenide element, a is a real number satisfying 0<a<1, and n is a natural number of 1 to 3.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: December 19, 2017
    Assignees: SK INNOVATION CO., LTD., UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY
    Inventors: Hyeung Jin Lee, Yong Rae Cho, Jong-Soo Rhyee, Yoo Jang Song, Jin Hee Kim
  • Patent number: 9842914
    Abstract: A method of forming a semiconductor device and resulting structures having stacked nanosheets with a wrap-around inner spacer by forming a nanosheet stack disposed above a substrate; forming a top sacrificial layer on a top surface of the nanosheet stack; forming a sidewall sacrificial layer on two opposite sidewalls of the nanosheet stack, such that a first and a second end of a first vertically-stacked nanosheet are exposed; removing the sidewall sacrificial layer, a portion of a first and a second end of a first sacrificial layer, and a portion of a first and a second end of a top sacrificial layer to expose portions of the first vertically-stacked nanosheet; and forming an inner spacer region on the first vertically-stacked nanosheet to replace the removed sidewall sacrificial layer, the removed portions of the first sacrificial layer, and the removed portions of the top sacrificial layer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: December 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chun W. Yeung, Chen Zhang
  • Patent number: 9818917
    Abstract: A QD glass cell includes a glass cell and QD fluorescent powder material. The glass cell includes a receiving chamber, and the QD fluorescent powder being encapsulated within the receiving chamber. A manufacturing method of the QD glass cell includes: S101: manufacturing a glass cell comprising a receiving chamber, and the glass cell comprising an injection port transmitting fluid into the receiving chamber; S102: manufacturing fluid QD fluorescent powder material; S103: filling the fluid QD fluorescent powder material into the receiving chamber via the injection port; S104: applying a curing process to the fluid QD fluorescent powder material within the receiving chamber; and S105: sealing the injection port by hot melting to obtain the QD glass cell. In addition, the above QD glass cell may be applied to LED light source.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 14, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Yong Fan
  • Patent number: 9816176
    Abstract: The present invention discloses a method for preparing a multilayer metal oxide nano-porous thin film gas sensitive material, in which the microsphere aqueous solution is self-assembled on a substrate covered with an insulating layer, to form a compact single-layer array template; the surface of these microspheres are etched by using a plasma etching method to reduce the pitches between the microspheres; the metal oxide thin film is deposited by a physical deposition method; the template is removed by ultrasonic treatment with a solvent to prepare a porous array metal oxide thin film; and annealing is performed in air atmosphere to obtain the metal oxide porous thin film gas sensitive material. The present invention can be used for preparing a regular porous array thin film gas sensitive material; the pore size of the prepared porous thin film material is uniform and controllable; and the combination of these materials is controllable.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: November 14, 2017
    Assignee: SOOCHOW UNIVERSITY
    Inventors: Xuhui Sun, Pingping Zhang, Shumin Zhang
  • Patent number: 9799828
    Abstract: Topological insulators can be utilized in a new type of infrared photodetector that is intrinsically sensitive to the polarization of incident light and static magnetic fields. The detector isolates single topological insulator surfaces and allows light collection and exposure to static magnetic fields. The wavelength range of interest is between 750 nm and about 100 microns. This detector eliminates the need for external polarization selective optics. Polarization sensitive infrared photodetectors are useful for optoelectronics applications, such as light detection in environments with low visibility in the visible wavelength regime.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: October 24, 2017
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventor: Peter Anand Sharma
  • Patent number: 9768085
    Abstract: A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Zuoguang Liu, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9755133
    Abstract: A tunable quantum qubit circuit comprising: a plurality of interconnected Josephson tunneling junctions sculpted in-situ on-chip, wherein each Josephson tunneling junction comprises a pair of high temperature superconductors separated by an active region having a controlled charge density; a capacitive-coupled control gate operatively coupled to the Josephson tunneling junctions and configured to simultaneously modulate energy levels of the Josephson tunneling junctions; and independent control gates operatively coupled to the Josephson tunneling junctions, wherein the independent control gates are reconfigurable on-the-fly by an operator.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: September 5, 2017
    Assignee: The United States of America as represented by Secretary of the Navy
    Inventors: Osama M. Nayfeh, Son Dinh, Anna Leese de Escobar, Kenneth Simonsen, Shahrokh Naderi
  • Patent number: 9754840
    Abstract: A method of forming a semiconductor device includes forming a fin extending from a substrate. The fin has a source/drain (S/D) region and a channel region. The fin includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer has a first composition, and the second semiconductor layer has a second composition different from the first composition. The method further includes removing the first semiconductor layer from the S/D region of the fin such that a first portion of the second semiconductor layer in the S/D region is suspended in a space. The method further includes epitaxially growing a third semiconductor layer in the S/D region, the third semiconductor layer wrapping around the first portion of the second semiconductor layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
  • Patent number: 9748271
    Abstract: The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel field-effect transistor (TFET) and a conventional field effect transistor (FET). Embodiments of the present invention include a hybrid amplifier which features a TFET common-source feeding a common-gate conventional FET (e.g. a MOSFET). A TFET gate may be electrically isolated from an output from a conventional FET. Thus, a high impedance input may be received by a TFET with a high-isolation output (i.e. low capacitance) at a conventional FET. A hybrid circuit amplifier including a TFET and a conventional FET may have a very high input impedance and a low miller capacitance.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: August 29, 2017
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Tamilmani Ethirajan, Edward J. Nowak
  • Patent number: 9741929
    Abstract: A method of making a novel STT-MRAM is disclosed, wherein the STT-MRAM comprises a novel apparatus along with a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory elements having spin-transfer torques acting on a recording layer from a MTJ stack and a novel magnetoresistance with a spin-valve layer. The spin-valve layer is field-reversible between two stable magnetization states either parallel or anti-parallel to the fixed reference layer magnetization through a set/reset current pulse along a conductive line provided by a control circuitry, accordingly, the magetoresistive element is pre-configured into a reading mode having canceled spin-transfer torques or a recording mode having additive spin-transfer torques.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: August 22, 2017
    Assignee: T3Memory, Inc.
    Inventor: Yimin Guo
  • Patent number: 9735234
    Abstract: A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Juntao Li
  • Patent number: 9734954
    Abstract: A composite comprising a conducting polymer and a graphene-based material is provided. The composite includes a graphene-based material doped with nitrogen or having a nitrogen-containing species grafted thereon, and a conducting polymer arranged on the graphene-based material. Methods of preparing the composite, and electrodes formed from the composite are also provided.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: August 15, 2017
    Assignees: Nanyang Technological University, Agency for Science, Technology and Research
    Inventors: Linfei Lai, Zexiang Shen, Jianyi Lin
  • Patent number: 9720772
    Abstract: A memory system according to an embodiment includes a plurality of magnetic nanowires, a read unit that reads data from the magnetic nanowires, a shift control unit that shifts domain walls in the magnetic nanowires, and a read control unit. The read control unit is configured to control the read unit to read the data from the magnetic nanowires in parallel, store two or more of the data read in parallel, and when the data corresponding to a first magnetic nanowire of the magnetic nanowires are delayed or advanced as compared to the data corresponding to a second magnetic nanowire of the magnetic nanowires, determines a misalignment in the data and correct the data based on the misalignment.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Sukegawa, Hiroshi Yao, Kohsuke Harada
  • Patent number: 9722151
    Abstract: A QD glass cell includes a glass cell and QD fluorescent powder material. The glass cell includes a receiving chamber, and the QD fluorescent powder being encapsulated within the receiving chamber. A manufacturing method of the QD glass cell includes: S101: manufacturing a glass cell comprising a receiving chamber, and the glass cell comprising an injection port transmitting fluid into the receiving chamber; S102: manufacturing fluid QD fluorescent powder material; S103: filling the fluid QD fluorescent powder material into the receiving chamber via the injection port; S104: applying a curing process to the fluid QD fluorescent powder material within the receiving chamber; and S105: sealing the injection port by hot melting to obtain the QD glass cell. In addition, the above QD glass cell may be applied to LED light source.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: August 1, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Yong Fan
  • Patent number: 9716224
    Abstract: A memristor device with a thermally-insulating cladding includes a first electrode, a second electrode, a memristor, and a thermally-insulating cladding. The memristor is coupled in electrical series between the first electrode and the second electrode. The thermally-insulating cladding surrounds at least a portion of the memristor.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: July 25, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gary Gibson, Richard Henze, Warren Jackson, Yoocham Jeon
  • Patent number: 9685580
    Abstract: A photovoltaic solar cell comprises a nano-patterned substrate layer. A plurality of nano-windows are etched into an intermediate substrate layer to form the nano-patterned substrate layer. The nano-patterned substrate layer is positioned between an n-type semiconductor layer composed of an n-type semiconductor material and a p-type semiconductor layer composed of a p-type semiconductor material. Semiconductor material accumulates in the plurality of nano-windows, causing a plurality of heterojunctions to form between the n-type semiconductor layer and the p-type semiconductor layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: June 20, 2017
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jose Luis Cruz-Campa, Xiaowang Zhou, David Zubia
  • Patent number: 9676621
    Abstract: The disclosure provides a field-effect transistor (FET)-based biosensor and uses thereof. In particular, to FET-based biosensors using thermally reduced graphene-based sheets as a conducting channel decorated with nanoparticle-biomolecule conjugates. The present disclosure also relates to FET-based biosensors using metal nitride/graphene hybrid sheets. The disclosure provides a method for detecting a target biomolecule in a sample using the FET-based biosensor described herein.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: June 13, 2017
    Assignee: UWM Research Foundation, Inc.
    Inventors: Junhong Chen, Shun Mao, Ganhua Lu
  • Patent number: 9663358
    Abstract: A quantum information processor can include a control system and a system of processor nodes. Each of the processor nodes can include multiple qubits and an actuator. The control system can manipulate the qubits of multiple processor nodes based on cross-node quantum interactions between the qubits. In some instances, the control system may perform multi-qubit quantum gates on qubits of different processor nodes based on the cross-node quantum interactions. Within each processor node, the qubits interact with the actuator by an intra-node quantum coupling. Between processor nodes, the actuators interact with each other by an inter-node quantum coupling. The cross-node quantum interaction can be produced by non-commutivity of the intra-node quantum couplings and the inter-node quantum couplings. In some instances, the qubits can be manipulated by applying a control sequence that produces an interaction frame where the cross-node quantum interaction dominates the time evolution of the system.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: May 30, 2017
    Assignee: Quantum Valley Investment Fund LP
    Inventors: David G. Cory, Troy W. Borneman, Christopher E. Granade
  • Patent number: 9660036
    Abstract: A graphene layer, a method of forming the graphene layer, a device including the graphene layer, and a method of manufacturing the device are provided. The method of forming the graphene layer may include forming a first graphene at a first temperature using a first source gas and forming a second graphene at a second temperature using a second source gas. One of the first and second graphenes may be a P-type graphene, and the other one of the first and second graphenes may be an N-type graphene. The first graphene and the second graphene together form a P—N junction.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 23, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyowon Kim, Jaeho Lee
  • Patent number: 9650732
    Abstract: The present disclosure provides methods for removing defects nanotube application solutions and providing low defect, highly uniform nanotube fabrics. In one aspect, a degassing process is performed on a suspension of nanotubes to remove air bubbles present in the solution. In another aspect, a continuous flow centrifugation (CFC) process is used to remove small scale defects from the solution. In another aspect, a depth filter is used to remove large scale defects from the solution. According to the present disclosure, these three methods can be used alone or combined to realize a low defect nanotube application solutions and fabrics.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: May 16, 2017
    Assignee: Nantero Inc.
    Inventors: J. Thomas Kocab, Thomas R. Bengtson, Sanjin Hosic, Rahul Sen, Billy Smith, David A. Roberts, Peter Sites
  • Patent number: 9653457
    Abstract: Stacked devices and circuits formed by stacked devices are described. In accordance with some embodiments, a semiconductor post extends vertically from a substrate. A first source/drain region is in the semiconductor post. A first gate electrode layer laterally surrounds the semiconductor post and is vertically above the first source/drain region. A first gate dielectric layer is interposed between the first gate electrode layer and the semiconductor post. A second source/drain region is in the semiconductor post and is vertically above the first gate electrode layer. The second source/drain region is connected to a power supply node. A second gate electrode layer laterally surrounds the semiconductor post and is vertically above the second source/drain region. A second gate dielectric layer is interposed between the second gate electrode layer and the semiconductor post. A third source/drain region is in the semiconductor post and is vertically above the second gate electrode layer.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Pen Guo, Carlos H. Diaz, Chih-Hao Wang, Jean-Pierre Colinge
  • Patent number: 9645135
    Abstract: The present invention is directed to a multiwire nanowire field effect transistor (nwFET) device for the measurement. The device includes a sensing nanowire having a first end and a second end and a nanowire FET having a first end and a second end, wherein the first end of the sensing nanowire is connected to the nanowire FET to form a node. Additionally, the first end of the nanowire FET is connected to a source electrode, the second end of the nanowire FET is connected to a drain electrode, and the second end of the sensing nanowire is connected to a base electrode. The sensing nanowire is derivatized with a plurality of immobilized capture probes that are specific for a target(s) of interest. The device is used to detect biomolecules or to detect the change in the ionic environment of a sample. In a further embodiment, the sensing nanowire is derivatized with amino, carboxyl or hydroxyl groups.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: May 9, 2017
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Kyeong-Sik Shin, Chi On Chui
  • Patent number: 9646998
    Abstract: This disclosure provides an array substrate and manufacturing method thereof, as well as a display device, the array substrate comprising: a substrate and a pattern comprising a source and a drain located on the substrate, further comprising: a tunnel junction structure located between the substrate and the pattern comprising the source and the drain, the tunnel junction structure forming an active layer of the array substrate and resulting in tunneling effect. The above array substrate and the manufacturing method thereof, as well as the display device have one or more beneficial effects as follows: a relatively high current carrier mobility, a higher switching speed of TFT; the threshold voltage of the TFT is not easily drifted, and has a relatively high uniformity; each pixel can use less TFTs, the switching speed of the pixel is higher; and the fabricating process is simpler and more practicable.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: May 9, 2017
    Assignees: Boe Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventor: Jinzhong Zhang
  • Patent number: 9640606
    Abstract: An electricity storage device includes a first electrode, a second electrode, an electricity storage layer, and a p-type semiconductor layer. The electricity storage layer is placed between the first electrode and the second electrode. The electricity storage layer contains a mixture of an insulating material and n-type semiconductor particles. The p-type semiconductor layer is placed between the electricity storage layer and the second electrode. The n-type semiconductor particles contain at least one of a titanium-niobium composite oxide and a titanium-tantalum composite oxide.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: May 2, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiko Sagara, Norihito Fujinoki, Yuki Nomura, Haruhiko Habuta
  • Patent number: 9634222
    Abstract: The present invention concerns electrically conductive nanocomposites. More specifically the electrical conductance of graphitic material can be improved significantly by a molecular coating that has well defined repeating structure. Even superconductivity of these materials may be possible at technologically meaningful temperatures.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: April 25, 2017
    Inventors: Jorma Virtanen, Veijo Kangas
  • Patent number: 9614091
    Abstract: An apparatus comprises a nanowire having a channel region, a gate structure surrounding a lower portion of the channel region, wherein the gate structure comprises a first dielectric layer comprising a vertical portion and a horizontal portion, a first workfunction metal layer over the first dielectric layer comprising a vertical portion and a horizontal portion and a low-resistivity metal layer over the first workfunction metal layer, wherein an edge of the low-resistivity metal layer and an edge of the vertical portion of the first workfunction metal layer are separated by a dielectric region and the low-resistivity metal layer is electrically coupled to the vertical portion of the first workfunction metal layer through the horizontal portion of the first workfunction metal layer.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 9583567
    Abstract: A field effect transistor includes a trench in a field dielectric material on a crystalline silicon substrate and source/drain features inside the trench. The field effect transistor further includes a channel feature comprising a III-V material in the trench and spanning between the source/drain features, and gate dielectric layers and a gate feature surrounding a portion of the channel feature.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Sanghoon Lee
  • Patent number: 9577114
    Abstract: A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active layer pattern including silicon and graphene; a gate insulating layer disposed on the active layer pattern; a gate electrode disposed on the gate insulating layer; an insulating interlayer covering the active layer pattern and the gate electrode; and a source electrode and a drain electrode in contact with the active layer pattern.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: February 21, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin-Woo Lee, Moo-Jin Kim
  • Patent number: 9570559
    Abstract: An electronic device can include a dielectric layer, and a graphene layer including a first surface located upon the dielectric layer. The electronic device can include a first electrode, a second electrode, and a third electrode each located upon the dielectric layer on a surface opposite the graphene layer. The first and second electrodes can be spaced apart along a longitudinal axis of the electronic device to define a first gap between the first and second electrodes, and the second and third electrodes are spaced apart along the longitudinal axis of the electronic device to define a second gap between the second and third electrodes. At least one of the first gap or the second gap can be angled so as to be neither parallel nor perpendicular to the longitudinal axis of the electronic device.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 14, 2017
    Assignee: University of Virginia Patent Foundation
    Inventors: Redwan Noor Sajjad, Avik Ghosh
  • Patent number: 9540683
    Abstract: We provide a sensor array device for the measurement of mixtures of organic compounds comprising an assembly of sensor half elements which have been functionalized through sensor compounds before the assembly. Each individual sensor of the array contains two sensor compounds which are bound at opposite sensor half elements. The molecular recognition is bi-functional. While the amount of sensor compounds increases linearly, the individual sensors increase with the second power.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: January 10, 2017
    Assignee: Lexogen GmbH
    Inventors: Torsten Reda, Igor Holländer, Alexander Seitz
  • Patent number: 9536953
    Abstract: A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces.
    Type: Grant
    Filed: June 20, 2015
    Date of Patent: January 3, 2017
    Assignee: Infineon Technologies AG
    Inventors: Klaus Elian, Guenther Ruhl, Horst Theuss, Irmgard Escher-Poeppel
  • Patent number: 9527043
    Abstract: A gas separation membrane including a porous support; and a gas separating active layer which is disposed on the porous support and includes a functionalized graphene.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: December 27, 2016
    Assignees: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Jae-young Choi, Ho-bum Park, Seon-mi Yoon, Hyo-won Kim, Byung-kook Ahn, Byung-min Yoo, Hee-wook Yoon
  • Patent number: 9525072
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: December 20, 2016
    Assignees: Taiwan Semiconductor Manufacturing Company Limited, National Taiwan University
    Inventors: Meng-Yu Lin, Shih-Yen Lin, Si-Chen Lee
  • Patent number: 9525136
    Abstract: Ultraviolet (UV), Terahertz (THZ) and Infrared (IR) radiation detecting and sensing systems using graphene nanoribbons and methods to making the same. In an illustrative embodiment, the detector includes a substrate, single or multiple layers of graphene nanoribbons, and first and second conducting interconnects each in electrical communication with the graphene layers. Graphene layers are tuned to increase the temperature coefficient of resistance to increase sensitivity to IR radiation. Absorption over a wide wavelength range of 200 nm to 1 mm are possible based on the two alternative devices structures described within. These two device types are a microbolometer based graphene film where the TCR of the layer is enhanced with selected functionalization molecules. The second device structure consists of a graphene nanoribbon layers with a source and drain metal interconnect and a deposited metal of SiO2 gate which modulates the current flow across the phototransistor detector.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: December 20, 2016
    Assignee: Magnolia Optical Technologies, Inc.
    Inventors: Elwood J. Egerton, Ashok K. Sood
  • Patent number: 9518336
    Abstract: A synthetic diamond material comprising one or more spin defects having a full width half maximum intrinsic inhomogeneous zero phonon line width of no more than 100 MHz. The method for obtain such a material involves a multi-stage annealing process.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 13, 2016
    Assignees: Element Six Limited, President and Fellows of Harvard College
    Inventors: Matthew Markham, Alastair Stacey, Nathalie De Leon, Yiwen Chu, Brendan John Shields, Birgit Judith Maria Hausmann, Patrick Maletinsky, Ruffin Eley Evans, Amir Yacoby, Hongkun Park, Marko Loncar, Mikhail D. Lukin
  • Patent number: 9515194
    Abstract: Embodiments of the invention include a method for fabricating a nano-ribbon transistor device and the resulting structure. A nano-ribbon transistor device including a substrate, a nano-ribbon channel, a core region in the center of the nano-ribbon channel, a gate formed around the nano-ribbon channel, a spacer formed on each sidewall of the gate, and a source and drain region epitaxially formed adjacent to each spacer is provided. The core region in the center of the nano-ribbon channel is selectively etched. A dielectric material is deposited on the exposed portions of the nano-ribbon channel. A back-bias control region is formed on the dielectric material within the core of the nano-ribbon channel and on the substrate adjacent to the nano-ribbon transistor device. A metal contact is formed in the back-bias control region.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9515173
    Abstract: Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9515244
    Abstract: A novel and effective structure of a stackable element (A1, A2) or more generally adapted to be associated modularly to other similar elements to form a septum of relatively large dimensions for a Seebeck/Peltier thermoelectric conversion device, may be fabricated with common planar processing techniques. The structure basically consists of a stack (A1, A2) of alternated layers of a first dielectric material (2), adapted to be deposited in films of thickness lesser than or equal to about 50 nm, of low heat conductivity and which is etchable by a solution of a specific chemical compound, and of a second dielectric material (3) of low heat conductivity that is not etched by the solution.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: December 6, 2016
    Assignee: Consorzio Delta Ti Research
    Inventors: Dario Narducci, Gianfranco Cerofolini
  • Patent number: 9508795
    Abstract: Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chun Yu Wong, Min-hwa Chi, Ashish Baraskar, Jagar Singh
  • Patent number: 9466699
    Abstract: A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: October 11, 2016
    Assignee: SHANGHAI IC R&D CENTER CO., LTD
    Inventors: Ao Guo, Zheng Ren, Shaojian Hu, Wei Zhou