Abstract: An electronic device can include a dielectric layer, and a graphene layer including a first surface located upon the dielectric layer. The electronic device can include a first electrode, a second electrode, and a third electrode each located upon the dielectric layer on a surface opposite the graphene layer. The first and second electrodes can be spaced apart along a longitudinal axis of the electronic device to define a first gap between the first and second electrodes, and the second and third electrodes are spaced apart along the longitudinal axis of the electronic device to define a second gap between the second and third electrodes. At least one of the first gap or the second gap can be angled so as to be neither parallel nor perpendicular to the longitudinal axis of the electronic device.

Abstract: We provide a sensor array device for the measurement of mixtures of organic compounds comprising an assembly of sensor half elements which have been functionalized through sensor compounds before the assembly. Each individual sensor of the array contains two sensor compounds which are bound at opposite sensor half elements. The molecular recognition is bi-functional. While the amount of sensor compounds increases linearly, the individual sensors increase with the second power.

Abstract: A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces.

Abstract: A gas separation membrane including a porous support; and a gas separating active layer which is disposed on the porous support and includes a functionalized graphene.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.

Abstract: Ultraviolet (UV), Terahertz (THZ) and Infrared (IR) radiation detecting and sensing systems using graphene nanoribbons and methods to making the same. In an illustrative embodiment, the detector includes a substrate, single or multiple layers of graphene nanoribbons, and first and second conducting interconnects each in electrical communication with the graphene layers. Graphene layers are tuned to increase the temperature coefficient of resistance to increase sensitivity to IR radiation. Absorption over a wide wavelength range of 200 nm to 1 mm are possible based on the two alternative devices structures described within. These two device types are a microbolometer based graphene film where the TCR of the layer is enhanced with selected functionalization molecules. The second device structure consists of a graphene nanoribbon layers with a source and drain metal interconnect and a deposited metal of SiO2 gate which modulates the current flow across the phototransistor detector.

Abstract: A synthetic diamond material comprising one or more spin defects having a full width half maximum intrinsic inhomogeneous zero phonon line width of no more than 100 MHz. The method for obtain such a material involves a multi-stage annealing process.

Abstract: Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.

Abstract: Embodiments of the invention include a method for fabricating a nano-ribbon transistor device and the resulting structure. A nano-ribbon transistor device including a substrate, a nano-ribbon channel, a core region in the center of the nano-ribbon channel, a gate formed around the nano-ribbon channel, a spacer formed on each sidewall of the gate, and a source and drain region epitaxially formed adjacent to each spacer is provided. The core region in the center of the nano-ribbon channel is selectively etched. A dielectric material is deposited on the exposed portions of the nano-ribbon channel. A back-bias control region is formed on the dielectric material within the core of the nano-ribbon channel and on the substrate adjacent to the nano-ribbon transistor device. A metal contact is formed in the back-bias control region.

Abstract: A novel and effective structure of a stackable element (A1, A2) or more generally adapted to be associated modularly to other similar elements to form a septum of relatively large dimensions for a Seebeck/Peltier thermoelectric conversion device, may be fabricated with common planar processing techniques. The structure basically consists of a stack (A1, A2) of alternated layers of a first dielectric material (2), adapted to be deposited in films of thickness lesser than or equal to about 50 nm, of low heat conductivity and which is etchable by a solution of a specific chemical compound, and of a second dielectric material (3) of low heat conductivity that is not etched by the solution.

Abstract: Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures.

Abstract: A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.

Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

Abstract: This disclosure provides systems, methods, and apparatus related to liquid flow cells for microscopy. In one aspect, a device includes a substrate having a first and a second oxide layer disposed on surfaces of the substrate. A first and a second nitride layer are disposed on the first and second oxide layers, respectively. A cavity is defined in the first oxide layer, the first nitride layer, and the substrate, with the cavity including a third nitride layer disposed on walls of the substrate and the second oxide layer that define the cavity. A channel is defined in the second oxide layer. An inlet port and an outlet port are defined in the second nitride layer and in fluid communication with the channel. A plurality of viewports is defined in the second nitride layer. A first graphene sheet is disposed on the second nitride layer covering the plurality of viewports.

Abstract: In an aspect of this disclosure, a method is provided comprising the steps of: (a) providing a silicon-containing substrate, (b) depositing a first metal on the substrate, (c) etching the substrate produced by step (b) using a first etch, and (d) etching the substrate produced by step (c) using a second etch, wherein the second etch is more aggressive towards the deposited metal than the first etch, wherein the result of step (d) comprises silicon nanowires. The method may further comprise, for example, steps (b1) subjecting the first metal to a treatment which causes it to agglomerate and (b2) depositing a second metal.

Abstract: The present invention provides a method and a system for forming wires (1) that enables a large scale process combined with a high structural complexity and material quality comparable to wires formed using substrate-based synthesis. The wires (1) are grown from catalytic seed particles (2) suspended in a gas within a reactor. Due to a modular approach wires (1) of different configuration can be formed in a continuous process. In-situ analysis to monitor and/or to sort particles and/or wires formed enables efficient process control.

Abstract: A hafnium telluride compound includes a layered crystal structure and represented by the following Chemical Formula 1. Hf3Te2-xAx??[Chemical Formula 1] Herein, A is at least one selected from phosphorus (P), Arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S) and selenium (Se), and 0<x?1.

Abstract: A semiconductor device having a composite structure is disclosed, which includes a channel structure having an inner core strut that extends substantially along a channel direction of the semiconductor device and an outer sleeve layer disposed on the inner core strut. The inner core strut mechanically supports the sleeve member across a channel length of the semiconductor device.

Abstract: Certain example embodiments of this invention relate to the use of graphene as a transparent conductive coating (TCC). In certain example embodiments, graphene thin films grown on large areas hetero-epitaxially, e.g., on a catalyst thin film, from a hydrocarbon gas (such as, for example, C2H2, CH4, or the like). The graphene thin films of certain example embodiments may be doped or undoped. In certain example embodiments, graphene thin films, once formed, may be lifted off of their carrier substrates and transferred to receiving substrates, e.g., for inclusion in an intermediate or final product. Graphene grown, lifted, and transferred in this way may exhibit low sheet resistances (e.g., less than 150 ohms/square and lower when doped) and high transmission values (e.g., at least in the visible and infrared spectra).

Abstract: A method of fabricating a semiconductor device includes forming first and second fin-type structures on first and second regions of a substrate, respectively, forming first and second capping layers on the first and second fin-type structures, respectively, forming a first dummy gate electrode on the first capping layer and a second dummy gate electrode on the second capping layer, exposing the first capping layer and the second capping layer by removing the first dummy gate electrode and the second dummy gate electrode, forming a second wire pattern group on the second region, and forming a first wire pattern group on the first region.

Abstract: A semiconductor device comprises at least two nanowire patterns over a substrate, wherein the at least two nanowire patterns have increasingly narrower widths as they extend away from the substrate and have different channel impurity concentrations. A gate electrode surrounds at least a part of the at least two nanowire patterns. A gate dielectric film is disposed between the at least two nanowire patterns and the gate electrode.

Abstract: A fin stack structure is provided on an insulator layer. The fin stack structure comprises, from bottom to top, a first semiconductor fin portion, a dielectric fin portion, a second semiconductor fin portion and a hard mask fin portion. A sacrificial gate structure is formed on a portion of the fin stack structure. The hard mask fin portion and the dielectric fin portion not located beneath the sacrificial gate structure are removed. An epitaxial semiconductor material structure is then formed from exposed surfaces of each semiconductor fin portion. The sacrificial gate structure is then removed. Next, remaining portions of the hard mask fin portion and the dielectric fin portion are removed. The insulating layer is then recessed. After recessing the insulator layer, the first and second semiconductor fin portions are suspended and are stacked one atop the other.

Abstract: Discloses herein is a method to make a transparent conductive electrode. The methods comprises providing a substrate, forming a film comprising a first region having a plurality of metal nanowires, wherein at least some of metal nanowires are surface functionalized and inert to oxidation or acid reactions; evaporating away the solvent in the metal nanowire film; exposing the nanowire film to a chemical reagent; forming a second region comprising nanowires, and annealing the film having the first and second region, wherein the resistivity difference between the first and second region is more than 1000.

Abstract: A polarization organic photoelectric conversion device having a structure in which an organic photoelectric conversion layer is interposed between a first electrode and a second electrode, at least one of which is transparent, wherein the organic photoelectric conversion layer is one obtained by uniaxially orienting at least a portion thereof in the plane in advance.

Abstract: Various embodiments are provided for graphite and/or graphene based semiconductor devices. In one embodiment, a semiconductor device includes a semiconductor layer and a semimetal stack. In another embodiment, the semiconductor device includes a semiconductor layer and a zero gap semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the semiconductor layer, which forms a Schottky barrier. In another embodiment, a semiconductor device includes first and second semiconductor layers and a semimetal stack. In another embodiment, a semiconductor device includes first and second semiconductor layers and a zero gap semiconductor layer. The first semiconductor layer includes a first semiconducting material and the second semi conductor layer includes a second semiconducting material formed on the first semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the second semiconductor layer, which forms a Schottky barrier.

Abstract: A topological insulator is grown on an IC wafer in a vacuum chamber as a thin film interconnect between two circuits in the IC communicating with each other. As the TI is being grown, magnetic doping of the various TI sub-layers is varied to create different edge states in the stack of sub-layers. The sub-edges conduct in parallel with virtually zero power dissipation. Conventional metal electrodes are formed on the IC wafer that electrically contact the four corners of the TI layer (including the side edges) to electrically connect a first circuit to a second circuit via the TI interconnect. The TI interconnect thus forms two independent conducting paths between the two circuits, with each path being formed of a plurality of sub-edges. This allows bi-direction communications without collisions. Since each electrode contacts many sub-edges in parallel, the overall contact resistance is extremely low.

Abstract: A method for generating quantum anomalous Hall effect is provided. A topological insulator quantum well film in 3QL to 5QL is formed on an insulating substrate. The topological insulator quantum well film is doped with a first element and a second element to form the magnetically doped topological insulator quantum well film. The doping of the first element and the second element respectively introduce hole type charge carriers and electron type charge carriers in the magnetically doped topological insulator quantum well film, to decrease the carrier density of the magnetically doped topological insulator quantum well film to be smaller than or equal to 1×1013 cm?2. One of the first element and the second element magnetically dopes the topological insulator quantum well film. An electric field is applied to the magnetically doped topological insulator quantum well film to decrease the carrier density.

Abstract: A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active layer pattern including silicon and graphene; a gate insulating layer disposed on the active layer pattern; a gate electrode disposed on the gate insulating layer; an insulating interlayer covering the active layer pattern and the gate electrode; and a source electrode and a drain electrode in contact with the active layer pattern.

Abstract: Provided is a graphene switching device including: a graphene layer formed on a substrate; a plurality of semiconductor nanowires on the substrate; a first electrode connected to a second end of the graphene layer; a second electrode on the substrate to face the first electrode so as to be connected to the plurality of semiconductor nanowires; a gate insulating layer on the substrate to cover the graphene layer; and a gate electrode on the gate insulating layer. The gate electrode and the plurality of semiconductor nanowires face each other with the graphene layer therebetween. At least one of the plurality of semiconductor nanowires is connected to at least one of the second electrode, the graphene layer, and the other of the plurality of semiconductor nanowires.

Abstract: A gate cavity is formed exposing a portion of a silicon fin by removing a sacrificial gate structure that straddles the silicon fin. An epitaxial silicon germanium alloy layer is formed within the gate cavity and on the exposed portion of the silicon fin. Thermal mixing or thermal condensation is performed to convert the exposed portion of the silicon fin into a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. A functional gate structure is formed within the gate cavity providing a finFET structure having a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions.

Abstract: Provided is a method of manufacturing a gradually stretchable substrate. The method includes forming convex regions and concave regions on a top surface of a stretchable substrate by compressing a mold onto the stretchable substrate and forming non-stretchable patterns by filling the concave regions of the stretchable substrate. The stretchable substrate includes a stretchable region defined by the non-stretchable patterns, the non-stretchable patterns have side surfaces in contact with the stretchable region, and the side surfaces of the non-stretchable patterns are formed of protrusions and a non-protrusion between the protrusions repetitively connected to one another.

Abstract: A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.

Abstract: A thin film transistor is equipped with a silicon substrate, a channel layer, a source electrode and a drain electrode. The channel layer, the source electrode and the drain electrode are arranged on the main surface of the silicon substrate. The channel layer is composed of multiple carbon nanowall thin films, wherein the multiple carbon nanowall thin films are arranged in parallel to each other between the source electrode and the drain electrode, one end of each of the multiple carbon nanowall thin films is in contact with the source electrode, and the other end of each of the multiple carbon nanowall thin films is in contact with the drain electrode. An insulating film and a gate electrode are arranged on the rear surface side of the silicon substrate.

Abstract: A photovoltaic device includes a semiconductor nanocrystal and a charge transporting layer that includes an inorganic material. The charge transporting layer can be a hole or electron transporting layer. The inorganic material can be an inorganic semiconductor.

Abstract: A system, method, and chip to control Purcell loss are described. The chip includes qubits formed on a first surface of a substrate. The method includes determining frequencies of the qubits, and controlling a separation between the frequencies of the qubits and chip mode frequencies of the chip.

Abstract: A method for making nanostructure is provided. The method includes following steps. A conductive layer including a graphene film is applied on an insulating substrate. A resist layer is placed on the conductive layer. A number of openings are formed by patterning the resist layer via electron beam lithography. A part of the conductive layer is exposed to form a first exposed portion through the plurality of openings. The first exposed portion of the conductive layer is removed to expose a part of the insulting substrate to form a second exposed portion. A preform layer is introduced on the second exposed portion of the insulating substrate. Remaining resist layer and remaining conductive layer are eliminated. A number of nanostructures are formed.

Abstract: A voltage switchable non-local spin-FET is disclosed which provides a layer of chromia over a ferromagnetic substrate, such as cobalt. A film of graphene overlays the chromia, with a protective layer of metal oxide like cobalt oxide or iron oxide there between to prevent catalytic degradation of the graphene, which may occur. The graphene is provided with a contact, or source and drain, depending on the application. The spin-FET, which exhibits magnetic remanence, may be provided with a top gate of, e.g., cobalt or other ferromagnet such as iron. As an alternative to the ferromagnetic substrate, the device may be formed on a silicon or gallium arsenide base, or directly on a metal interconnect of an integrated circuit.

Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.

Abstract: Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells. Methods for controlling spontaneous ferroelectric polarization in nanoshell devices are also disclosed.

Abstract: Systems and methods for discriminating among volatile compounds is provided using a semiconductor junction structure or sensor device. Sensor devices of the present disclosure employ a combination of hole carriers (p-type) and electron carriers (n-type) metal oxides deposited, for example, on a gold microspring array designed so that it has several leads that are at different distances from each other.

Abstract: A bowl shaped metal nanostructure array includes a substrate having a surface and a number of particle-in-bowl structures located on the surface of the substrate. Each particle-in-bowl structures includes a bowl shaped concave structure and a protruding member protruding from the bowl shaped concave structure. The protruding member is integrated with the bowl shaped concave structure.

Abstract: An organic transistor is provided with: an insulating substrate; a pair of insulating pedestals (2, 3) that are arranged spaced apart from each other on the substrate and that form respectively raised flat surfaces; a source electrode (4) provided on the raised flat surface formed on one of the pedestals; a drain electrode (5) provided on the raised flat surface formed on the other pedestal; a gate electrode (6) provided on the substrate between the pair of pedestals; and an organic semiconductor layer (7) arranged in contact with the upper surfaces of the source electrode and the drain electrode. The gate electrode and the lower surface of the organic semiconductor layer vertically oppose each other across a gap region (8), and the side surfaces of the pedestals facing the gap region are shaped such that the lower side edges recede apart from the gate electrode with respect to the upper side edges.

Abstract: A Raman detecting system includes a bowl shaped metal nanostructure array configured to load a sample, a projecting module configured to project a beam of light to the bowl shaped metal nanostructure array, and a receiving module configured to collect the light scattered by the bowl shaped metal nanostructure array. The bowl shaped metal nanostructure array includes a substrate having a surface and a number of particle-in-bowl structures located on the surface of the substrate. Each particle-in-bowl structure includes a bowl shaped concave structure and a protruding member protruding from the bowl shaped concave structure. The protruding member is integrated with the bowl shaped concave structure.

Abstract: System, devices and methods are presented that provide an imaging array fabrication process method, comprising fabricating an array of semiconductor imaging elements, interconnecting the elements with stretchable interconnections, and transfer printing the array with a pre-strained elastomeric stamp to a secondary non-planar surface.

Abstract: The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Abstract: A semiconductor device includes a first-conductive type first pillar, a first dielectric surrounding the first pillar, a gate surrounding the dielectric, a second pillar underneath the first pillar, and a third pillar on a top of the first pillar. The second pillar has a second-conductive type region in a surface thereof except at least a part of a contact surface with the first pillar, and a first-conductive type region surrounded by the second-conductive type region. The third pillar has a second-conductive type impurity region in a surface thereof except a part of a contact surface with the first pillar, and a first-conductive type region therein and surrounded by the second-conductive type region of the third pillar. The first-conductive type region of each of the second and third pillars has a length greater than that of a depletion layer extending from a base of the second-conductive type region of one of the second and third pillars.

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract: A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces.

Abstract: A method of manufacturing a thin-film transistor is provided, including preparing ink including a solution in which a graphene oxide, a reduced graphene oxide, or a combination thereof is dispersed, forming the ink on a substrate in the form of a pattern, and forming a source electrode and a drain electrode that are positioned at edges of the pattern and a semiconductor channel positioned between the electrodes by a coffee-ring effect in the ink by using the graphene oxide, the reduced graphene oxide, or the combination thereof within the formed pattern.

Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.