Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device) Patents (Class 257/9)
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Patent number: 10600696Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.Type: GrantFiled: May 23, 2019Date of Patent: March 24, 2020Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Zhengyong Zhu
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Patent number: 10600638Abstract: A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.Type: GrantFiled: October 24, 2016Date of Patent: March 24, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John Zhang
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Method for coating thin film in rolling manner and apparatus for coating thin film by using the same
Patent number: 10583452Abstract: A method for coating a thin film in a rolling manner and a thin film coating apparatus are provided. The method includes: floating a thin film material on a liquefied material; rolling a cylindrical substrate after contacting the cylindrical substrate with the thin film material; and coating the thin film material on a surface of the cylindrical substrate by using an attraction force between the surface of the cylindrical substrate and the thin film material.Type: GrantFiled: April 6, 2017Date of Patent: March 10, 2020Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Taek-Soo Kim, Sumin Kang -
Patent number: 10578891Abstract: Embodiments are directed to a microwave-to-optical transducer device. The device includes an anchorage structure that includes a bar extending in a plane and laterally delimiting two voids on each longitudinal side of the bar. That is, the two voids are arranged side-by-side in said plane. The device further includes a piezoelectric beam structured as an optical cavity (e.g., as a 1D photonic crystal cavity), where the beam extends transversally to the bar, parallel to said plane, and is anchored on a resting point on the bar. The beam extends outwardly, beyond the resting point and on each side thereof, so as to overhang each of the two voids. Embodiments are further directed to related microwave circuits, including a microwave-to-optical transducer such as described above and, in particular, to superconducting microwave circuits configured as quantum information processing devices.Type: GrantFiled: August 13, 2018Date of Patent: March 3, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Katharina Schmeing, Paul F. Seidler
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Patent number: 10559675Abstract: Embodiments of the present invention are directed to a method that incorporates a germanium pull-out process to form semiconductor structures having stacked silicon nanotubes. In a non-limiting embodiment of the invention, a sacrificial layer is formed over a substrate. The sacrificial layer includes a first type of semiconductor material. A pull-out layer is formed on the sacrificial layer. The first type of semiconductor material from the sacrificial layer is removed to form a silicon-rich layer on a surface of the sacrificial layer. The sacrificial layer can be removed such that the silicon-rich layer defines a silicon nanotube.Type: GrantFiled: December 21, 2017Date of Patent: February 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juntao Li, Kangguo Cheng, Choonghyun Lee, Peng Xu
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Patent number: 10553496Abstract: A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistors includes a germanium nanowire, a III-V compound layer surrounding the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.Type: GrantFiled: December 8, 2017Date of Patent: February 4, 2020Assignee: Zing Semiconductor CorporationInventor: Deyuan Xiao
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Patent number: 10546994Abstract: A technique relates a superconducting microwave cavity. An array of posts has different heights in the cavity, and the array supports a localized microwave mode. The array of posts includes lower resonant frequency posts and higher resonant frequency posts. The higher resonant frequency posts are arranged around the lower resonant frequency posts. A first plate is opposite a second plate in the cavity. One end of the lower resonant frequency posts is positioned on the second plate so as to be electrically connected to the second plate. Another end of the lower resonant frequency posts in the array is open so as not to form an electrical connection to the first plate. Qubits are connected to the lower resonant frequency posts in the array of posts, such that each of the qubits is physically connected to one or two of the lower resonant frequency posts in the array of posts.Type: GrantFiled: August 28, 2018Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oliver Dial, Jay M. Gambetta, Douglas T. McClure, III, Matthias Steffen
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Patent number: 10546957Abstract: A semiconductor device includes a semiconductor wafer having one or more suspended nanosheet extending between first and second source/drain regions. A gate structure wraps around the nanosheet stack to define a channel region located between the source/drain regions. The semiconductor device further includes a first all-around source/drain contact formed in the first source/drain region and a second all-around source/drain contact formed in the second source/drain region. The first and second all-around source/drain contacts each include a source/drain epitaxy structure and an electrically conductive external portion that encapsulates the source/drain epitaxy structure.Type: GrantFiled: January 11, 2018Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peng Xu, Chun Wing Yeung, Chen Zhang
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Patent number: 10535737Abstract: A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first direction, in which the channel structure has plurality of first portions and plurality of second portions alternately stacked, and a width of the first portions is smaller than that of the second portions in a second direction different from the first direction. The gate structure is disposed over the substrate and crossing the channel structure along the second direction, in which the gate structure is in contact with the first portions and the second portions.Type: GrantFiled: October 27, 2017Date of Patent: January 14, 2020Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Fang-Liang Lu, Chia-Che Chung, Yu-Jiun Peng, Chee-Wee Liu
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Patent number: 10522622Abstract: A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires.Type: GrantFiled: May 14, 2018Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Ching Cheng, I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang, Hung-Li Chiang
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Patent number: 10522694Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.Type: GrantFiled: September 28, 2017Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Sheng Chen, Szu-Wei Huang, Hung-Li Chiang, Cheng-Hsien Wu, Chih Chieh Yeh
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Patent number: 10489477Abstract: Systems, devices, articles, methods, and techniques for advancing quantum computing by removing unwanted interactions in one or more quantum processor. One approach includes creating an updated plurality of programmable parameters based at least in part on a received value for the characteristic magnetic susceptibility of the qubit in the at least one quantum processor, and returning the updated plurality of programmable parameters. Examples programmable parameters include local biases, and coupling values characterizing the problem Hamilton.Type: GrantFiled: May 18, 2018Date of Patent: November 26, 2019Assignee: D-WAVE SYSTEMS INC.Inventor: Trevor Michael Lanting
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Patent number: 10483105Abstract: Provided is a method for growing a nanowire, including: providing a substrate with a base portion having a first surface and at least one support structure extending above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending from the root end; and elastically bending the at least one nanowire.Type: GrantFiled: May 13, 2016Date of Patent: November 19, 2019Assignee: STC.UNMInventors: Seung-Chang Lee, Steven R. J. Brueck
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Patent number: 10468312Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.Type: GrantFiled: October 2, 2017Date of Patent: November 5, 2019Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Zhengyong Zhu
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Patent number: 10446719Abstract: The disclosed technology provides micro-assembled micro-LED displays and lighting elements using arrays of micro-LEDs that are too small (e.g., micro-LEDs with a width or diameter of 10 ?m to 50 ?m), numerous, or fragile to assemble by conventional means. The disclosed technology provides for micro-LED displays and lighting elements assembled using micro-transfer printing technology. The micro-LEDs can be prepared on a native substrate and printed to a display substrate (e.g., plastic, metal, glass, or other materials), thereby obviating the manufacture of the micro-LEDs on the display substrate. In certain embodiments, the display substrate is transparent and/or flexible.Type: GrantFiled: June 18, 2015Date of Patent: October 15, 2019Assignee: X-Celeprint LimitedInventors: Christopher Bower, Matthew Meitl, David Gomez, Salvatore Bonafede, David Kneeburg, Alin Fecioru, Carl Prevatte
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Patent number: 10431663Abstract: Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.Type: GrantFiled: January 10, 2018Date of Patent: October 1, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ruilong Xie, Balasubramanian Pranatharthiharan, Pietro Montanini, Julien Frougier
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Patent number: 10430493Abstract: Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.Type: GrantFiled: April 5, 2019Date of Patent: October 1, 2019Assignee: Rain Neuromorphics Inc.Inventor: Jack Kendall
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Patent number: 10424696Abstract: Provided are a wavelength converting particle, a method for manufacturing a wavelength converting particle, and a light-emitting diode containing a wavelength converting particle. The wavelength converting particle comprises an organic/inorganic/hybrid perovskite nanocrystal that converts a wavelength of light generated by an excitation light source into a specified wavelength. Accordingly, it is possible to optically stabilize and improve color purity and light-emission performance without changes in a light-emitting wavelength range.Type: GrantFiled: November 6, 2015Date of Patent: September 24, 2019Assignees: POSTECH ACADEMY-INDUSTRY FOUNDATIONInventors: Taewoo Lee, Younghoon Kim, Himchan Cho
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Patent number: 10411090Abstract: Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.Type: GrantFiled: September 24, 2015Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Cory E. Weber, Rishabh Mehandru, Stephen M. Cea
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Patent number: 10403754Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.Type: GrantFiled: May 3, 2018Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha
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Patent number: 10396214Abstract: Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.Type: GrantFiled: March 16, 2018Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
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Patent number: 10374035Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.Type: GrantFiled: July 6, 2017Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Junli Wang
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Patent number: 10367033Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.Type: GrantFiled: August 24, 2018Date of Patent: July 30, 2019Assignee: Micron Technology, Inc.Inventors: Ombretta Donghi, Marcello Ravasio, Samuele Sciarrillo, Roberto Somaschini
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Patent number: 10347760Abstract: A reconfigurable field effect transistor (RFET) includes a nanowire, wherein the nanowire comprises two Schottky contacts, as well as two gate contacts partially enclosing the nanowire in cross section. An integrated circuit can be produced therefrom. The aim of producing CMOS circuits with enhanced functionality and a more compact design is achieved in that the nanowire is divided along the cross section thereof into two nanowire parts, wherein each nanowire part comprises a respective Schottky contact and a respective gate contact, and the two nanowire parts are connected electrically to one another via a common substrate and stand vertically on the substrate. In a nanowire-parts-array, between the nanowire parts, a respective top-gate contact and/or back-gate contact can be formed in a substrate defining a substrate plane.Type: GrantFiled: June 20, 2017Date of Patent: July 9, 2019Assignees: Technische Universität Dresden, NaMLab gGmbHInventors: Tim Baldauf, André Heinzig, Walter Michael Weber
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Patent number: 10347719Abstract: A semiconductor structure. The structure includes first source/drain located in a first source/drain region. The structure includes a second source/drain located in a second source/drain region. The structure includes a plurality of semiconductor nanosheets located between the first source/drain and the second source/drain in a gate region. The structure includes an insulating layer separating the first source drain from a bulk substrate. The bulk substrate may have a first horizontal surface in the gate region, a second horizontal surface in the first source/drain region, and a connecting surface forming an at least partially vertical connection between the first horizontal surface and the second horizontal surface. The insulating layer may be directly on the second horizontal surface and the connecting surface.Type: GrantFiled: July 6, 2018Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
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Patent number: 10332961Abstract: Embodiments are directed to a method of fabricating inner spacers of a nanosheet FET. The method includes forming sacrificial and channel nanosheets over a substrate, removing sidewall portions of the sacrificial nanosheet, and forming a dielectric that extends over the channel nanosheet and within a space that was occupied by the removed sidewall portions of the sacrificial nanosheet. The method further includes forming a top protective spacer over the channel nanosheet and the dielectric, as well as applying a directional etch to the top protective spacer, the channel nanosheet, and the dielectric, wherein the directional etch is configured to be selective to the channel nanosheet and the dielectric, wherein the directional etch is configured to not be selective to the top protective spacer, and wherein applying the directional etch etches portions of the channel nanosheet and portions of the flowable dielectric that are not under the top dielectric.Type: GrantFiled: November 30, 2017Date of Patent: June 25, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-chen Yeh
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Patent number: 10333027Abstract: Disclosed in one embodiment is a light-emitting device comprising: a first semiconductor layer; an active layer arranged on the first semiconductor layer and including a plurality of first uneven portions; an electron blocking layer including a plurality of second uneven portions arranged on the plurality of first uneven portions; and a second semiconductor layer formed on the electron blocking layer, wherein the electron blocking layer has at least two doping concentration peak sections of a p-type dopant in the thickness direction.Type: GrantFiled: May 19, 2016Date of Patent: June 25, 2019Assignee: LG INNOTEK CO., LTD.Inventor: Chong Cook Kim
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Patent number: 10325993Abstract: A device includes a nanowire, a gate dielectric layer and a gate electrode. The nanowire has a sidewall. The gate dielectric layer surrounds the nanowire. The gate electrode surrounds the gate dielectric layer and separated from the nanowire. The gate electrode comprises a sloped sidewall inclined with respect to the sidewall of the nanowire.Type: GrantFiled: September 28, 2017Date of Patent: June 18, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Chih Wang, Yu-Chieh Liao, Tai-I Yang, Hsin-Ping Chen
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Patent number: 10325996Abstract: A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.Type: GrantFiled: October 4, 2017Date of Patent: June 18, 2019Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Franz Hirler, Anton Mauder, Helmut Strack, Frank Kahlmann, Gerhard Miller
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Patent number: 10325820Abstract: Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.Type: GrantFiled: January 10, 2018Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Soon-Cheon Seo, Choonghyun Lee, Injo Ok
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Patent number: 10319846Abstract: A semiconductor structure includes a substrate, an isolation layer disposed over the substrate, a plurality of nanosheet channels, interfacial layers surrounding each of the nanosheet channels, and dielectric layers surrounding each of the interfacial layers. The plurality of nanosheet channels includes first and second sets of two or more nanosheet channels for first and second NFETs and third and fourth sets of two or more nanosheet channels for first and second PFETs. The interfacial layers surrounding the first and third sets of nanosheet channels for the first NFET and the first PFET have a first thickness, and interfacial layers surrounding the second and fourth sets of nanosheets channels for the second NFET and the second PFET have a second thickness smaller than the first thickness. The first NFET has a higher threshold voltage than the second NFET, and the first PFET has a lower threshold voltage than the second PFET.Type: GrantFiled: May 9, 2018Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Takashi Ando, ChoongHyun Lee, Jingyun Zhang, Pouya Hashemi
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Patent number: 10319676Abstract: Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.Type: GrantFiled: March 16, 2018Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robin H. Chao, James J. Demarest, Nicolas J. Loubet
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Patent number: 10312323Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.Type: GrantFiled: July 17, 2017Date of Patent: June 4, 2019Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Junli Wang
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Patent number: 10312329Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate structure including a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the first material layer includes a nanowire; forming a base layer on the substrate structure; selectively growing a graphene layer on the base layer; forming a second dielectric layer on the graphene layer; forming an electrode material layer on the substrate structure to cover the second dielectric layer; defining an active region; and forming a gate by etching at least a portion of a stack layer to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, where the gate structure includes a portion of the electrode material layer and the second dielectric layer.Type: GrantFiled: August 22, 2017Date of Patent: June 4, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Ming Zhou
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Patent number: 10296352Abstract: Systems and methods of processing using a quantum processor are described. A method includes obtaining a problem Hamiltonian and defining a nested Hamiltonian with a plurality of logical qubits by embedding a logical KN representing the problem Hamiltonian into a larger KC×N, where N represents a number of the logical qubits and C represents a nesting level defining the amount of hardware resources for the nest Hamiltonian. The method also includes encoding the nested Hamiltonian into the plurality of physical qubits of the quantum processor; and performing a quantum annealing process with the quantum processor after the encoding.Type: GrantFiled: June 15, 2017Date of Patent: May 21, 2019Assignee: University of Southern CaliforniaInventors: Daniel Lidar, Tameem Albash, Walter Vinci
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Patent number: 10297671Abstract: A method is presented for forming a nanosheet structure having a uniform threshold voltage (Vt). The method includes forming a conductive barrier surrounding a nanosheet, forming a first work function conducting layer over the conductive barrier layer, and forming a conducting layer adjacent the first work function conducting layer, the conducting layer defining a first region and a second region. The method further includes forming a second work function conducting layer over the second region of the conducting layer to compensate for threshold voltage offset between the first and second regions of the conducting layer.Type: GrantFiled: July 20, 2018Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, ChoongHyun Lee, Vijay Narayanan, Koji Watanabe
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Patent number: 10290738Abstract: One illustrative method disclosed includes, among other things, forming a gate structure around a fin and above a layer of insulating material, forming a gate spacer adjacent the gate structure and a fin spacer positioned adjacent the fin above the insulating material, the fin spacer leaving an upper surface of the fin exposed, and performing at least one etching process to remove at least a portion of the fin positioned between the fin spacer, the fin having a recessed upper surface that at least partially defines a fin recess positioned between the fin spacer. In this example, the method further includes forming an epi semiconductor material on the fin recess and removing the fin spacer from adjacent the epi semiconductor material while leaving a portion of the gate spacer in position adjacent the gate structure.Type: GrantFiled: April 10, 2017Date of Patent: May 14, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Christopher M. Prindle, Kwan-Yong Lim
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Patent number: 10283607Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first diffusion region, a second diffusion region, and a first nanowire. The second GAA transistor includes: a third diffusion region, a fourth diffusion region, and a second nanowire. The first diffusion region, the second diffusion region, and the first nanowire are symmetrical with the third diffusion region, the fourth diffusion region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow through the first nanowire, and the second GAA transistor is arranged to provide a second current to flow through the second nanowire.Type: GrantFiled: February 27, 2018Date of Patent: May 7, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chung-Hui Chen
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Patent number: 10283649Abstract: A Schottky barrier diode includes a graphene nanoribbon, a first electrode connected to one end of the graphene nanoribbon, and a second electrode connected to the other end of the graphene nanoribbon. The graphene nanoribbon includes a first part and a second part which are connected in the length direction of the graphene nanoribbon and which differ in electronic state. For example, edges of the first part in a length direction of the graphene nanoribbon are terminated with a first modifying group and edges of the second part in the length direction of the graphene nanoribbon are terminated with a second modifying group.Type: GrantFiled: May 19, 2017Date of Patent: May 7, 2019Assignee: FUJITSU LIMITEDInventors: Shintaro Sato, Hideyuki Jippo
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Patent number: 10272647Abstract: Described herein are methods for improved transfer of graphene from formation substrates to target substrates. In particular, the methods described herein are useful in the transfer of high-quality chemical vapor deposition-grown monolayers of graphene from metal, e.g., copper, formation substrates via non-polymeric methods. The improved processes provide graphene materials with less defects in the structure.Type: GrantFiled: December 14, 2015Date of Patent: April 30, 2019Assignee: Corning IncorporatedInventors: Benedict Yorke Johnson, Prantik Mazumder, Kamal Kishore Soni
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Patent number: 10274645Abstract: A manufacturing method of micro-nano structure antireflective coating layer and a display apparatus thereof are described. The method includes providing a substrate, forming a silicon oxide layer on the substrate, forming a graphene layer with a hexagonal honeycomb lattice on the silicon oxide layer, and forming a bottom surface of the antireflective coating layer in the nucleation points by serving the graphene layer as a growing base layer, wherein a diffusion length and an atomic mass of diffusion atoms of the antireflective coating layer are decreased with time by a gradient growing manner to form a upper surface of the antireflective coating layer.Type: GrantFiled: December 28, 2016Date of Patent: April 30, 2019Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.Inventor: Guowei Zha
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Patent number: 10252914Abstract: Methods of producing layers of patterned graphene with smooth edges are provided. The methods comprise the steps of fabricating a layer of crystalline graphene on a surface, wherein the layer of crystalline graphene has a crystallographically disordered edge, and decreasing the crystallographic disorder of the edge of the layer of crystalline graphene by heating the layer of crystalline graphene on the surface at an elevated temperature in a catalytic environment comprising carbon-containing molecules.Type: GrantFiled: June 16, 2016Date of Patent: April 9, 2019Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATIONInventors: Michael Scott Arnold, Padma Gopalan, Nathaniel S. Safron, Myungwoong Kim
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Patent number: 10211359Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.Type: GrantFiled: November 18, 2016Date of Patent: February 19, 2019Assignee: Northrop Grumman Systems CorporationInventors: Narsingh B. Singh, John V. Veliadis, Bettina Nechay, Andre Berghmans, David J. Knuteson, David Kahler, Brian Wagner, Marc Sherwin
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Patent number: 10186351Abstract: A system for providing electrical and optical interconnection using a 3D non-carbon-based topological insulator (TI) is disclosed. The system includes a length of the TI having a tube shape having wall thickness of about 10 nm to about 200 nm and a hollow interior portion surrounded by an interior surface of the TI. The length includes a first end and a second end, wherein the first end is configured to receive an optical signal, an electrical signal, or both. The optical signal propagates in the hollow interior portion along the length to the second end by total internal reflection due to a refractive index of the interior surface of the TI. The electrical signal propagates along an external surface of the TI to the second end.Type: GrantFiled: November 16, 2017Date of Patent: January 22, 2019Assignee: THE BOEING COMPANYInventors: Jeffrey H. Hunt, Wayne R. Howe, Angela W. Li
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Patent number: 10181495Abstract: A process for producing a light emitting diode device, the process including: forming a plurality of quantum dots on a surface of a layer including a first area and a second area, the forming including: exposing the first area of the surface to light having a first wavelength while exposing the first area to a quantum dot forming environment that causes the quantum dots in the first area to form at a first growth rate while the quantum dots have a dimension less than a first threshold dimension; exposing the second area of the surface to light having a second wavelength while exposing the second area to the quantum dot forming environment that causes the quantum dots in the second area to form at a third growth rate while the quantum dots have a dimension less than a second threshold dimension; and processing the layer to form the LED device.Type: GrantFiled: December 21, 2017Date of Patent: January 15, 2019Assignee: X Development LLCInventors: Martin Friedrich Schubert, Michael Jason Grundmann
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Patent number: 10170374Abstract: A semiconductor device includes at least one n-channel, at least one p-channel, at least one first high-k dielectric sheath, at least one second high-k dielectric sheath, a first metal gate electrode and a second metal gate electrode. The first high-k dielectric sheath surrounds the n-channel. The second high-k dielectric sheath surrounds the p-channel. The first high-k dielectric sheath and the second high-k dielectric sheath comprise different high-k dielectric materials. The first metal gate electrode surrounds the first high-k dielectric sheath. The second metal gate electrode surrounds the second high-k dielectric sheath.Type: GrantFiled: June 26, 2017Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu, Chih-Chieh Yeh, Chih-Sheng Chang
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Patent number: 10139655Abstract: The spin-Hall effect can be used to modulate the linear polarization of light via the magneto-optical Kerr effect. A material is illuminated while simultaneously passing a modulated electric current through the material, so that reflected light has a new linear polarization that differs from the initial linear polarization to a degree depending on the amplitude of the modulated electric current.Type: GrantFiled: April 27, 2016Date of Patent: November 27, 2018Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Olaf M. J. van't Erve, Connie H. Li, Berend T. Jonker, Aubrey T. Hanbicki, Kathleen M. McCreary
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Patent number: 10141424Abstract: Method of manufacturing a structure with semiconducting bars suitable for forming one at least one transistor channel, including the following steps: a) make a semiconducting structure, composed of an alternation of first bars based on a first material and second bars based on a second material, the second material being a semiconducting material, then b) remove exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around the second bars, then c) grow a given semiconducting material (25) around the second bars (6c) in the opening, the given semiconducting material having a mesh parameter different from the mesh parameter of the second material (7) so as to induce a strain on the sheaths based on the given semiconducting material.Type: GrantFiled: May 24, 2017Date of Patent: November 27, 2018Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, IBM CORPORATIONInventors: Remi Coquand, Emmanuel Augendre, Nicolas Loubet, Shay Reboh
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Patent number: 10121854Abstract: Provided are electronic devices and methods of manufacturing same. An electronic device includes an energy barrier forming layer on a substrate, an upper channel material layer on the substrate, and a gate electrode that covers the upper channel material layer and the energy barrier forming layer. The gate electrode includes a side gate electrode portion that faces a side surface of the energy barrier forming layer. The side gate electrode may be configured to cause an electric field to be applied directly on the energy barrier forming layer via the side surface of the energy barrier forming layer, thereby enabling adjustment of the energy barrier between the energy barrier forming layer and the upper channel material layer. The electronic device may further include a lower channel material layer that is provided on the substrate and does not contact the upper channel material layer.Type: GrantFiled: May 25, 2017Date of Patent: November 6, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jinseong Heo, Kiyoung Lee, Jaeho Lee, Seongjun Park
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Patent number: 10121877Abstract: A method for fabricating a semiconductor device includes forming a semiconductor fin over a substrate. A first doped region is formed on a first end of the semiconductor fin. A second doped region is formed on a second end of the semiconductor fin. An extended contact is formed on the second doped region. A portion of the extended contact extends past an end of the semiconductor fin in a direction orthogonal to a channel of the semiconductor fin. A contact extension is formed on the portion of the extended contact extending past the end of the semiconductor fin. A contact is formed on the first doped region.Type: GrantFiled: September 13, 2017Date of Patent: November 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence B. Hook, Joshua M. Rubin, Tenko Yamashita