Abstract: To provide a method for manufacturing a power storage device which enables improvement in performance of the power storage device, such as an increase in discharge capacity. To provide a method for forming a semiconductor region which is used for a power storage device or the like so as to improve performance. A method for forming a crystalline semiconductor region includes the steps of: forming, over a conductive layer, a crystalline semiconductor region that includes a plurality of whiskers including a crystalline semiconductor by an LPCVD method; and performing heat treatment on the crystalline semiconductor region after supply of a source gas containing a deposition gas including silicon is stopped. A method for manufacturing a power storage device includes the step of using the crystalline semiconductor region as an active material layer of the power storage device.

Abstract: Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.

Abstract: A method of making a thin film resistor includes: forming a doped region in a semiconductor substrate; forming a dielectric layer over the substrate; forming a thin film resistor over the dielectric layer; forming a contact hole in the dielectric layer before annealing the thin film resistor, wherein the contact hole exposes a portion of the doped region; and performing rapid thermal annealing on the thin film resistor after forming the contact hole.

Abstract: A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first oxide layer and a second, “L-shaped,” electrode is formed on the insulating member. An electrical contact is connected to the horizontal portion of the second electrode. A bridge of memory material extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall spacer insulating member.

Abstract: A passive integrated circuit formed on a substrate, including contact areas of a conductive material specifically capable of receiving bonding pads, wherein the conductive material further creates connections between regions of a lower metallization level.

Abstract: An energy storage device (300), the device (300) comprising a substrate (102), a steric structure (104) formed on and/or in a main surface (106) of the substrate (102), a current collector stack (202) formed on the steric structure (104), and an electric storage stack (302) formed on the current collector stack (202), wherein side walls (108) of the steric structure (104) and the main surface (106) of the substrate (102) enclose an acute angle of more than 80 degrees.

Abstract: Provided are a resistive memory device and a method of fabricating the same. The resistive memory device comprises an electron channel layer formed by means of a swelling process and an annealing process. Thus, conductive nanoparticles are uniformly dispersed in the electron channel layer to improve reliability of the resistive memory device. According to the method, an electron channel layer is formed by means of a printing process, a swelling process, and an annealing process. Thus, fabrication time is reduced.

Abstract: A phase change memory device includes a plurality of word lines, a plurality of bit lines disposed to be crossed with the plurality of word lines, switching devices disposed at intersections of the plurality of word lines and the plurality of bit lines, heating electrodes connected to the switching devices respectively, heat absorbing layers disposed between adjacent heating electrodes, and phase change layers formed on the heating electrodes and the heat absorbing layers and extended in the same direction of the bit line.

Abstract: An electrically actuated device (10) comprises an active region (30) disposed between a first electrode (12) and a second electrode (14); a substantially nonrandom distribution of dopant initiators at an interface between the active region and the first electrode; and a substantially nonrandom distribution of dopants in a portion of the active region adjacent to the interface.

Abstract: Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor.

Abstract: A nanoscale switching device is provided, comprising: a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region having at least one non-conducting layer comprising an electronically semiconducting or nominally insulating and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field; and a source layer interposed between the first electrode and the second electrode and comprising a highly reactive and highly mobile ionic species that reacts with a component in the switching material to create dopants that are capable of drifting through the non-conducting layer under an electric field, thereby controlling dopant profile by ionic modulation. A crossbar array comprising a plurality of the nanoscale switching devices is also provided, along with a process for making at least one nanoscale switching device.

Abstract: The disclosure identified as methods of mounting integrated circuits, including solar cells, to a substrate wherein the circuits are mounted prior to being singulated into discrete die. Once the semiconductor die sites or other circuits are formed on a wafer, the wafer will be attached, either whole, or divided into one or more multi-die site wafer segments, to a substrate. This attachment may be by conventional surface mount technology, for example. After such mounting, the individual die sites on the wafer segments will be singulated to form discrete die already mounted to the supporting substrate. The singulation may be preferably performed by laser dicing of the wafer segments.

Abstract: High voltage semiconductor devices and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming first trenches in an insulating material. A trap region is formed in the insulating material by introducing an impurity into the first trenches. The first trenches are filled with a conductive material.

Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.

Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The non-ohmic element has a first semiconductor layer which includes at least one diffusion buffering region and a conductive layer adjacent to the first semiconductor layer. The diffusion buffering region is different in crystal structure from a semiconductor region except for the diffusion buffering region in the first semiconductor layer.

Abstract: According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion.

Abstract: According to one embodiment, a method is described for manufacturing a semiconductor device. The method can form a conductive layer including tungsten on a foundation layer. The method can form a trench by selectively etching the conductive layer. The trench is shallower than a depth from a surface of the conductive layer to the foundation layer. The method can form a protective film on a side surface and a bottom surface of the conductive layer in the trench using a gas containing bromine. The protective film includes a compound of the tungsten and the bromine. The method can remove the protective film on the bottom surface of the conductive layer. The method can etch a portion of the conductive layer below the trench with the protective film on the side surface of the conductive layer.

Abstract: In a first aspect, a method of forming a memory cell is provided that includes: (a) forming a layer of dielectric material above a substrate; (b) forming an opening in the dielectric layer; (c) depositing a solution that includes a carbon-based switching material on the substrate; (d) rotating the substrate to cause the solution to flow into the opening and to form a carbon-based switching material layer within the opening; and (e) forming a memory element using the carbon-based switching material layer. Numerous other aspects are provided.

Abstract: The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode.

Abstract: A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes. At least one doped well is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells may be connected in parallel to provide a varactor having complex voltage dependency of capacitance. The buried plate layer and another doped well connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench.

Abstract: According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.

Abstract: A lower electrode may be covered by a protective film to reduce the exposure of the lower electrode to subsequent processing steps or the open environment. As a result, materials that may have advantageous properties as lower electrodes may be utilized despite the fact that they may be sensitive to subsequent processing steps or the open environment.

Abstract: In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided.

Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Abstract: A nonvolatile memory cell including a storage element in series with a diode steering element. At least one interface of the diode steering element is passivated.

Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided between the first interconnect line and the second interconnect line and which includes a non-ohmic element and a memory element, the non-ohmic element including a conductive layer provided on at least one of first and second ends of the cell unit and a silicon portion provided between the first and second ends, the memory element being connected to the non-ohmic element via the conductive layer and storing data in accordance with a reversible change in a resistance state, wherein the non-ohmic element includes a first silicon germanium region in the silicon portion.

Abstract: A phase change memory may be formed which is amenable to multilevel programming. The phase change material may be formed with a lateral extent which does not exceed the lateral extent of an underlying heater. As a result, the possibility of current bypassing the amorphous phase change material in the reset state is reduced, reducing the programming current that is necessary to prevent this situation. In addition, a more controllable multilevel phase change memory may be formed in some embodiments.

Abstract: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor.

Abstract: A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells can be arranged in parallel with a corresponding series of control gates. A select gate can also be disposed in series with the variable-resistance material memory cells. Writing/reading/erasing to a given variable-resistance material memory cell can include turning off the corresponding control gate, while turning on all other control gates. Various devices can include such a variable-resistance material memory array.

Abstract: A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse.

Abstract: Disclosed is a resistance change type nonvolatile memory that has an insulation film structure, is advantageous for the implementation of high integration, and achieves a stable switching characteristic, and a manufacturing method therefor. The memory includes at least an MIM (Metal/Insulator/Metal) structure including an insulation film (2) sandwiched between metal electrodes (1) and (3), and the insulation film (2) includes a laminated structure including a Ta2O5 film and a TiO2 film with a thickness of less than 30 nm. The Ta2O5 film is a stoichiometric amorphous film.

Abstract: An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.

Abstract: A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word lines covered with a dielectric material which defines gaps. An access device within a substrate has a first terminal under a second gap and second terminals under first and third gaps. First and second source lines are in the first and third gaps and are electrically connected to the second terminals. A first electrode in the second gap is electrically connected to the first terminal. A memory element in the second gap is positioned over and electrically connected to the first electrode. A second electrode is positioned over and contacts the memory element. The first contact, the first electrode, the memory element and the second electrode are self aligning. A portion of the memory element may have a sub lithographically dimensioned width.

Abstract: A phase change random access memory includes a semiconductor substrate, a switching device pattern formed on the semiconductor substrate, a bottom electrode contact pattern formed on the switching device pattern, a phase change layer pattern formed on the bottom electrode contact pattern, and an insulating layer disposed at a portion of an contact surface between the bottom electrode contact pattern and the phase change layer pattern.

Abstract: A method of fabricating a phase change random access memory device includes forming a sacrificial layer of a predetermined height within a bottom electrode contact hole. The method also includes forming an insulating layer on a whole resultant structure including the bottom electrode contact hole. The method also includes forming a spacer on a sidewall of the bottom electrode contact hole by etching the insulating layer and removing the sacrificial layer.

Abstract: A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a fuse pattern including a conductive polymer layer formed between the first and second fuse connection patterns and connecting the first and second fuse connection patterns, and a fuse box structure that exposes the fuse pattern.

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

Abstract: A method of making a non-volatile memory device includes providing a substrate having a substrate surface, and forming a non-volatile memory array over the substrate surface. The non-volatile memory array includes an array of semiconductor diodes, and each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface.

Abstract: A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern.

Abstract: A method of manufacturing a nonvolatile memory device having a laminated structure in which a first magnetic material layer, a tunnel insulator film, and a second magnetic material layer are sequentially laminated, in which information is stored when an electric resistance value changes depending on a magnetization reversal state is disclosed. The method includes the steps of: sequentially forming the first magnetic material layer, the tunnel insulator film, and the second magnetic material layer; forming a mask layer on the second magnetic material layer; oxidizing a part uncovered by the mask layer of the second magnetic material layer; and reducing the oxidized part of the second magnetic material layer.

Abstract: A nonvolatile memory device includes at least one switching device and at least one storage node electrically connected to the at least one switching device. The at least one storage node includes a lower electrode, one or more oxygen-deficient metal oxide layers, one or more data storage layers, and an upper electrode. At least one of the one or more metal oxide layers is electrically connected to the lower electrode. At least one of the one or more data storage layers is electrically connected to at least one of the one or more metal oxide layers. The upper electrode is electrically connected to at least one of the one or more data storage layers. A method of manufacturing the nonvolatile memory device includes preparing the at least one switching device and forming the lower electrode, one or more metal oxide layers, one or more data storage layers, and upper electrode.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A phase change memory device includes a semiconductor substrate having a conductive region, a heater electrode formed on the semiconductor substrate and including a connection element which is composed of carbon nanotubes electrically connected with the conductive region, and a phase change pattern layer contacting the connection element of the heater electrode.

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.

Abstract: In some aspects, a method of forming a memory cell is provided that includes (1) forming a steering element above a substrate; and (2) selectively forming a reversible resistance-switching element coupled to the steering element by: (a) forming a material layer on the substrate; (b) etching the material layer; and (c) oxidizing the etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.

Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOx and MOy (where x<y) and in contact with the electrodes (309a, 309c) respectively, and a diffusion layer region (302b) is connected with the lower electrode (309a) to form a memory cell (300), the region (302b) serving as a drain of the transistor (317) upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer (309b).

Abstract: A resistive switching non-volatile memory element is disclosed comprising a resistive switching metal-oxide layer sandwiched between and in contact with a top electrode and a bottom electrode, the resistive switching metal oxide layer having a substantial isotropic non-stoichiometric metal-to-oxygen ratio. For example, the memory element may comprise a nickel oxide resistive switching layer sandwiched between and in contact with a nickel top electrode and a nickel bottom electrode whereby the ratio oxygen-to-nickel of the nickel oxide layer is between 0 and 0.85.

Abstract: In various embodiments, electronic devices containing switchably conductive silicon oxide as a switching element are described herein. The electronic devices are two-terminal devices containing a first electrical contact and a second electrical contact in which at least one of the first electrical contact or the second electrical contact is deposed on a substrate to define a gap region therebetween. A switching layer containing a switchably conductive silicon oxide resides in the gap region between the first electrical contact and the second electrical contact. The electronic devices exhibit hysteretic current versus voltage properties, enabling their use in switching and memory applications. Methods for configuring, operating and constructing the electronic devices are also presented herein.

Abstract: Provided is an electronic component that includes a first bi-layer stack including a first silicon oxide layer and a first silicon nitride layer, a second bi-layer stack including a second silicon oxide layer and a second silicon nitride layer, and a convertible structure which is convertible between at least two states having different electrical properties, where the convertible structure is arranged between the first bi-layer stack and the second bi-layer stack.

Abstract: A structure having a plurality of conductive regions insulated electrically from each other comprises a movable piece supported movably above the upper face of the conductive region, the movable piece having an electrode in opposition to the conductive region, the structure being constructed to be capable of emitting and receiving electric signals through the lower face of the conductive region, the plural conductive regions being insulated by sequentially connected oxidized regions formed from an oxide of a material having through-holes or grooves.