Abstract: According to one embodiment, a nonvolatile memory device includes a substrate, a first electrode, a second electrode, a third electrode, a first memory portion and a second memory portion. The first electrode extends in a first direction and is provided on the substrate. The second electrode extends in a second direction crossing the first direction and is provided on the first electrode. The third electrode extends in a third direction crossing the second direction and is provided on the second electrode. The first memory portion is provided between the first and the second electrodes and has a first oxygen composition ratio and a first layer thickness. The second memory portion is provided between the second and the third electrodes and has at least one of a second oxygen composition ratio different from the first oxygen composition ratio and a second layer thickness different from the first layer thickness.

Abstract: Embodiments of the current invention include methods of forming a strontium titanate (SrTiO3) film using atomic layer deposition (ALD). More particularly, the method includes forming a plurality of titanium oxide (TiO2) unit films using ALD and forming a plurality of strontium oxide (SrO) unit films using ALD. The combined thickness of the TiO2 and SrO unit films is less than approximately 5 angstroms. The TiO2 and SrO units films are then annealed to form a strontium titanate layer.

Abstract: A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a first electrode length according to a thickness of a second spacer layer and a second electrode formed from the second spacer layer having a second electrode length according to the thickness of the second spacer layer are formed on sidewalls of the sidewall insulating member. A bridge of memory material having a bridge width extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall insulating member, wherein the bridge comprises memory material.

Abstract: An electronic component (100, 1400) comprises a first electrode (106), a second electrode (107), a convertible structure (102) electrically coupled between the first electrode (106) and the second electrode (107), being convertible between at least two states by heating and having different electrical properties in different ones of the at least two states, and a retention enhancement structure (108, 1402) arranged between the first electrode (106) and the second electrode (107), connected to the convertible structure (102) and configured for suppressing conversion between different ones of the at least two states in the absence of heating.

Abstract: A nonvolatile memory device using a resistance material and a method of fabricating the same are provided. The nonvolatile memory device includes a switching element, and a data storage part electrically connected to the switching element. In the data storage part, a lower electrode is connected to the switching element, and an insulating layer is formed on the lower electrode to a predetermined thickness. The insulating layer has a contact hole exposing the lower electrode. A data storage layer is filled in the contact hole and the data storage layer is formed of transition metal oxide. An upper electrode is formed on the insulating layer and the data storage layer.

Abstract: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.

Abstract: Fabricating a cross-point memory structure using two lithography steps with a top conductor and connector or memory element and a bottom conductor orthogonal to the top connector. A first lithography step followed by a series of depositions and etching steps patterns a first channel having a bottom conductor. A second lithography step followed by a series of depositions and etching steps patterns a second channel orthogonal to the first channel and having a memory element connecting the an upper conductor and the lower conductor at their overlaid intersections.

Abstract: A semiconductor device (100) of the present invention has a structure in which an interlayer insulating layer (115) is formed on an uppermost wire (114), contacts (116, 117) penetrate the interlayer insulating layer (115), a lower electrode (118a) of the resistance variable element is formed on the interlayer insulating layer (115) to cover the contact (116), and resistance variable layer (119) is formed on the interlayer insulating layer (115) to cover the lower electrode (118a) and the contact (117). The contact (116) and the lower electrode (118a) serve as a first terminal, while the contact (117) serves as a second terminal.

Abstract: A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes.

Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.

Abstract: A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

Abstract: The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a double subtractive process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a double subtractive process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to rails for forming memory lines and at least one depth corresponds to pillars for forming memory cells. Numerous other aspects are disclosed.

Abstract: An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.

Abstract: A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions and a memory material element therebetween. The lower memory material layer is in electrical contact with a bottom electrode. The lower memory material layer has an average lateral dimension. The memory material element defines an electrical property state change region therein and has a minimum lateral dimension which is substantially less than the average lateral dimension. In some examples the memory material element is a tapered structure with the electrical property state change region at the junction of the memory material element and the lower memory material layer.

Abstract: Microelectronic structures and devices, and method of fabricating a three-dimensional microelectronic structure is provided, comprising passing a first precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures to enhance formation of a first portion of said three-dimensional microelectronic structure; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said first portion of a selected three-dimensional microelectronic structure is formed from said first precursor material; positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs; passing a second precursor material for a selected three-dimensional mi

Abstract: A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.

Abstract: A non volatile memory cell that includes a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including dielectric material and metal atoms; and a second electrode. In other embodiments, a memory array is disclosed that includes a plurality of non volatile memory cells, each non volatile memory cell including a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including clusters of a first electrically conductive atomic component interspersed in an oxidized second atomic component; and a second electrode; at least one word line; and at least one bit line, wherein the word line is orthogonal to the bit line and each of the plurality of non volatile memory cells are operatively coupled to a word line and a bit line.

Abstract: The memory element has a structure at least including a first conductive layer, a second conductive layer, and a memory layer disposed between the first conductive layer and the second conductive layer. The memory layer is formed by a droplet discharge method using nanoparticles of a conductive material each of which is coated with an organic thin film. Specifically, a composition in which nanoparticles of a conductive material each of which is coated with an organic thin film are dispersed in a solvent is discharged (ejected) as ink droplets, and the solvent is dried to be vaporized to form the memory layer. Accordingly, a memory element can be formed simply. In addition, efficiency in the use of materials can be improved and yield is also improved, so that the memory element can be provided at low cost.

Abstract: A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first conductivity type, wherein the base layer of a first conductivity type is the substrate base or is a doped layer over the substrate base. At least one doped region of a second conductivity type is below the surface of said first layer, and extends to form a first junction with the base layer. A doped surface layer of a first conductivity type is over the at least one region of a second conductivity type and forms a second junction with said at least one region of a second conductivity type.

Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Abstract: Some embodiments include devices that contain bundles of CNTs. An undulating topography extends over the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is directly over the CNTs, with the material being a plurality of particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width. Some embodiments include methods in which a plurality of crossed carbon nanotubes are formed over a semiconductor substrate. The CNTs form an undulating upper topography extending across the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is deposited over the CNTs, with the material being deposited as particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width.

Abstract: A multifunction MENS element includes a first cantilever, a second cantilever and a MENS component. The first cantilever, the second cantilever and the MENS component together form a MENS structure. The MENS component includes an inductor device.

Abstract: A semiconductor device is made by providing an integrated passive device (IPD). Through-silicon vias (TSVs) are formed in the IPD. A capacitor is formed over a surface of the IPD by depositing a first metal layer over the IPD, depositing a resistive layer over the first metal layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the resistive and dielectric layers. The first metal layer and the resistive layer are electrically connected to form a resistor and the first metal layer forms a first inductor. A wafer supporter is mounted over the IPD using an adhesive material and a third metal layer is deposited over the IPD. The third metal layer forms a second inductor that is electrically connected to the capacitor and the resistor by the TSVs of the IPD. An interconnect structure is connected to the IPD.

Abstract: A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. Methods for making the memory cell are described.

Abstract: Disclosed herein is a storage element including: a first electrode; a second electrode formed in a position opposed to the first electrode; and a variable-resistance layer formed so as to be interposed between the first electrode and the second electrode. The first electrode is a tubular object, and is formed so as to be thicker on an opposite side from the variable-resistance layer than on a side of the variable-resistance layer.

Abstract: A method for manufacturing a nonvolatile storage device including: a plurality of first electrodes aligning in a first direction; a plurality of second electrodes aligning in a second direction nonparallel to the first direction and provided above the first electrodes; and a first storage unit provided between the first electrode and the second electrode and including a first storage layer, a resistance of the first storage layer changing by at least one of an applied electric field and an applied current, the method includes: stacking a first electrode film forming a first electrode and a first storage unit film forming a first storage unit on a major surface of a substrate; processing the first electrode film and the first storage unit film into a strip shape aligning in the first direction; burying a sacrifice layer between the processed first electrode films and between the processed first storage unit films; forming a second electrode film forming a second electrode on the first storage unit film and the

Abstract: A semiconductor device comprising: a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions.

Abstract: A method of constructing a solid-state energy-density micro radioisotope power source device. In such embodiments, the method comprises depositing the pre-voltaic semiconductor composition, comprising a semiconductor material and a radioisotope material, into a micro chamber formed within a power source device body. The method additionally includes heating the body to a temperature at which the pre-voltaic semiconductor composition will liquefy within the micro chamber to provide a liquid state composite mixture. Furthermore, the method includes cooling the body and liquid state composite mixture such that liquid state composite mixture solidifies to provide a solid-state composite voltaic semiconductor, thereby providing a solid-state high energy-density micro radioisotope power source device.

Abstract: A semiconductor die has an RF coupler and balun integrated on a common substrate. The RF coupler includes first and second conductive traces formed in close proximity. The RF coupler further includes a resistor. The balun includes a primary coil and two secondary coils. A first capacitor is coupled between first and second terminals of the semiconductor die. A second capacitor is coupled between a third terminal of the semiconductor die and a ground terminal. A third capacitor is coupled between a fourth terminal of the semiconductor die and the ground terminal. A fourth capacitor is coupled between the high side and low side of the primary coil. The integration of the RF coupler and balun on the common substrate offers flexible coupling strength and signal directivity, and further improves electrical performance due to short lead lengths, reduces form factor, and increases manufacturing yield.

Abstract: A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first oxide layer and a second, “L-shaped,” electrode is formed on the insulating member. An electrical contact is connected to the horizontal portion of the second electrode. A bridge of memory material extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall spacer insulating member.

Abstract: Methods for making a programmable metallization memory cell are disclosed.

Abstract: Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a number of conductive elements overlaid with a first layer of nanowires, at least some of the conductive elements electrically coupled to more than one of the nanowires through individual switching junctions, each of the switching junctions configured in either a low-conductance state or a high-conductance state; and switching a portion of the switching junctions from the low-conductance state to the high-conductance state or the high-conductance state to the low-conductance state so that individual nanowires of the first layer of nanowires are electrically coupled to different conductive elements of the number of conductive elements using a different one of the switching junctions configured in the high-conductance state.

Abstract: To provide a semiconductor device which is higher functional and reliable and a technique capable of manufacturing the semiconductor device with a high yield at low cost without complexing the apparatus or process. At least one of a first conductive layer and a second conductive layer is formed containing one kind or plural kinds of indium, tin, lead, bismuth, calcium, manganese, or zinc; or oxidation treatment is performed at least one of interfaces between an organic compound layer and the first conductive layer and between the organic compound layer and the second conductive layer. The first conductive layer, the organic compound layer, and the second conductive layer which are formed over a first substrate with a peeling layer interposed therebetween can be peeled from the first substrate with the peeling layer, and transposed to a second substrate.

Abstract: Embodiments of the present invention provide a method that cools a substrate to a temperature below 10° C. and then implants ions into the substrate while the temperature of the substrate is below 10° C. The implanting causes damage to a first depth of the substrate to create an amorphized region in the substrate. The method forms a layer of metal on the substrate and heats the substrate until the metal reacts with the substrate and forms a silicide region within the amorphized region of the substrate. The depth of the silicide region is at least as deep as the first depth.

Abstract: An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the invention the PN junction between the region and the poly fuse is reverse biased.

Abstract: A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes. At least one doped well is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells may be connected in parallel to provide a varactor having complex voltage dependency of capacitance. The buried plate layer and another doped well connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench.

Abstract: A method of forming a variable resistance memory device includes forming an opening in an insulating layer, and forming a variable resistance layer by filling the opening with an antimony rich antimony-tellurium compound.

Abstract: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor.

Abstract: An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having improved electrical properties, in particular with regard to the use as an ESD protection element.

Abstract: A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.

Abstract: An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically connected to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region.

Abstract: A first passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out or data-input purposes only, a plurality of conducting pins isolated from one another.

Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

Abstract: A semiconductor device has an integrated passive device (IPD) formed on a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed on the front side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed on the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed on the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed on the substrate and electrically connects the conductive layer to a ground point.

Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Abstract: In the method a first layer, particularly of amorphous silicon, is deposited on the surface of a substrate with trenches. Part of this surface is covered with a protective layer. The first layer is thereafter maskless removed with a dry etching treatment on the substrate surface while it is kept within the trench.

Abstract: A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via.

Abstract: Method for making an electromechanical component on a plane substrate and comprising at least one structure vibrating in the plane of the substrate and actuation electrodes. The method comprises at least the following steps in sequence: formation of the substrate comprising one silicon area partly covered by two insulating areas, formation of a sacrificial silicon and germanium alloy layer by selective epitaxy starting from the uncovered part of the silicon area, formation of a strongly doped silicon layer by epitaxy, comprising a monocrystalline area arranged on said sacrificial layer and two polycrystalline areas arranged on insulating areas, simultaneous formation of the vibrating structure and actuation electrodes, by etching of a predetermined pattern in the monocrystalline area designed to form spaces between the electrodes and the vibrating structure, elimination of said sacrificial silicon and germanium alloy layer by selective etching.

Abstract: A memory cell includes a first electrode, a second electrode, and phase-change material between the first electrode and the second electrode. The phase-change material defines a narrow region. The memory cell includes first insulation material having a first thermal conductivity and contacting the phase-change material. A maximum thickness of the first insulation material contacts the narrow region. The memory cell includes a second insulation material having a second thermal conductivity greater than the first thermal conductivity and contacting the first insulation material.