Characterized By The Substrate (epo) Patents (Class 257/E21.119)
  • Publication number: 20080286953
    Abstract: In manufacturing an SOI substrate, in a case where a step is present in a surface to be bonded, a substrate may warp and the contact area becomes small due to the step, an SOI layer having a desired shape cannot be obtained in some cases. However, the present invention provides an SOI substrate having a desired shape even when a step is produced on a surface to be bonded. Between steps on the surface to be bonded, dummy patterns 302 are formed at predetermined intervals, and thus the warp of the substrate to be bonded can be suppressed, the adhesion between the bonded substrates can be ensured, and an SOI layer having a desired shape can be obtained.
    Type: Application
    Filed: March 26, 2008
    Publication date: November 20, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideto Ohnuma
  • Publication number: 20080251880
    Abstract: The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 16, 2008
    Inventors: Guy M. Cohen, Alexander Reznicek, Katherine L. Saenger, Min Yang
  • Publication number: 20080230781
    Abstract: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate. Thereby, a silicon nanocrystalline structure can be formed on a silicon substrate by using a process of producing silicon integrated circuits with achieving high luminous efficiency, and terminating reliably with oxygen or nitrogen on the surface thereof.
    Type: Application
    Filed: May 19, 2008
    Publication date: September 25, 2008
    Inventors: Yoichiro Numasawa, Yukinobu Murao
  • Publication number: 20080217647
    Abstract: A method of forming high quality nitride semiconductor layers on a patterned substrate and a light emitting diode having the same are disclosed. After forming a nucleation layer on the patterned substrate, a first 3D and 2D growth layers are formed thereon in this order by growing nitride semiconductor layers in 3D and 2D growth conditions. Then, a second 3D growth layer is formed on the first 2D growth layer by growing a nitride semiconductor layer in another 3D growth condition, and a second 2D growth layer is formed on the second 3D growth layer by growing a nitride semiconductor layer in another 2D growth condition. As such, the thickness of the 3D growth layer can be reduced by alternately forming the 3D and 2D growth layers, thereby preventing the 3D growth layer from having a rough surface and improving crystal quality of the final 2D growth layer.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 11, 2008
    Applicant: SEOUL OPTO DEVICE CO., LTD.
    Inventors: Joo Won Choi, Kyoung Hoon Kim, Eu Jin Hwang
  • Publication number: 20080173895
    Abstract: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the SiGe film. The buffer layer may be aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN). A GaN film is deposited overlying the buffer layer having a second TEC, greater than the first TEC. The SiGe film has a third TEC, with a value in between the first and second TECs. In one aspect, a graded SiGe film may be formed having a Ge content ratio in a range of about 0% to 50%, where the Ge content increases with the graded SiGe film thickness.
    Type: Application
    Filed: January 24, 2007
    Publication date: July 24, 2008
    Inventors: Jer-Shen Maa, Tingkai Li, Douglas J. Tweet, Gregory M. Stecker, Sheng Teng Hsu
  • Publication number: 20080138944
    Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed.
    Type: Application
    Filed: January 8, 2008
    Publication date: June 12, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shinji MAEKAWA, Hidekazu MIYAIRI
  • Publication number: 20080090388
    Abstract: A method for fabricating a semiconductor device, comprising: forming a semiconductor film on a substrate; and recrystallizing the semiconductor film using as a heat source flame of a gas burner that uses hydrogen and oxygen gas mixture as a fuel.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 17, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsuru Sato, Sumio Utsunomiya
  • Publication number: 20080067523
    Abstract: The invention relates to a new High Electron Mobility Transistor (HEMT), made essentially of layers of Group XIII element(s) nitride(s). Contrary to currently available transistors of this type, the transistor according to the invention is produced on a homosubstrate made of gallium-containing nitride, has no nucleation layer and its buffer layer is remarkably thinner than in known HEMTs. Preferably, at least the buffer layer, being a part of the transistor according to the present invention, is produced by epitaxial methods and the direction of growth of said layer in an epitaxial process is essentially perpendicular to the direction of growth of the substrate. The invention relates also to a method of manufacturing of High Electron Mobility Transistor (HEMT).
    Type: Application
    Filed: June 10, 2005
    Publication date: March 20, 2008
    Inventors: Robert Dwilinski, Roman Doradzinski, Jerzy Garczynski, Leszek Sierzputowski, Yasuo Kanbara
  • Publication number: 20080070387
    Abstract: A technique is provided which enables formation of nitride semiconductor layers with excellent flatness and excellent crystallinity on a gallium nitride substrate (GaN substrate), while improving the producibility of the semiconductor device using the GaN substrate. A gallium nitride substrate is prepared which has an upper surface having an off-angle of not less than 0.1° nor more than 1.0° in a <1-100> direction, with respect to a (0001) plane. Then, a plurality of nitride semiconductor layers including an n-type semiconductor layer are stacked on the upper surface of the gallium nitride substrate to form a semiconductor device such as a semiconductor laser.
    Type: Application
    Filed: November 16, 2007
    Publication date: March 20, 2008
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Akihito Ohno, Masayoshi Takemi, Nobuyuki Tomita
  • Publication number: 20080061293
    Abstract: A semiconductor device including, on at least one surface of a crystalline semiconductor substrate, at least one first amorphous semiconductor region doped with a first type of conductivity. The semiconductor substrate includes, on the same at least one surface, at least one second amorphous semiconductor region doped with a second type of conductivity, opposite the first type of conductivity. The first amorphous semiconductor region, insulated for the second amorphous semiconductor region by at least ore dielectric region in the contact with the semiconductor substrate, and the second amorphous semiconductor region form an interdigitated structure.
    Type: Application
    Filed: January 18, 2006
    Publication date: March 13, 2008
    Applicant: COMMISSARIAT A'ENERGIE ATOMIQUE
    Inventors: Pierre Ribeyron, Claude Jaussaud
  • Publication number: 20080035939
    Abstract: Electronic and opto-electronic devices having epitaxially-deposited III/V compounds on vicinal group IV substrates and method for making same. The devices include an AlAs nucleating layer on a Ge substrate. The group IV substrate contains a p-n junction whose change of characteristics during epitaxial growth of As-containing layers is minimized by the AlAs nucleating layer. The AlAs nucleating layer provides improved morphology of the devices and a means to control the position of a p-n junction near the surface of the group IV substrate through diffusion of As and/or P and near the bottom of the III/V structure through minimized diffusion of the group IV element.
    Type: Application
    Filed: July 11, 2007
    Publication date: February 14, 2008
    Applicant: CYRIUM TECHNOLOGIES INCORPORATED
    Inventors: Norbert PUETZ, Simon FAFARD, Bruno J. RIEL
  • Publication number: 20070262307
    Abstract: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate. Thereby, a silicon nanocrystalline structure can be formed on a silicon substrate by using a process of producing silicon integrated circuits with achieving high luminous efficiency, and terminating reliably with oxygen or nitrogen on the surface thereof.
    Type: Application
    Filed: July 16, 2007
    Publication date: November 15, 2007
    Inventors: Yoichiro Numasawa, Yukinobu Murao
  • Patent number: 7223661
    Abstract: The method includes forming an isolation film on a silicon substrate to define an active region; forming an antireflective film on an entire surface of the substrate containing the isolation film; forming a photosensitive film pattern on the antireflective film while exposing a portion of the isolation film or the active region adjacent to the isolation film; etching the antireflective film, the isolation film, and the substrate by using the photosensitive film pattern as an etching mask to recess the active region; performing a light etch treatment on a substrate resultant without removing the remaining photosensitive film pattern, so as to remove a damaged layer and a carbon pollutant formed on a surface of the recessed active region; and removing the remaining photosensitive film pattern and the antireflective film.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: May 29, 2007
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Jae Young Kim, Ki Won Nam