Abstract: The present invention is directed to a thick film conductive composition comprising: (a) electrically conductive silver powder; (b) zinc-containing additive; (c) glass frit wherein said glass frit is lead-free; dispersed in (d) organic medium. The present invention is further directed to an electrode formed from the composition above wherein said composition has been fired to remove the organic vehicle and sinter said glass particles. Still further, the invention is directed to a method of manufacturing a semiconductor device from a structural element composed of a semiconductor having a p-n junction and an insulating film formed on a main surface of the semiconductor comprising the steps of (a) applying onto said insulating film the thick film composition detailed above; and (b) firing said semiconductor, insulating film and thick film composition to form an electrode.

Abstract: A disclosed laminated structure includes a wettability-variable layer containing a wettability-variable material whose surface energy changes when energy is applied thereto and including at least a high-surface-energy area having high surface energy and a low-surface-energy area having low surface energy; and a conductive layer formed on the high-surface-energy area. The high-surface-energy area includes a first area and a second area extending from the first area and having a width smaller than that of the first area.

Abstract: A semiconductor chip according to the present invention includes a semiconductor substrate, a bump of a metal projecting from a surface of the semiconductor substrate, and an alloy film covering the entire surface of the bump, the alloy film being composed of an alloy of the metal of the bump and a second metal.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent.

Abstract: The present invention provides a method of forming a via hole (9), or a via (7), from a lower side (5) of a substrate (3) for electronic devices towards an upper side (4) of a substrate (3) at least partly through the substrate (3). The method comprises the steps of: etching a first lengthwise portion (1 1) of the via hole (9) and etching a second lengthwise portion (12) of the via hole (9); whereby the first lengthwise portion (11) and the second lengthwise portion (12) substantially form the via hole (9) and a constriction (23) is formed in the via hole (9). The constriction (23) defines an aperture (24) of the via hole (9) and the method further comprises the step of opening the via hole (9) by etching, with the constriction (23) functioning as an etch mask. A via is formed by at least partly filling the via hole with conductive material. A substrate for electronic devices comprising a via is also provided.

Abstract: Disclosed is a semiconductor device comprising a p-type SiC semiconductor and an ohmic electrode having an Ni/Al laminated structure provided on the p-type SiC semiconductor. The semiconductor device simultaneously has improved contact resistance and surface roughness in the ohmic electrode. The semiconductor device comprises an ohmic electrode (18) comprising a nickel (Ni) layer (21), a titanium (Ti) layer (22), and an aluminum (Al) layer (23) stacked in that order on a p-type silicon carbide semiconductor region (13). The ohmic electrode (18) comprises 14 to 47 atomic % of a nickel element, 5 to 12 atomic % of titanium element, and 35 to 74 atomic % of an aluminum element, provided that the atomic ratio of the nickel element to the titanium element is 1 to 11.

Abstract: The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.

Abstract: A gallium arsenide (GaAs) integrated circuit device is provided. The GaAs circuit device has a GaAs substrate with a copper contact layer for making electrical ground contact with a pad of a target device. Although copper is known to detrimentally affect GaAs devices, the copper contact layer is isolated from the GaAs substrate using a barrier layer. The barrier layer may be, for example, a layer of nickel vanadium (NiV). This nickel vanadium (NiV) barrier protects the gallium arsenide substrate from the diffusion effects of the copper contact layer. An organic solder preservative may coat the exposed copper to reduce oxidation effects. In some cases, a gold or copper seed layer may be deposited on the GaAs substrate prior to depositing the copper contact layer.

Abstract: Described is a method of forming a solder deposit on a substrate comprising the following steps i) provide a substrate including a surface bearing electrical circuitry that includes at least one contact area, ii) form a solder mask layer that is placed on the substrate surface and patterned to expose the at least one contact area, iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface, iv) electroplate a solder deposit layer containing a tin or tin alloy onto the conductive layer and v) etch away an amount of the solder deposit layer containing tin or tin alloy sufficient to remove the solder deposit layer from the solder mask layer area leaving a solder material layer on the at least one contact area.

Abstract: A method of manufacturing a semiconductor device in which a stress can be effectively applied from a semiconductor layer having a different lattice constant from a semiconductor substrate to a channel part, whereby carrier mobility can be improved and higher functionality can be achieved.

Abstract: A semiconductor device includes at least two conductive pads, one of the conductive pads being formed above another of the at least two conductive pads, and a redistribution layer extending from at least one of the conductive pads. The semiconductor device also includes a bump structure formed over the conductive pads and electrically coupled to the conductive pads.

Abstract: A method for fabricating a light emitting device includes forming a trench in a first surface on a first side of a substrate. The trench comprises a first sloped surface not parallel to the first surface, wherein the substrate has a second side opposite to the first side of the substrate. The method also includes forming light emission layers over the first trench surface and the first surface, wherein the light emission layer is configured to emit light and removing at least a portion of the substrate from the second side of the substrate to form a protrusion on the second side of the substrate to allow the light emission layer to emit light out of the protrusion on the second side of the substrate.

Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.

Abstract: Light emitting diode (LED) dies are fabricated by forming LED layers including a first conductivity type layer, a light-emitting layer, and a second conductivity type layer. Trenches are formed in the LED layers that reach at least partially into the first conductivity type layer. Electrically insulation regions are formed in or next to at least portions of the first conductivity type layer along the die edges. A first conductivity bond pad layer is formed to electrically contact the first conductivity type layer and extend over the singulation streets between the LED dies. A second conductivity bond pad layer is formed to electrically contact the second conductivity type layer, and extend over the singulation streets between the LED dies and the electrically insulated portions of the first conductivity type layer. The LED dies are mounted to submounts and the LED dies are singulated along the singulation streets between the LED dies.

Abstract: A method of manufacturing a semiconductor device on a substrate (10) is disclosed. The method comprises providing the substrate (10) including a body region (12) protruding from said substrate (10), the body region (12) being covered by a gate electrode material (16, 56) forming a first gate region (18) on a first side of the body region (12) and a second gate region (20) on a second side of the body region (12), the gate material (16, 56) being separated from the body region (12) by a dielectric layer (14); and introducing a dopant (22, 58) of a first conductivity type into the gate electrode material (16, 56) such that the first gate region (18, 20) is exposed to the dopant while the second gate region (20, 18) is substantially sheltered from the dopant by the protruding body region (12). This allows for versatile tuning of the work function of a single gate to be formed. An integrated circuit comprising such a semiconductor device is also disclosed.

Abstract: According to a method of manufacturing a MONOS nonvolatile semiconductor memory device, a tunnel insulating film, a charge storage layer, a block insulating film containing a metal oxide and a control gate electrode are stacked on a semiconductor substrate. Heat treatment is carried out in an atmosphere containing an oxidizing gas after the tunnel insulating film, the charge storage layer and the block insulating film are stacked on the semiconductor substrate. Thereafter, the control gate electrode is formed on the block insulating film.

Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32, which contacts with the surface of a p-type semiconductor region in the semiconductor multilayer structure 20.

Abstract: The present invention is directed to a thick film conductive composition comprising: (a) electrically conductive silver powder; (b) Zn-containing additive wherein the particle size of said zinc-containing additive is in the range of 7 nanometers to less than 100 nanometers; (c) glass frit wherein said glass frit has a softening point in the range of 300 to 600° C.; dispersed in (d) organic medium. The present invention is further directed to a semiconductor device and a method of manufacturing a semiconductor device from a structural element composed of a semiconductor having a p-n junction and an insulating film formed on a main surface of the semiconductor comprising the steps of (a) applying onto said insulating film the thick film composition as describe above; and (b) firing said semiconductor, insulating film and thick film composition to form an electrode.

Abstract: In one embodiment, a semiconductor device may includes a through via disposed within a substrate with a diffusion barrier layer disposed over the through via and the substrate. An insulation layer may be disposed over the diffusion barrier layer, a metal interconnection layer disposed within the insulation layer over at least a portion of the via contact, and a via contact disposed between the metal interconnection layer and the through via within the insulation layer. The via contact may have a cross-sectional area larger than a cross-sectional area of the through via so that the through via and the diffusion barrier layer do not contact each other.

Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells.

Abstract: Provided are methods and apparatuses for manufacturing a multilayer metal thin film without additional heat treatment processes. The method of manufacturing a multilayer metal thin film including steps of: (a) forming a first metal layer on a substrate by flowing a first metal precursor into a first reaction container; and (b) forming a second metal layer on the first metal layer by flowing a second metal precursor into a second reaction container, wherein the step (b) is performed in a range of a heat treatment temperature of the first metal layer so that the second metal layer is formed as the first metal layer is heat-treated.

Abstract: The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf3N4) and hafnium oxide (HfO2) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using precursor chemicals, followed by depositing hafnium nitride using precursor chemicals, and repeating to form the laminate structure. Alternatively, the hafnium nitride may be deposited first followed by the hafnium nitride. Such a dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric in a DRAM, or a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because of the reduced leakage current when compared to an electrically equivalent thickness of silicon dioxide.

Abstract: A compound field effect transistor having multiple pinch-off voltages, comprising first and second field effect transistors, each field effect transistor comprising a semiconductor layer, the semiconductor layer having an electrically conducting layer therein. An ohmic contact layer on the semiconductor layer, a source and a drain on the ohmic contact layer, at least one gate on the semiconductor layer between source and drain, at least one gate of the first transistor and one gate of the second transistor being matched gates, each gate having the same effective thickness of electrically conducting layer beneath it, but the gates having different gate lengths.

Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.

Abstract: This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <300° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least one disilane derivative compound that is fully substituted with alkylamino and/or dialkylamino functional groups.

Abstract: A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.

Abstract: A method for manufacturing a semiconductor device according to the present invention includes the following step: a step (S10) of forming a GaN-based semiconductor layer, a step (S20) of forming an Al film on the GaN-based semiconductor layer, a step (S30, S40) of forming a mask layer composed of a material having a lower etching rate than that of the material constituting the Al film, a step (S50) of partially removing the Al film and the GaN-based semiconductor layer using the mask layer as a mask to form a ridge portion, a step (S60) of retracting the positions of the side walls at the ends of the Al film from the positions of the side walls of the mask layer, a step (S70) of forming a protection film composed of a material having a lower etching rate than that of the material constituting the Al film on the side surfaces of the ridge portion and on the upper surface of the mask layer, and a step (S80) of removing the Al film to remove the mask layer and the protection film formed on the upper surface of t

Abstract: Provided are a cleaning liquid for lithography that exhibits excellent corrosion suppression performance in relation to tungsten, and excellent removal performance in relation to a resist film or the like, and a method for forming a wiring using the cleaning liquid for lithography. The cleaning liquid for lithography according to the present invention includes a quaternary ammonium hydroxide, a water-soluble organic solvent, water, an inorganic salt and an anti-corrosion agent represented by a general formula (1) below. In the general formula (1), R1 represents an alkyl group or an aryl group having 1-17 carbon atoms, and R2 represents an alkyl group having 1-13 carbon atoms.

Abstract: A method of manufacturing a semiconductor device is disclosed, wherein a plating layer is formed on a first surface side of a semiconductor substrate stably and at a low cost, while preventing the plating liquid from being contaminated and avoiding deposition of uneven plating layer on a second surface side. An electrode is formed on the first surface of the semiconductor substrate, and another electrode is formed on the second surface. A curing resin is applied on the electrode on the second surface and a film is stuck on the curing resin, and the curing resin is then cured. After that, a plating process is conducted on the first surface. The film and the curing resin are then peeled off.

Abstract: A method of fabricating a lower bottom electrode for a memory element and a semiconductor structure having the same includes forming a dielectric layer over a semiconductor substrate having a plurality of conductive contacts formed therein to be connected to access circuitry, forming a dielectric cap layer over exposed portions of the dielectric layer and the conductive contacts, depositing a planarizing material over the dielectric cap layer, etching a via to an upper surface of each conductive contact, removing the planarizing material, depositing electrode material over the dielectric cap layer and within the vias, the electrode material contacting an upper surface of each conductive contact, and planarizing the electrode material to form a lower bottom electrode over each conductive contact.

Abstract: A semiconductor device comprises a semiconductor construct including a semiconductor substrate, and an external connection electrode provided to protrude on the surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including the side surface of the semiconductor substrate.

Abstract: A solar cell including a high electrical resistivity transparent layer formed on a CdS buffer layer is provided. The high electrical resistivity transparent layer includes an intrinsic oxide film formed on the buffer layer and an intermediate oxide film formed on the intrinsic oxide film. The intrinsic oxide film includes undoped zinc oxide and has a thickness range of 10 to 40 nm. The intermediate oxide film includes semi-intrinsic zinc oxide doped with aluminum and has a thickness range of 50-150 nm. The intermediate oxide film has an aluminum concentration of less than 1000 ppm.

Abstract: A transparent conductive film for lamination on a substrate and comprising an ITO film and an FTO film, wherein a part or all of the crystal structure of a surface of the FTO film is orthorhombic, and a transparent conductive film for lamination on a substrate and comprising an ITO film and an FTO film, wherein the thickness of the FTO film is within a range from 5 nm to 20 nm and the FTO film is a continuous film. A method of producing the transparent conductive films includes depositing the ITO film on a substrate using a pyrosol process, and subsequently depositing the FTO film continuously on top of the ITO film.

Abstract: Methods of forming a metal silicate layer and methods of fabricating a semiconductor device including the metal silicate layer are provided, the methods of forming the metal silicate layer include forming the metal silicate using a plurality of silicon precursors. The silicon precursors are homoleptic silicon precursors in which ligands bound to silicon have the same molecular structure.

Abstract: The invention relates to a method for treating a metal oxide layer deposited on a substrate. The method comprises the step of applying a substantially atmospheric plasma process at a relatively low temperature. Preferably, the temperature during the plasma process is lower than approximately 180° C. Further, the atmospheric plasma process can be applied in a plasma chamber comprising H2 gas and He gas.

Abstract: A sub assembly is disclosed for use in fabrication of photo-electrochemical devices including: a first layer which includes a semiconductor material; a second layer which is electrically conductive; and wherein the second layer supports the first layer. Methods of producing the sub assembly are also disclosed.

Abstract: A method of manufacturing a semiconductor element including a semiconductor substrate, a conductive post portion provided on the semiconductor substrate to protrude therefrom, and a solder layer provided on the conductive post portion, includes forming on the semiconductor substrate the conductive post portion having a distal end surface curved in a substantially arc shape by electrolytic plating, forming an intermediate solder layer on the distal end surface of the conductive post portion, and reflowing the intermediate solder layer to form the solder layer which has a thickest portion at a top of the distal end surface of the conductive post portion.

Abstract: Disclosed is a method of manufacturing an organic light emitting device, an organic light emitting device manufactured by using the method, and an electronic device including the organic light emitting device. The method includes (a) forming an insulating layer on a lower electrode, (b) etching the insulating layer to form an opening ranging from an upper surface of the insulating layer to the lower electrode so that an overhang structure having a lowermost circumference that is larger than an uppermost circumference is formed, (c) forming a conductive layer on an upper surface of the lower electrode in the opening and a surface of the insulating layer other than the overhang structure, (d) forming an organic material layer on the conductive layer formed on the upper surface of the lower electrode in the opening, and (e) forming an upper electrode on an upper surface of the conductive layer disposed on the upper surface of the insulating layer and an upper surface of the organic material layer.

Abstract: A cap layer for a metal feature such as a copper interconnect on a semiconductor wafer is formed by immersion plating a more noble metal (e.g. Pd) onto the copper interconnect and breaking up, preferably by mechanical abrasion, loose nodules of the noble metal that form on the copper interconnect surface. The mechanical abrasion removes plated noble metal which is only loosely attached to the copper surface, and then continued exposure of the copper surface to immersion plating chemicals leads to plating at new sites on the surface until a continuous, well-bonded noble metal layer has formed. The method can be implemented conveniently by supplying immersion plating chemicals to the surface of a wafer undergoing CMP or undergoing scrubbing in a wafer-scrubber apparatus.

Abstract: Methods of preparing photovoltaic modules, as well as related components, systems, and devices, are disclosed.

Abstract: A semiconductor device includes: a first insulation film formed over a semiconductor substrate; and a plurality of first interconnects selectively formed in the first insulation film. A plurality of gaps are formed in part of the first insulation film located between adjacent ones of the first interconnects so that each of the gaps has a cylindrical shape extending vertically to a principal surface of the semiconductor substrate. A cap film is formed of metal or a material containing metal in upper part of each of the first interconnects.

Abstract: A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer.

Abstract: A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.

Abstract: A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas.

Abstract: The semiconductor device comprises a word line and a bit line. The word line comprises a gate electrode and a first metal interconnect. The first metal interconnect has contact with the gate electrode and extends into a region upper than a first impurity-diffused region in a first direction. The bit line comprises a connecting part and a second metal interconnect. The connecting part is formed so as to have contact with at least part of the side surface of the first impurity-diffused region. The second metal interconnect has contact with the connecting part and extends into a region lower than the semiconductor region in a second direction orthogonal to the first direction.

Abstract: A semiconductor device includes a substrate, at least one via hole provided on the substrate, a through silicon via provided in the at least one via hole, and an interface chip that is electrically connected to the core chips through the through silicon via. The via hole includes a bowing shaped portion in which a diameter of a center portion is larger than diameters of both edges.

Abstract: There are provided: a thin film transistor substrate provided with an amorphous transparent conductive film in which residue due to etching hardly occurs; a liquid crystal display device which utilizes the thin film transistor substrate; and a method for manufacturing a thin film transistor substrate in which the thin film transistor substrate can be efficiently obtained. Provided is a thin film transistor substrate in which there is provided a transparent substrate, on the transparent substrate there are formed a gate electrode, a semiconductor layer, a source electrode, a drain electrode, a transparent pixel electrode, and a transparent electrode, and the transparent pixel electrode is formed with a transparent conductive film and is electrically connected to the source electrode or the drain electrode, wherein the transparent conductive film which constitutes the transparent pixel electrode is composed of an indium oxide containing gallium.

Abstract: An exemplary method for fabricating a damascene interconnect structure includes the following. First, providing a substrate. Second, depositing a multilayer dielectric film on the substrate. Third, forming a patterned photoresist on the multilayer dielectric film. Fourth, etching the multilayer dielectric film to form a plurality of trenches, a portion of each of the trenches having an enlarged width at each of sidewalls thereof. Fifth, filling the trenches with conductive metal to form conductive lines such that air is trapped in extremities of the enlarged width portions of the trenches.

Abstract: A method for producing the LED substrate has steps of: p providing a conductive metallic board, forming multiple grooves in a top of the conductive metallic board; protecting the conductive metallic board from corrosion, forming an etched substrate with circuits and wires for plating on the conductive metallic board, electroless plating the etched substrate to form an electroless plated substrate, plating metal on the electroless plated substrate, and coating solder mask to obtain the LED substrate. Because LED chips are mounted on the surfaces of the metal layer without insulating adhesive below, heat from LED chips can be dissipated efficiently. The LED substrate of the present invention can be soldered directly onto a dissipation module to further enhance dissipation efficiency.

Abstract: A phase change memory device having a heater that exhibits a temperature dependent resistivity which provides a way of reducing a reset current is presented. The phase change memory device includes a phase change pattern and a heating electrode contacted with the phase change pattern. The heating electrode includes a smart heating electrode such that the smart heating layer is formed of a conduction material that exhibits an increase in resistance as a function of an increase in temperature, i.e., a positive temperature dependent resistivity.