Abstract: A semiconductor chip such as an MMIC is provided. The semiconductor chip has: a Si semiconductor as a substrate; and a low-loss transmission line, and can be easily connected to a circuit board on which the semiconductor chip is to be mounted and can ensure a stable GND potential. The semiconductor chip is a flip-chip semiconductor chip, and includes: a Si substrate; an integrated circuit manufactured on a main surface of the substrate; a dielectric film formed above the integrated circuit; and a conductor film for grounding formed on an upper surface of the dielectric film. The integrated circuit includes a wiring layer including a signal line which transmits signals for the integrated circuit. The signal line, the dielectric film, and the conductor film constitute a microstrip line.

Abstract: A chip bump structure is formed on a substrate. The substrate includes at least one contact pad and a dielectric layer. The dielectric layer has at least one opening. The at least one opening exposes the at least one contact pad. The chip bump structure includes at least one elastic bump, at least one first metal layer, at least one second metal layer, and at least one solder ball. The at least one elastic bump covers a central portion of the at least one contact pad. The at least one first metal layer covers the at least one elastic bump. The at least one first metal layer has a portion of the at least one contact pad. The portion of the at least one contact pad is not overlaid by the at least one elastic bump. The at least one second metal layer is formed on a portion of the at least one first metal layer. The portion of the at least one first metal layer is located on the top of the at least one elastic bump. The at least one solder ball is formed on the at least one second metal layer.

Abstract: A semiconductor device with improved quality and reliability is provided. In a UBM formed over an electrode pad located over a semiconductor substrate, the edge (end) of an Au film as an upper layer is located inside or in the same position as the edge (end) of a TiW film as a lower layer, which can suppress the formation of a suspended part in the Au film. This arrangement can prevent the occurrence of electrical short circuit between the adjacent pads due to the suspended part and the adhesion of the suspended part as foreign matter to the semiconductor substrate, thus improving the quality and reliability of the semiconductor device (semiconductor chip).

Abstract: The invention provides an ohmic electrode of a p-type SiC semiconductor element, which includes an ohmic electrode layer that is made of Ti3SiC2, and that is formed directly on a surface of a p-type SiC semiconductor. The invention also provides a method of forming an ohmic electrode of a p-type SiC semiconductor element. The ohmic electrode includes an ohmic electrode layer that is made of Ti3SiC2, and that is formed directly on a surface of a p-type SiC semiconductor. The method includes forming a ternary mixed film that includes Ti, Si, and C in a manner such that an atomic composition ratio, Ti:Si:C is 3:1:2, on a surface of a p-type SiC semiconductor to produce a laminated film; and annealing the produced laminated film under vacuum or under an inert gas atmosphere.

Abstract: The invention provides a method for forming a contact hole, comprising: forming a gate, a sidewall spacer, a sacrificial sidewall spacer, a source region and a drain region on a substrate, wherein the sidewall spacer is formed around the gate, the sacrificial sidewall spacer is formed over the sidewall spacer, and the source region and the drain region are formed within the substrate and on respective sides of the gate; forming an interlayer dielectric layer, with the gate, the sidewall spacer and the sacrificial sidewall spacer being exposed; removing the sacrificial sidewall spacer to form a contact space, a material that the sacrificial sidewall spacer is made of being different from any of materials that the gate, the sidewall spacer and the interlayer dielectric layer are made of; forming a conducting layer to fill the contact space; and cutting off the conducting layer, to form at least two conductors connected to the source region and the drain region respectively.

Abstract: A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract: A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

Abstract: An IC chip and an IC chip manufacturing method thereof are provided. The IC chip has a chip body and at least one bump. The chip body has at least one conducting area on its surface. The bump is formed on the conducting area of the chip body. The bump includes a plurality of protrusions and at least one conducting material. The protrusions protrude out of the conducting area and are spaced apart from each other. The conducting material covers the protrusions and electrically connects the conducting area. The method includes: (A) providing a chip body having a conducting area on its surface; (B) forming a plurality of protrusions on the chip body, wherein the protrusions protrude out of the conducting area and are spaced apart from each other; and (C) forming at least one conducting material, wherein the conducting material covers the protrusions and electrically connects the conducting area.

Abstract: A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer and the second conductive layer. Further, the first conductive layer includes one or more selected from carbon, chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. And the second conductive layer includes one or more selected from chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel, or nitride of these materials.

Abstract: Methods are generally provided for forming a conductive oxide layer on a substrate. In one particular embodiment, the method can include sputtering a transparent conductive oxide layer on a substrate at a sputtering temperature from about 50° C. to about 250° C., and annealing the transparent conductive oxide layer at an anneal temperature of about 450° C. to about 650° C. Methods are also generally provided for manufacturing a cadmium telluride based thin film photovoltaic device.

Abstract: An electronic component includes a plurality of first electrode pads arranged on a first substrate, a plurality of second electrode pads arranged at positions corresponding to the first electrode pads on a second substrate and a plurality of solder bumps which join together the first electrode pads and the second electrode pads. Here, the first substrate is located over the second substrate so that the first electrode pads and the second electrode pads are at positions which are shifted from opposite positions where the first electrode pads opposite to the second electrode pads, and at least a part of the solder bumps are solidified into hourglass-shaped.

Abstract: The present disclosure provides methods for forming semiconductor devices with laser-etched vias and apparatus including the same. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside and a backside, and providing a layer above the frontside of the substrate, the layer having a different composition from the substrate. The method further includes controlling a laser power and a laser pulse number to laser etch an opening through the layer and at least a portion of the frontside of the substrate, filling the opening with a conductive material to form a via, removing a portion of the backside of the substrate to expose the via, and electrically coupling a first element to a second element with the via. A semiconductor device fabricated by such a method is also disclosed.

Abstract: A semiconductor device comprises an electrical contact designed to reduce a contact resistance. The electrical contact has a size that varies according to a length of a region where the contact is to be formed.

Abstract: The present disclosure fabricates an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory device. The memory device is stacked with memory layers having a low aspect ratio. The memory device can be easily fabricated with only two extra masks for saving cost. The present disclosure uses a general method for mass-producing TFT and is thus fit for fabricating NAND-type or NOR-type flash memory to be used as embedded memory in a system-on-chip.

Abstract: Methods are generally provided for forming a conductive oxide layer on a substrate. In one particular embodiment, the method can include sputtering a transparent conductive oxide layer (e.g., including cadmium stannate) on a substrate from a target in a sputtering atmosphere comprising cadmium. The transparent conductive oxide layer can be sputtered at a sputtering temperature greater of about 100° C. to about 600° C. Methods are also generally provided for manufacturing a cadmium telluride based thin film photovoltaic device.

Abstract: Methods are generally provided for forming a conductive oxide layer on a substrate. In one particular embodiment, the method can include sputtering a transparent conductive oxide layer on a substrate from a target (e.g., including cadmium stannate) in a sputtering atmosphere comprising cadmium. The transparent conductive oxide layer can be sputtered at a sputtering temperature of about 100° C. to about 600° C. Methods are also generally provided for manufacturing a cadmium telluride based thin film photovoltaic device.

Abstract: An interconnect structure for integrated circuits incorporates manganese silicate and manganese silicon nitride layers that completely surrounds copper wires in integrated circuits and methods for making the same are provided. The manganese silicate forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The manganese silicate and manganese silicon nitride also promote strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use. The strong adhesion at the copper-manganese silicate and manganese silicon nitride interfaces also protect against failure by electromigration of the copper during use of the devices. The manganese-containing sheath also protects the copper from corrosion by oxygen or water from its surroundings.

Abstract: A method of forming low dielectric contrast structures by imprinting a silsesquioxane based polymerizable composition. The imprinting composition including: one or more polyhedral silsesquioxane oligomers each having one or more polymerizable groups, wherein each of the one or more polymerizable group is bound to a different silicon atom of the one or more polyhedral silsesquioxane oligomers; and one or more polymerizable diluents, the diluents constituting at least 50% by weight of the composition.

Abstract: The present invention comprises a first substrate with a die formed on a die metal pad, a first and a second wiring circuits formed on the surfaces of the first substrate. A second substrate has a die opening window for receiving the die, a third wiring circuit is formed on top surface of the second substrate and a fourth wiring circuit on bottom surface of the second substrate. An adhesive material is filled into the gap between back side of the die and top surface of the first substrate and between the side wall of the die and the side wall of the die receiving through hole and the bottom side of the second substrate. During the formation, laser is introduced to cut the backside of the first substrate and an opening hole is formed in the first substrate to expose a part of the backside of the Au or Au/Ag metal layer of chip/die.

Abstract: The present invention discloses a display device and a manufacturing method thereof by which a manufacturing process can be simplified. Further, the present invention discloses technique for manufacturing a pattern such as a wiring into a desired shape with good controllability. A method for forming a pattern for constituting the display device according to the present invention comprises the steps of forming a first region and a second region; discharging a composition containing a pattern formation material to a region across the second region and the first region; and flowing a part of the composition discharged to the first region into the second region; wherein wettability with respect to the composition of the first region is lower than that of the second composition.

Abstract: A semiconductor device according to one embodiment includes: a substrate having an element region where a semiconductor element is formed; a via hole formed in a portion of the substrate adjacent to the element region; a conducting portion provided in the via hole via an insulating layer; and a buffer layer provided between the substrate and the insulating layer, wherein the buffer layer is made of a material in which a difference in thermal expansion coefficient between the substrate and the buffer layer is smaller than that between the substrate and the insulating layer.

Abstract: Provided is a method for manufacturing a silicon carbide semiconductor device which is capable of obtaining the silicon carbide semiconductor device having a high forward current and a low reverse leakage current by a simple method. The method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a film made of a first electrode material on one surface of a silicon carbide substrate, and forming an ohmic electrode by performing heat treatment at a temperature range of 930 to 950° C.; and forming a film made of a second electrode material on the other surface of the silicon carbide substrate, and forming a Schottky electrode by performing heat treatment.

Abstract: A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.

Abstract: According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate.

Abstract: A method for fabricating a semiconductor device includes: (a) forming an interlayer insulating film on a substrate; (b) forming an interconnect in the interlayer insulating film; (c) applying an organic solution to an upper surface of the interconnect and an upper surface of the interlayer insulating film; (d) after (c), applying a silylating solution to the upper surface of the interconnect and the upper surface of the interlayer insulating film; (e) after (d), heating the substrate; and (f) forming a first liner insulating film at least on the upper surface of the interconnect.

Abstract: It is an object of the present invention to provide a semiconductor device, in particular, a light emitting element which can be easily manufactured with a wet method. One feature of the invention is a light emitting device including a transistor and a light emitting element. In the light emitting element, an organic layer, a light emitting layer, and a second electrode are sequentially formed over a first electrode, and the transistor is electrically connected to the light emitting element through a wiring. Here, the wiring contains aluminum, carbon, and titanium. The organic layer is formed by a wet method. The first electrode which is in contact with the organic layer is formed from indium tin oxide containing titanium oxide.

Abstract: A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.

Abstract: A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.

Abstract: Metal pastes comprising (a) at least one electrically conductive metal powder selected from the group consisting of silver, copper and nickel, (b) at least one lead-containing glass frit with a softening point temperature in the range of 571 to 636° C. and containing 53 to 57 wt.-% of PbO, 25 to 29 wt.-% of SiO2, 2 to 6 wt.-% of Al2O3 and 6 to 9 wt.-% of B2O3 and (c) an organic vehicle.

Abstract: This invention relates to thick-film pastes and processes for using such pastes to make solar cell contacts and other circuit devices. In particular, the thick-film pastes comprise a lead-tellurium-oxide frit component, an organic vehicle, and a conductive metal component comprising a silver component and a nickel component.

Abstract: A method for forming through vias connecting the front surface to the rear surface of a semiconductor substrate, including the steps of: forming openings in the substrate, thermally oxidizing walls of the openings, filling the openings with a sacrificial material, forming electronic components in the substrate, etching the sacrificial material, filling the openings with a metal, and etching the rear surface of the substrate all the way to the bottom of the openings.

Abstract: An electrode for silicon carbide includes a silicide region which is provided in contact with a surface of a silicon carbide (SiC) layer and a carbide region which is provided on the silicide region. The silicide region contains a silicide of a first metal in more amount than a carbide of a second metal whose free energy of carbide formation is less than that of silicon (Si). The carbide region contains the carbide of the second metal in more amount than the silicide of the first metal.

Abstract: A semiconductor device includes a semiconductor chip having a wire and a passivation film formed on the outermost surface with an opening partially exposing the wire. A resin layer is stacked on the semiconductor chip and provided with a through-hole in a position opposed to a portion of the wire facing the opening. A pad is formed on a peripheral portion of the through-hole in the resin layer and in the through-hole so that an external connection terminal is arranged on the surface thereof. The peripheral portion of the resin layer is formed more thickly than the remaining portion of the resin layer other than the peripheral portion.

Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Abstract: A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method includes attaching a carrier to a substrate including a via to form a pressurized sealed cavity between the carrier and the substrate. The method may also include thinning the substrate attached to the carrier and forming a redistribution layer on the thinned substrate in electrical communication with the via, the redistribution layer including a conductive layer formed through atmospheric pressure chemical vapor deposition. Additional methods, devices, and systems are devices, systems, and methods are also disclosed.

Abstract: A method includes forming a first dielectric layer over a substrate; forming nanoclusters over the first dielectric layer; forming a second dielectric layer over the nanoclusters; annealing the second dielectric layer using nitrous oxide; and after the annealing the second dielectric layer, forming a gate electrode over the second dielectric layer.

Abstract: A semiconductor light-emitting device according to the embodiment includes a substrate, a compound semiconductor layer, a metal electrode layer provided with particular openings, a light-extraction layer, and a counter electrode. The light-extraction layer has a thickness of 20 to 120 nm and covers at least partly the metal part of the metal electrode layer; or otherwise the light-extraction layer has a rugged structure and covers at least partly the metal part of the metal electrode layer. The rugged structure has projections so arranged that their summits are positioned at intervals of 100 to 600 nm, and the heights of the summits from the surface of the metal electrode layer are 200 to 700 nm.

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Abstract: Unintended full siliciding of a polysilicon gate electrode is prevented. The invention provides a method of manufacturing a semiconductor device, the method including: forming a stack structure by stacking a gate insulating film and a silicon layer in this order on a substrate; forming an offset spacer along the side surfaces of the stack structure, the offset spacer including a SiN film; cleaning an exposed region of an upper surface of the silicon layer with a chemical solution after the forming the offset spacer; forming a metal film after the cleaning, the metal film covering at least the exposed region; and performing siliciding through a heating process after the forming the metal film. The SiN film of the offset spacer is a SiN film formed by ALD at 450° C. equal to or higher, or a SiN film having a tensile/compressive stress of 1 Gpa or higher. The chemical solution is DHF having a ratio by weight of 1/100 or higher in HF/H2O or buffered hydrofluoric acid.

Abstract: Methods of filling deep trenches in substrates are described. A method includes providing a substrate with a deep trench formed therein. The method also includes forming a dielectric layer conformal with the substrate and the deep trench. The method also includes, with the entire portion of the dielectric layer conformal with the deep trench exposed, removing at least a portion, but not all, of the dielectric layer at the top of the deep trench with a relatively low bias plasma etch process.

Abstract: A method for manufacturing semiconductor device includes forming an interlayer dielectric layer including a contact plug defined therein to electrically couple a semiconductor substrate on which a cell region and a dummy region are defined. A sacrificial layer is formed over the interlayer dielectric layer. An etch stop pattern is formed over the sacrificial layer, the etch stop pattern being vertically aligned to the dummy region. A storage electrode region through the sacrificial layer is defined to expose a first storage electrode contact of the cell region, the second storage electrode contact of the dummy region remaining covered by the sacrificial layer. A conductive layer is deposited within the storage electrode region to form a storage electrode contacting the first storage electrode contact of the cell region.

Abstract: A manufacturing method of a bump structure having a reinforcement member is disclosed. First, a substrate including pads and a passivation layer is provided. The passivation layer has first openings, and each first opening exposes a portion of the corresponding pad respectively. Next, an under ball metal (UBM) material layer is formed on the substrate to cover the passivation layer and the pads exposed by the passivation layer. Bumps are formed on the UBM material layer and the lower surface of each bump is smaller than that of the opening. Each reinforcement member formed on the UBM material layer around each bump contacts with each bump, and the material of the reinforcement member is a polymer. The UBM material layer is patterned to form UBM layers and the lower surface of each UBM layer is larger than that of each corresponding opening. Hence, the bump has a planar upper surface.

Abstract: The present invention provides a metal nitride film that realizes an intended effective work function (for example, a high effective work function) and has EOT exhibiting no change or a reduced change, a semiconductor device using the metal nitride film, and a manufacturing method of the semiconductor device. The metal nitride film according to an embodiment of the present invention contains Ti, Al and N, wherein the metal nitride film has such molar fractions of Ti, Al and N as (N/(Ti+Al+N)) of 0.53 or more, (Ti/(Ti+Al+N)) of 0.32 or less, and (Al/(Ti+Al+N)) of 0.15 or less.

Abstract: A method for fabricating a semiconductor device includes forming an interlayer dielectric film on a semiconductor substrate including a pattern region and a dummy region, forming a photoresist pattern on the interlayer dielectric film such that the pattern region and the dummy region are partially exposed, etching the interlayer dielectric film exposed through the photoresist pattern as an etching mask to form a contact hole and a dummy contact hole, filling the contact hole and the dummy contact hole with a conductive material to form a contact plug and a dummy plug, depositing a semiconductor layer on the contact plug and the dummy plug, and subjecting the semiconductor layer to patterning to form a semiconductor layer pattern and a dummy pattern.

Abstract: A biocompatible electrode is manufactured by depositing filling metal 36 and etching back the filling metal to the surface of the surrounding insulator 30. Then, a further etch forms a recess 38 at the top of the via 32. An electrode metal 40 is then deposited and etched back to fill the recess 38 and form biocompatible electrode 42. In this way, a planar biocompatible electrode is achieved. The step of etching to form the recess may be carried out in the same CMP tool as is used to etch back the filling metal 36. A hydrogen peroxide etch may be used.

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.