Abstract: A method for manufacturing a semiconductor device including covering a portion of at least one semiconductor device with a foil, including covering at least one target region of the semiconductor device, and illuminating the foil with a laser to singulate from the foil a portion covering the at least one target region of the at least one semiconductor device.

Abstract: Gas mixtures which comprise acids like HF, HCl or HBr and other constituents, especially gas mixtures which comprise or consist of carboxylic acid fluorides, C(O)F2 or phosphorous pentafluoride and HCl and optionally HF, can be separated by ionic liquids. The process is performed reversibly. Ionic liquids are applied the anion of which corresponds to a stronger acid than the acid to be removed. Highly purified products, for example, highly purified carbonyl fluoride can be obtained.

Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.

Abstract: A method for patterning an insulation layer and selectively removing a capping layer overlying the insulation layer is described. The method utilizes a dry non-plasma removal process. The dry non-plasma removal process may include a self-limiting process.

Abstract: A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor wafer through orifices (100) containing in the ring (70). Water and/or nitrogen can be applied to the surface of the semiconductor wafer through orifices (110) contained in the spokes (90).

Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Abstract: A combination of a dry oxidizing, wet etching, and wet cleaning processes are used to remove particle defects from a wafer after ion implantation, as part of a wafer bonding process to fabricate a SOI wafer. The particle defects on the topside and the backside of the wafer are oxidized, in a dry strip chamber, with an energized gas. In a wet clean chamber, the backside of the wafer is treated with an etchant solution to remove completely or partially a thermal silicon oxide layer, followed by exposure of the topside and the backside to a cleaning solution. The cleaning solution contains ammonium hydroxide, hydrogen peroxide, DI water, and optionally a chelating agent, and a surfactant. The wet clean chamber is integrated with the dry strip chamber and contained in a single wafer processing system.

Abstract: A semiconductor device is formed by forming a second trench 120 at the base of a first trench 18, depositing insulator 124 at the base of the second trench 120, and then etching cavities 26 laterally from the sidewalls of the second trench, but not the base which is protected by insulator 124. The invention may in particular be used to form semiconductor devices with cavities under the active components, or by filling the cavities to form silicon on insulator or silicon on conductor devices.

Abstract: An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.

Abstract: The present invention discloses an integration structure of a semiconductor circuit and microprobe sensing elements and a method for fabricating the same. In the method of the present invention, a semiconductor circuit is fabricated on one surface of a semiconductor substrate, and the other surface of the semiconductor substrate is etched to form a microprobe structure for detect physiological signals. Next, a deposition method is used to sequentially form an electrical isolated layer and an electrical conductive layer on the microprobes. Then, an electrical conductive material is used to electrically connect the electrical conductive layer with the electrical pads of the semiconductor circuit. Thus is achieved the integration of a semiconductor circuit and microprobe sensing elements in an identical semiconductor substrate with the problem of electric electrical isolated being solved simultaneously.

Abstract: Method for recovering treated metal silicide surfaces or layers are provided. In at least one embodiment, a substrate having an at least partially oxidized metal silicide surface disposed thereon is cleaned to remove the oxidized regions to provide an altered metal silicide surface. The altered metal silicide surface is then exposed to one or more silicon-containing compounds at conditions sufficient to recover the metal silicide surface.

Abstract: Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a layer of ruthenium near the silicon nitride surface. The ruthenium is a good electrical conductor and it responds differently from Ta and TaN to certain etchants. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”. Thus, said included layer of ruthenium may be used as an etch stop layer during the etching of Ta and/or TaN while the latter materials may be used to form a hard mask for etching the ruthenium without significant corrosion of the silicon nitride surface.

Abstract: The present invention relates to a solution for treating a surface of a substrate for use in a semiconductor device. More particularly, the present invention relates to a liquid rinse formulation for use in semiconductor processing, wherein the liquid formulation contains: i. a surface passivation agent; and ii. an oxygen scavenger, wherein the pH of the rinse formulation is 8.0 or greater.

Abstract: A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first dopant type on the fins on the first side of the structure. The method further includes annealing the dopant material such that the first dopant type diffuses into the fins on the first side of the structure. The method further includes protecting the first dopant type from diffusing into the fins on the second side of the structure during the annealing.

Abstract: The invention concerns a manufacturing process, and the related micromachined capacitive ultra-acoustic transducer, that uses commercial silicon wafer 8 already covered on at least one or, more preferably, on both faces by an upper layer 9 and by a lower layer 9? of silicon nitride deposited with low pressure chemical vapour deposition technique, or deposition LPCVD deposition. One of the two layers 9 or 9? of silicon nitride, of optimal quality, covering the wafer 8 is used as emitting membrane of the transducer. As a consequence, the micro-cell array 6 forming the CMUT transducer is grown onto one of the two layers of silicon nitride, i.e. it is grown at the back of the transducer with a sequence of steps that is reversed with respect to the classical technology.

Abstract: A method of forming a vapor thin film is provided, which includes loading a substrate into a chamber, adsorbing a source gas on the substrate by supplying the source gas into the chamber, and forming the thin film on the substrate by supplying a reaction gas into the chamber, wherein the forming of the thin film on the substrate is proceeded under an electric field formed in one direction on the substrate by applying a bias to the substrate.

Abstract: A method for producing a semiconductor includes providing a p-doped semiconductor body having a first side and a second side; implanting protons into the semiconductor body via the first side to a target depth of the semiconductor body; bonding the first side of the semiconductor body to a carrier substrate; forming an n-doped zone in the semiconductor body by heating the semiconductor body such that a pn junction arises in the semiconductor body; and removing the second side of the semiconductor body at least as far as a space charge zone spanned at the pn junction.

Abstract: Various embodiments may be used for laser-based modification of target material of a workpiece while advantageously achieving improvements in processing throughput and/or quality. Embodiments of a method of processing may include focusing and directing laser pulses to a region of the workpiece at a pulse repetition rate sufficiently high so that material is efficiently removed from the region and a quantity of unwanted material within the region, proximate to the region, or both is reduced relative to a quantity obtainable at a lower repetition rate. In at least one embodiment, an ultrashort pulse laser system may include at least one of a fiber amplifier or fiber laser. Various embodiments are suitable for at least one of dicing, cutting, scribing, and forming features on or within a semiconductor substrate.

Abstract: A method of manufacturing microstructures is disclosed, the method comprising a applying a mask to substrate; forming a pattern in the mask; processing the substrate according to the pattern; and mechanically removing the mask from the substrate. A polymer mask is disclosed for manufacturing micro scale structure, the polymer mask comprising a thin, preferably ultra thin flexible film. A method of manufacturing an integrated circuit is disclosed, the method comprising forming a plurality of isolated semiconductor devices on a common substrate; and connecting some of the devices. Apparatus for manufacturing microstructures is disclosed comprising: a mechanism for coating a mass substrate to create a structure; a mechanism for removing a mask from the substrate; and processing apparatus.

Abstract: A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The nanolayer deposition process is a cyclic sequential deposition process, comprising the first step of introducing a first plurality of precursors to deposit a thin film with the deposition process not self-limiting, then a second step of purging the first set of precursors and a third step of introducing a second plurality of precursors to modify the deposited thin film. The deposition step in the NLD process using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film such as a modification of film composition, a doping or a removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film.

Abstract: An assembly including a main wafer having a body with a front side and a back side, and a handler wafer, is obtained. The main wafer has a plurality of blind electrical vias terminating above the back side. The blind electrical vias have conductive cores with surrounding insulator adjacent side and end regions of the cores. The handler wafer is secured to the front side of the body of the main wafer. An additional step includes exposing the blind electrical vias on the back side. The blind electrical vias are exposed to various heights across the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer.

Abstract: A printing screen which, in one embodiment, is adapted to print resistors on a substrate including conductors. An emulsion material covers at least a first area of the screen and at least a second area of the screen defines a region of the screen through which a thick film paste material passes and is deposited onto the substrate to form the resistors. A pattern of recesses, defined in the bottom surface of the layer of emulsion material, matches the pattern of conductors on the substrate. When the screen is lowered onto or near the substrate, the conductors are fitted into the respective recesses to assure that during printing the screen lays flat against the substrate irrespective of the number, size, or location of the conductors on the substrate for forming resistors of uniform thickness and thus uniform resistance.

Abstract: A disclosed valve comprises a first valve body including first and second openings that permit gaseous communication between a chamber and an evacuation apparatus; a sealing valve element that moves near/away from the second opening to open/close the second opening; a sealing member provided in the sealing valve element to seal the second opening when the sealing valve element closes the second opening; a valve element retreat area that is provided in an inner wall of the first valve body away from the second opening, and shields the sealing member from an inside of the first valve body when the sealing valve element is moved to the valve element retreat area; and a first pivot shaft that pivots the sealing valve element so that the sealing valve element may be located in one of the second opening and the valve element retreat area.

Abstract: Methods, devices, systems and/or articles related to techniques for forming a graphene film on a substrate, and the resulting graphene layers and graphenated substrates are generally disclosed. Some example techniques may be embodied as methods or processes for forming graphene. Some other example techniques may be embodied as devices employed to manipulate, treat, or otherwise process substrates, graphite, graphene and/or graphenated substrates as described herein. Graphene layers and graphenated substrates produced by the various techniques and devices provided herein are also disclosed.

Abstract: A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.

Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.

Abstract: An etching solution contains water, nitric acid, hydrofluoric acid, and sulphuric acid. More specifically it contains 15 to 40% by weight of nitric acid, 10 to 41% by weight of sulphuric acid and 0.8 to 2.0% by weight of hydrofluoric acid. The etching solution is used for etching silicon and to etching methods for silicon wafers.

Abstract: A method for working a nitride semiconductor substrate, comprising the steps of: preparing a disk-shaped nitride semiconductor substrate comprising a plurality of striped regions having defect concentration regions in which crystal defect density is higher than in surrounding low defect regions; and forming a cut-out at a specific location along the edge of the nitride semiconductor substrate, using as a reference the direction in which at least one from among the plurality of striped regions extends.

Abstract: Provided are a wafer carrier transferring apparatus and a semiconductor conductor fabricating system having the wafer carrier transferring apparatus. The wafer carrier transferring apparatus comprises an arm pocket portion supporting a wafer carrier and a pocket end portion detachably coupled to opposite ends of the arm pocket portion.

Abstract: Provided are a unit for supplying chemical liquid, and apparatus and method for treating a substrate using the unit. A pre-wet, photoresist, and edge bead removal nozzles are mounted on a single nozzle body. Therefore, the equipment installing space can be saved as compared with a case where the nozzles are installed on respective nozzle arms, thereby making better use of a space for installing equipments.

Abstract: A method to form a barrier layer and contact plug using a touch up RIE. In a first embodiment, we form a first barrier layer over the dielectric layer and the substrate in the contact hole. The first barrier layer is comprised of Ta. A second barrier layer is formed over the first barrier layer. The second barrier layer is comprised of TaN or WN. We planarize a first conductive layer to form a first contact plug in the contact hole. We reactive ion etch (e.g., W touch up etch) the top surfaces using a Cl and B containing etch. Because of the composition of the barrier layers and RIE etch chemistry, the barrier layers are not significantly etched selectively to the dielectric layer. In a second embodiment, a barrier film is comprised of WN.

Abstract: A method for processing a semiconductor fin structure is disclosed. The method includes thermal annealing a fin structure in an ambient containing an isotope of hydrogen. Following the thermal annealing step, the fin structure is etched in a crystal-orientation dependent, self-limiting, manner. The crystal-orientation dependent etch may be selected to be an aqueous solution containing ammonium hydroxide (NH4OH). The completed fin structure has smooth sidewalls and a uniform thickness profile. The fin structure sidewalls are {110} planes.

Abstract: A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions.

Abstract: A chemical mechanical polishing composition useful for chemical mechanical polishing of a patterned semiconductor wafer containing a nonferrous metal. The chemical mechanical polishing composition comprises an inhibitor for the nonferrous metal; a copolymer of poly(ethylene glycol)methyl ether (meth)acrylate and 1-vinylimidazole; and water.

Abstract: The invention is directed to a method of chemically-mechanically polishing a a surface of a substrate, comprising contacting a surface of a substrate comprising nickel-phosphorous with a chemical-mechanical polishing composition comprising wet-process silica, an agent that oxidizes nickel-phosphorous, and an aminopolycarboxylic acid, wherein the polishing composition has a pH of about 1 to about 5, and abrading at least a portion of the nickel-phosphorous to polish the substrate.

Abstract: A method for chemical mechanical polishing of mirror structures. Such mirror structures may be used for displays (e.g., LCOS, DLP), optical devices, and the like. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method forms a first dielectric layer overlying the semiconductor substrate and forms an aluminum layer overlying the dielectric layer. The aluminum layer has a predetermined roughness of greater than 20 Angstroms RMS. The method patterns the aluminum layer to expose portions of the dielectric layer. The method includes forming a second dielectric layer overlying the patterned aluminum layer and exposed portions of the dielectric layer. The method removes a portion of the second dielectric layer.

Abstract: A method for forming semiconductor devices is provided. A wafer with a patterned photoresist mask over the wafer, wherein the patterned photoresist mask has patterned photoresist mask features with scum at bottoms of the photoresist mask features is provided. The scum is removed from the bottoms of the photoresist mask features, comprising: providing a descumming gas consisting essentially of helium and forming the helium into a plasma, which removes the scum.

Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.

Abstract: A wafer processing method is provided comprising the steps of: holding a wafer (20) having devices formed on its front surface (21) so that a back surface (22) of the wafer is exposed; grinding the back surface of the wafer to form a brittle fracture layer (Z) on the back surface; and polishing the back surface of the wafer entirely so that the brittle fracture layer remains partially. It is possible to improve the strength of the wafer and reduce its surface roughness while allowing utilization of a gettering effect. It is also preferable to remove only an outermost layer of the back surface of the wafer. Further, it is preferable that the wafer is polished by at least one of wet polishing, dry polishing, wet etching and dry etching.

Abstract: It is an object to provide a method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even when a single crystal semiconductor substrate in which crystal defects exist is used. Such an SOI substrate can be manufactured through the steps of forming a single crystal semiconductor layer which has an extremely small number of defects over a single crystal semiconductor substrate by an epitaxial growth method; forming an oxide film on the single crystal semiconductor substrate by thermal oxidation treatment; introducing ions into the single crystal semiconductor substrate through the oxide film; bonding the single crystal semiconductor substrate into which the ions are introduced and a semiconductor substrate to each other; causing separation by heat treatment; and performing planarization treatment on the single crystal semiconductor layer provided over the semiconductor substrate.

Abstract: A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.

Abstract: In an apparatus for etching a semiconductor wafer or sample (101), the semiconductor wafer or sample is placed on a sample holder (104) disposed in a first chamber (103). The combination of the semiconductor wafer or sample and the sample holder is enclosed within a second chamber (130) inside the first chamber. Gas is evacuated from the second chamber and an etching gas is introduced into the second chamber, but not into the first chamber, to etch the semiconductor wafer or sample.

Abstract: A system and method is disclosed for reducing etch sequencing induced downstream dielectric defects produced in a SOG planarization process used in high volume semiconductor manufacturing. Three factors have been identified as causes of the defects. The three factors are: (1) phosphorus-doping in the base dielectric, and (2) using for SOG etchback an etch tool that was last used for a bond pad etch process, and (3) residual metal contaminants in the etch chamber used for the SOG etchback. Elimination of any one of these three factors eliminates the defects.

Abstract: The invention includes methods of selectively removing metal-containing copper barrier materials (such as tantalum-containing materials, titanium-containing materials and tungsten-containing materials) relative to oxide (such as silicon dioxide) and/or copper. The selective removal can utilize etchant solutions containing hydrofluoric acid and one or more carboxylic acids. The etchant solutions can contain less than 6 weight percent water, and/or can have a dielectric constant below 40.

Abstract: A method of manufacturing an ultra thin integrated circuit comprises providing a substrate having a front side, a back side, and an edge extending from the front side to the back side; creating a defect layer in the substrate; forming semiconductor devices proximate the front side after creating the defect layer; and cleaving proximate the defect layer after forming the semiconductor devices. Other methods and apparatus are also provided.

Abstract: An aspect of the invention provides a method for polishing a patterned semiconductor wafer containing a copper interconnect metal with a polishing pad. The method includes the following: a) providing an aqueous polishing solution, the polishing solution containing an benzotriazole (BTA) inhibitor and a copper complexing compound and water; b) polishing the patterned wafer with the aqueous polishing solution and the polishing pad in a manner that dissolves copper into Cu+1 ions, the Cu+1 ions and BTA inhibitor having a concentration where [BTA]*[Cu+1]> than Ksp for Cu-BTA precipitate if the aqueous solution did not contain the complexing compound; and c) oxidizing at least some of the copper ions to prevent the polishing from precipitating the Cu-BTA precipitate.

Abstract: Provided may be a slurry composition for chemical mechanical polishing (CMP) and a CMP method using the same. For example, the slurry composition may include a first polishing inhibitor including at least one of PO43? or HPO42? and a second polishing inhibitor, which may be a C2-C10 hydrocarbon compound having —SO3H or —OSO3H. By using the slurry composition for CMP and a CMP method using the same, increased selectivity to SiN may be obtained.

Abstract: A method for fabricating a semiconductor device includes forming a dielectric film containing a porogen material above a substrate; removing a portion of the porogen material contained in the dielectric film so as to make a concentration of the porogen material higher in a part on a lower side of the dielectric film than in another part on a higher side of the dielectric film; forming an opening halfway in the dielectric film from which a portion of the porogen material has been removed to leave the dielectric film below a bottom of the opening; removing or polymerizing a remainder of the porogen material contained in the dielectric film; and etching the bottom of the opening after removing or polymerizing the remainder of the porogen material.

Abstract: A silicon wafer laser processing method for forming a deteriorated layer along dividing lines formed on a silicon wafer in the inside of the silicon wafer by applying a laser beam along the dividing lines, wherein the wavelength of the laser beam is set to 1,100 to 2,000 nm.

Abstract: Method for recovering treated metal silicide surfaces or layers are provided. In at least one embodiment, a substrate having an at least partially oxidized metal silicide surface disposed thereon is cleaned to remove the oxidized regions to provide an altered metal silicide surface. The altered metal silicide surface is then exposed to one or more silicon-containing compounds at conditions sufficient to recover the metal silicide surface.