Abstract: Methods for forming dual damascene structures in low-k dielectric materials that facilitate reducing photoresist poison issues are provided herein. In some embodiments, such methods may include plasma etching a via through a first mask layer into a low-k dielectric material disposed on a substrate. The first mask layer may then be removed using a process including exposing the first mask layer to a first plasma comprising an oxygen containing gas and at least one of a dilutant gas or a passivation gas, and subsequently exposing the first mask layer to a second plasma comprising an oxygen containing gas and formed using one of either plasma bias power or plasma source power. An anti-reflective coating may then be deposited into the via and atop the low-k dielectric material. A trench may then be plasma etched through a second mask layer formed atop the anti-reflective coating into the low-k dielectric material.

Abstract: A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.

Abstract: A micro-mirror manufacturing method for dividing a plurality of micro-mirror devices each having at least one mirror, formed on a semiconductor wafer into individual micro-mirror devices can be provided. The manufacturing method comprises a step of depositing an inorganic protection layer on the mirror before separating the micro-mirror devices from the wafer and a step of removing the inorganic protection layer after separating the micro-mirror devices from the wafer.

Abstract: The fluid-confining apparatus includes at least a substrate holder, at least a confining fluid supplying tube, at least a confining fluid recovering tube, at least a process fluid supplying tube, and at least a process fluid recovering tube. The process fluid supplying tube supplies at least a process fluid, and makes the process fluid contact with at least a treatment region of a wafer. The confining fluid supplying tube continuity supplies at least a confining fluid. The confining fluid does not dissolve the process fluid. The flowing confining fluid can contact with at least a non-treatment region of the wafer, and confines the process fluid into a predetermined space.

Abstract: A method for using a film formation apparatus for a semiconductor process to form a thin film on a target substrate inside a reaction chamber includes performing a cleaning process to remove a by-product film deposited on a predetermined region in a gas route from a film formation gas supply system, which supplies a film formation gas contributory to film formation, through the reaction chamber to an exhaust system, by alternately repeating an etching step and an exhaust step a plurality of times in a state where the reaction chamber does not accommodate the target substrate. The etching step includes supplying a cleaning gas in an activated state for etching the by-product film onto the predetermined region, thereby etching the by-product film. The exhaust step includes stopping supply of the cleaning gas and exhausting gas by the exhaust system from a space in which the predetermined region is present.

Abstract: A method for manufacturing a semiconductor device comprises dry-etching a thin film using a resist mask carrying patterns in which at least one of the width of each pattern and the space between neighboring two patterns ranges from 32 to 130 nm using a halogenated carbon-containing compound gas with the halogen being at least two members selected from the group consisting of F, I and Br. The ratio of at least one of I and Br is not more than 26% of the total amount of the halogen atoms as expressed in terms of the atomic compositional ratio to transfer the patterns onto the thin film. Such etching of a thin film avoids causing damage to the resist mask used. The resulting thin film carrying the transferred patterns is used as a mask for subjecting the underlying material to dry-etching.

Abstract: A method of fabricating a semiconductor device is disclosed, by which thickness of a gate oxide layer can be controlled for uniformity. Embodiments include sequentially forming a pad oxide layer and a nitride layer over a semiconductor substrate having an epi-layer grown thereon, the semiconductor substrate having a backside over which a backside nitride layer and a backside oxide layer are formed, forming a trench on the semiconductor substrate, depositing an oxide layer over a front side the semiconductor substrate to fill the trench with the oxide layer, selectively etching the oxide layer, performing a chemical mechanical polishing process on the front side of the semiconductor substrate, performing a chemical mechanical polishing process on the backside of the semiconductor substrate, and forming a gate oxide layer over the semiconductor substrate.

Abstract: In the manufacture of integrated circuits, reactive compositions that include a reactive etchant species and an oxygen-containing species can provide selective removal of target material and can reduce contamination of gas delivery lines.

Abstract: Methods are provided for removing an oxide layer from a metal pad on an integrated circuit in order to reduce contact resistance. In one embodiment, aluminum oxide, on the surface of a bond pad substantially comprised of aluminum, is reacted with a first chemical agent to form an inorganic salt, and the inorganic salt is then reacted with a second chemical agent leaving a substantially bare, that is, unoxidized, aluminum surface.

Abstract: High aspect ratio contact openings are etched while preventing bowing or bending of the etch profile by forming a highly conductive thin film on the side wall of each contact opening. The conductivity of the thin film on the side wall is enhanced by ion bombardment carried out periodically during the etch process.

Abstract: A method for fabricating a microelectronic structure provides for forming a backfilling material layer at least laterally adjacent, and preferably laterally adjoining, a resist layer located over a substrate. Preferably, the resist layer comprises a surface treated resist layer. Optionally, the backfilling material layer may be surface treated similarly to the surface treated resist layer. Under such circumstances: (1) surface portions of the backfilling material layer and resist layer; and (2) remaining portions of the backfilling material layer and resist layer, may be sequentially stripped using a two step etch method, such as a two step plasma etch method. Alternatively, a surface portion of the surface treated resist layer only may be stripped while using a first etch method, and the remaining portions of the resist layer and backfilling material layer may be planarized prior to being simultaneously stripped while using a second etch method.

Abstract: The present invention provides processes and equipments for safely and easily preparing an F2-containing gas, as well as processes and equipments for surface modification using the F2-containing gas prepared. According to the present invention, a gas containing a fluoro compound that is easier to handle than F2 is supplied and the fluoro compound is excited and decomposed to convert it into F2 gas before surface modification and then used for surface modification. According to the present invention, there is no necessity of providing, storing and transporting a large amount of F2 gas in advance because a necessary amount of F2 gas is obtained immediately before surface modification.

Abstract: Combinatorial processing including rotation and movement within a region is described, including defining multiple regions of at least one substrate, processing the multiple regions of the at least one substrate in a combinatorial manner, rotating a head in one of the multiple regions to perform the processing, and repositioning the head relative to the one of the multiple regions while rotating the head during the processing.

Abstract: A method of forming a feature on a multi-layer semiconductor is disclosed. A pattern feature is formed in an uppermost layer of the multi-layer semiconductor. The multilayer semiconductor is etched with a SO2 based chemistry to extend the pattern feature to a lower layer of the multi-layer semiconductor. Use of the SO2 based chemistry for etch eliminates features roughness associated with conventional CO, SiCL4 or CO2-based chemistries.

Abstract: A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.

Abstract: A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.

Abstract: A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.

Abstract: In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle.

Abstract: A method for etching wafers using advanced patterning film (APF) to reduce bowing and improve bottom-to-top ratios includes providing a wafer having an APF layer into a processing chamber, wherein the processing chamber is configured with a power source operating at about 162 MHz, supplying a process gas into the chamber, applying a source power using the 162 MHz power source, and applying a bias power to the wafer. The process gas comprises hydrogen gas (H2), nitrogen gas (N2), and carbon monoxide gas (CO). The ratio of H2:N2 is about 1:1. Additionally, the wafer temperature is adjusted to improve the etching characteristics.

Abstract: The present invention provides a method for producing a shallow trench isolation, comprises: forming a plurality of first grooves on a silicon substrate with a mask etching method, wherein the silicon substrate comprises a silicon layer, an oxide layer and a first polysilicon layer; conducting oxidation process on an inner peripheral portion of the second grooves to form an insulting layer. The depth of the insulating layer on the periphery of the first polysilicon layer formed by the oxidation process is larger than the depths of the insulating layers that are formed on the silicon layer and on the oxidation layer through the oxidation process; filling high density plasma oxide layer into the second grooves to form a plurality of high density plasma oxide layer fillers; removing the first polysilicon layer by etching; covering the silicon substrate with a second polysilicon layer by deposition; and polishing the second polysilicon layer to form a plurality of self-aligned floating gate.

Abstract: A method of manufacturing a semiconductor device has forming an interlayer insulating film over a wiring layer, forming an opening in the interlayer insulating film, performing a first plasma treatment using a gas including hydrogen or ammonia, performing a second plasma treatment with a gas including fluorocarbon after the first plasma treatment.

Abstract: The purpose of the present invention is to stabilize the polishing film thickness during the overpolishing following the removal of barrier metal in Cu-CMP (chemical mechanical polishing). To this end, a table in which the relationship between wire perimeter and overpolishing process polishing rate is created. The polishing time is calculated based on the wire perimeter in determining the overpolishing time after the removal of barrier metal in Cu-CMP to stabilize the overpolishing film thickness.

Abstract: A process is taught for producing a smooth, damage-free surface on a SiC wafer, suitable for subsequent epitaxial film growth or ion implantation and semiconductor device fabrication. The process uses certain oxygenated solutions in combination with a colloidal abrasive in order to remove material from the wafer surface in a controlled manner. Hydrogen peroxide with or without ozonated water, in combination with colloidal silica or alumina (or alternatively, in combination with HF to affect the oxide removal) is the preferred embodiment of the invention. The invention also provides a means to monitor the sub-surface damage depth and extent since it initially reveals this damage though the higher oxidation rate and the associated higher removal rate.

Abstract: The present invention provides a technique for realizing highly flat surface of a semiconductor integrated circuit employing copper as a wiring metal. The present invention provides a polishing composition containing a neutralized carboxylic acid, an oxidizer and water, wherein a part of the carboxylic acid is an alicyclic resin acid (A) and the pH value is within a range of from 7.5 to 12. The alicyclic resin acid is preferably at least one type selected from the group consisting of abietic acid, an isomer of abietic acid, pimaric acid, an isomer of pimaric acid and derivatives of these, or a rosin. Further, the present invention provides a polishing method of semiconductor integrated circuit surface in which a copper film formed on a surface having a groove for wiring, by using the polishing composition, and the present invention provides a copper wiring for semiconductor integrated circuit formed by this polishing method.

Abstract: In a method for manufacturing a micromechanical structure, first a two-dimensional structure is formed in a substrate. The two-dimensional structure is deflected from the substrate plane by action of force and fixed in the deflected state.

Abstract: One embodiment of the present invention relates to a method of processing a semiconductor device. During the method an amorphization implant is performed to amorphize a selected region of a semiconductor structure. The amorphized selected region is then removed by performing a recess etch that is selective thereto. Other methods and systems are also disclosed.

Abstract: Contact spatial-frequency doubling technology is invented to pattern a contact-hole array and a row/column (or multiple isolated rows/columns) of contact holes with their density increased to twice of the maximum density achievable during one exposure with a conventional lithographic technology. These contact frequency doubling processes can be used not only in contact-hole patterning for both memory and logic devices, but also applicable for doubling the density of epi-Si (or epi-SiGe, epi-Ge) columns. If introduced to fabricate vertical MOSFET devices wherein the epi-columns act as the transistor body/channel and drain/source is designed in the vertical way, the epi-column doubling technology can enable cost-effective fabrication processes for high-density 4F2 DRAM and vertical CMOS applications.

Abstract: A slurry composition includes an acidic aqueous solution and one or both of, an amphoteric surfactant and a glycol compound. Examples of the amphoteric surfactant include a betaine compound and an amino acid compound, and examples of the amino acid compound include lysine, proline and arginine. Examples of the glycol compound include diethylene glycol, ethylene glycol and polyethylene glycol.

Abstract: An apparatus for feeding slurry to an external device. The apparatus includes a preparation tank for preparing the slurry. A circulation pipe is connected to the preparation tank to circulate the slurry. A feeding pipe is connected between the preparation tank and the external device to feed the external device with the slurry. A pump sends the chemical solution in the preparation tank to the circulation pipe and the feeding pipe. A concentration detector is arranged downstream to the pump to detect the concentration of the slurry. A controller controls the concentration of the chemical solution in the preparation tank in accordance with the detection value of the concentration detector and controls the feeding of the chemical solution.

Abstract: The present invention relates to a method for manufacturing a high flatness silicon wafer comprising (S21) slicing a silicon single crystal ingot to produce a wafer; (S22) chamfering an edge of the wafer sliced from the ingot; (S23) lapping the edge-chamfered wafer; (S24) etching the lapped wafer; (S25) grinding the etched wafer; (S26) slight-etching the ground wafer using an alkali aqueous solution to remove a surface degraded layer generated on the ground wafer; (S27) polishing one or two surfaces of the slight-etched wafer; and (S28) cleaning the polished wafer.

Abstract: A substrate is processed in a process chamber comprising a substrate support having a receiving surface for receiving a substrate so that a front surface of the substrate is exposed within the chamber. An energized process gas is used to process the front surface of the substrate. A peripheral edge of the backside surface of the substrate is cleaned by raising the substrate above the receiving surface of the substrate support to a raised position, and exposing the backside surface of the substrate to an energized cleaning gas.

Abstract: An effective electropurge process and apparatus for wet processing of semiconductor wafers applies electrical charges to the wafer surface with an ample voltage sufficient to provide an effective field intensity which can substantially eliminate intolerable sub-0.05 micron “killer” defects when making highly advanced microchips with a feature size or line width less than 0.15 micron. The process can be used with frequent voltage reversal for automated wet-batch cleaning operations using cassettes that hold 10 to 50 wafers at a time and in various other operations involving megasonic transducers, mechanical brush scrubbers, laser cleaners and CMP equipment. The electropurge process is primarily intended for Fab plants where large wafers with a diameter of 200 to 400 mm require 250 to 350 steps including many dry layering, patterning and doping operations and at least 30 wet processing steps.

Abstract: A method for fabricating substrate material to include trenches and unreleased beams with submicron dimensions includes etching a first oxide layer on the substrate to define a first set of voids in the first oxide layer to expose the substrate. A second oxide layer is accreted to the first oxide layer to narrow the first set of voids to become a second set of voids on the substrate. A polysilicon layer is deposited over the second oxide layer, the first oxide layer and the substrate. A third set of voids is etched into the polysilicon layer. Further etching widens the third set of voids to define a fourth set of voids to expose the first oxide layer and the substrate. The first oxide layer and the substrate is deeply etched to define beams and trenches in the substrate.

Abstract: A method for manufacturing a semiconductor device includes mounting a target substrate on a mounting table in a processing chamber; performing a plasma etching process via a resist mask; and performing an ashing process for removing the resist mask in the same processing chamber. Further, a temperature control of the target substrate is performed to increase the temperature of the target substrate higher than a temperature level in the plasma etching process in the ashing process.

Abstract: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered with the resist layer 18 formed thereon, and then the resist layer 18 is removed with a chemical solution containing an organic solvent such as isopropyl alcohol as a main component. Subsequently, a third oxide film 22 having different thickness than the second oxide film 16 is formed in the first region 13a.

Abstract: A semiconductor device, and a method for manufacturing the semiconductor device, has forming a layer having an in-plane polishing amount distribution, and setting the approximate uniform thickness of the layer over the whole semiconductor wafer by the process such that the in-plane polishing amount distribution is approximately uniform.

Abstract: A method and apparatus for processing a substrate in a capacitively-coupled plasma processing system having a plasma processing chamber and at least an upper electrode and a lower electrode. The substrate is disposed on the lower electrode during plasma processing. The method includes providing at least a first RF signal, which has a first RF frequency, to the lower electrode. The first RF signal couples with a plasma in the plasma processing chamber, thereby inducing an induced RF signal on the upper electrode. The method also includes providing a second RF signal to the upper electrode. The second RF signal also has the first RF frequency. A phase of the second RF signal is offset from a phase of the first RF signal by a value that is less than 10%. The method further includes processing the substrate while the second RF signal is provided to the upper electrode.

Abstract: A method for semiconductor structure formation includes: providing a substrate; forming a first lower mask layer on the substrate; forming a first patterned mask on the first lower mask layer; forming a second lower mask layer on the first lower mask layer and overlaying the first patterned mask; forming a second patterned mask on the second lower mask layer without the second patterned mask overlapping the first patterned mask; etching and undercutting the first lower mask layer and the second lower mask layer to form the third patterned mask with the first patterned mask and the second patterned mask; etching the substrate by using the third patterned mask to form a plurality of islands; and removing the third patterned mask.

Abstract: An antenna array for a radio frequency plasma process chamber including, an array of electrodes, an array of dielectric tubes concentrically disposed about each electrode tube to define a chamber configured to be at atmospheric pressure between an outer surface of each electrode tube and an inner surface of the corresponding dielectric tube, and a hermetic seal between each dielectric tube and the plasma process chamber configured to allow a vacuum or low pressure in the plasma process chamber.

Abstract: A method for providing CMP slurries for copper CMP that have improved pot life by ameliorating hydrogen peroxide degradation in slurries. The method comprises a composition that has a transition metal content of less than about 5 parts per million (ppm), preferably less than about 2 ppm. Preferably the method comprises a composition containing less than about 2 ppm of yttrium, zirconium, and/or iron.

Abstract: A method for decapsulating a package is provided. The method comprises steps of providing a package having a chip therein, wherein the chip has an active surface and a rear surface. Further, the package further comprises a heat sink, a plurality of solder bumps, a substrate, an underfill and a plurality of solder balls. The method further comprises removing the heat sink and removing the substrate together with the solder balls. A dry etching process is performed to remove a portion of the underfill. A wet etching process is performed to remove the rest portion of the underfill. A thermal process solder bump removal process is performed to melt the solder bumps and then a solder bump removal process is performed to remove the melted solder bumps from the active surface of the chip.

Abstract: The present invention relates to a novel etching solution suitable for characterizing defects on semiconductor surfaces, including silicon germanium surfaces, as well as a method for treating semiconductor surfaces with an etching solution as disclosed herein. This novel etching solution is chromium-free and enables a highly sufficient etch rate and highly satisfactory etch results.

Abstract: An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench. Chemical mechanical polishing is executed to expose the insulating surface of the substrate and leave a portion of the conductive film in the trench. The surface of the substrate having the exposed conductive film in the trench and the exposed insulating surface is exposed to first liquid. After being exposed to the first liquid, the surface of the substrate is exposed to second liquid. The first liquid is either solution which contains at least one first substance selected from a first group consisting of benzotriazole, derivative of benzotriazole and interfacial active agent, or water. The second solution is solution which contains the first substance at a density higher than a density of the first liquid.

Abstract: The present invention relates to a method for fabricating a metal interconnection line with use of a barrier metal layer formed in a low temperature. The method includes the steps of: forming an inter-layer insulation layer on a substrate; etching predetermined regions of the inter-layer insulation layer to form a plurality of contact openings; forming an ohmic metal layer on the contact openings and the etched inter-layer insulation layer; forming a seed layer on the ohmic metal layer; forming a metal layer on the seed layer and nitriding the metal layer in a repeated number of times to form a barrier metal layer; and forming a metal interconnection line on the barrier metal layer by burying the contact openings.

Abstract: A method in a plasma processing system for etching a feature through a given layer on a semiconductor substrate. The method includes placing the substrate in a plasma processing chamber of the plasma processing system. The method also includes flowing an etchant gas mixture into the plasma processing chamber, the etchant gas mixture being configured to etch the given layer. The method additionally includes striking a plasma from the etchant source gas. Furthermore, the method includes etching the feature at least partially through the given layer while applying a bias RF signal to the substrate, the bias RF signal having a bias RF frequency of between about 45 MHz and about 75 MHz. The bias RF signal further has a bias RF power component that is configured to cause the etch feature to be etched with an etch selectivity to a second layer of the substrate that is higher than a predefined selectivity threshold.

Abstract: A substrate comprising an oxide layer covering a nitride layer, is etched in a process zone of a substrate processing chamber. A process gas comprising H2 gas is introduced into the process zone, and the process gas is energized to etch through the oxide layer to at least partially expose the nitride layer. The energized process gas has a selectivity of etching the oxide layer to the nitride layer of at least about 25:1.

Abstract: A wet processing system detects a globule of a process solution in a drippy or dripping state from the tip of any one of process solution pouring nozzles being moved to a pouring position for pouring the process solution onto a substrate by obtaining image data on the process solution pouring nozzle, and takes proper measures to prevent the process solution from dripping. A wet processing system 1 pours a process solution, such as a resist solution, through one of process solution pouring nozzles 10 onto a surface of a substrate, such as a wafer W, held substantially horizontally by a substrate holding device 41 surrounded by a cup 5 to process the surface by a wet process. A nozzle carrying mechanism 10a carries the process solution pouring nozzles 10 between a home position on a nozzle bath 14 and a pouring position above the substrate held by the substrate holding device 41. An optical image of the tips of the process solution pouring nozzles 10 is obtained by an image pickup means, such as a camera 17.

Abstract: An apparatus for etching a semiconductor substrate may include a bath, a reaction preventing layer, and a nozzle. The bath may receive a chemical solution. Grooves may be formed at the inner wall of the bath. The reaction preventing layer may be formed on the inner wall and in the grooves of the bath to reduce or prevent a chemical reaction between the chemical solution and the bath. The nozzle may supply the chemical solution to the bath. In a method of etching a semiconductor substrate, the semiconductor substrate having trench structures and an insulation layer pattern may be prepared. The semiconductor substrate may then be dipped into the bath having the reaction preventing layer in which the chemical solution is received. The semiconductor substrate may be reacted with the chemical solution by blocking the chemical reaction between the chemical solution and the bath to etch the insulation layer pattern and the trench structure at a uniform rate.

Abstract: There is provided a process for forming a contained second layer over a first layer, including the steps: forming the first layer having a first surface energy; forming an intermediate layer over and in direct contact with the first layer, said intermediate layer having a second surface energy which is lower than the first surface energy; removing selected portions of the intermediate layer to form a pattern comprising uncovered areas of the first layer and covered areas of the first layer; and forming a contained second layer over the uncovered areas of the first layer. There is also provided an organic electronic device made by the process.

Abstract: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.